WO2006057730A3 - Network device architecture for consolidating input/output and reducing latency - Google Patents

Network device architecture for consolidating input/output and reducing latency Download PDF

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Publication number
WO2006057730A3
WO2006057730A3 PCT/US2005/037239 US2005037239W WO2006057730A3 WO 2006057730 A3 WO2006057730 A3 WO 2006057730A3 US 2005037239 W US2005037239 W US 2005037239W WO 2006057730 A3 WO2006057730 A3 WO 2006057730A3
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WO
WIPO (PCT)
Prior art keywords
ethernet
vls
drop
low latency
behavior
Prior art date
Application number
PCT/US2005/037239
Other languages
French (fr)
Other versions
WO2006057730A2 (en
Inventor
Silvano Gai
Thomas Edsall
Davide Bergamasco
Dinesh Dutt
Flavio Bonomi
Original Assignee
Cisco Tech Inc
Silvano Gai
Thomas Edsall
Davide Bergamasco
Dinesh Dutt
Flavio Bonomi
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cisco Tech Inc, Silvano Gai, Thomas Edsall, Davide Bergamasco, Dinesh Dutt, Flavio Bonomi filed Critical Cisco Tech Inc
Priority to EP05851226.0A priority Critical patent/EP1803257B1/en
Priority to CN200580034646.0A priority patent/CN101040489B/en
Publication of WO2006057730A2 publication Critical patent/WO2006057730A2/en
Publication of WO2006057730A3 publication Critical patent/WO2006057730A3/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/407—Bus networks with decentralised control
    • H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection (CSMA-CD)
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/32—Flow control; Congestion control by discarding or delaying data units, e.g. packets or frames
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/33—Flow control; Congestion control using forward notification
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/39—Credit based
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements

Abstract

The present invention provides methods and devices for implementing a Low Latency Ethernet ('LLE') solution, also referred to herein as a Data Center Ethernet ('DCE') solution, which simplifies the connectivity of data centers and provides a high bandwidth, low latency network for carrying Ethernet and storage traffic. Some aspects of the invention involve transforming FC frames into a format suitable for transport on an Ethernet. Some preferred implementations of the invention implement multiple virtual lanes ('VLs') in a single physical connection of a data center or similar network. Some VLs are 'drop' VLs (1505), with Ethernet-like behavior, and others are 'no-drop' lanes (1510 )with FC-like behavior. Some preferred implementations of the invention provide guaranteed bandwidth based on credits and VL. Active buffer management allows for both high reliability and low latency while using small frame buffers. Preferably, the rules for active buffer management are different for drop and no drop VLs.
PCT/US2005/037239 2004-10-22 2005-10-13 Network device architecture for consolidating input/output and reducing latency WO2006057730A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP05851226.0A EP1803257B1 (en) 2004-10-22 2005-10-13 Network device architecture for consolidating input/output and reducing latency
CN200580034646.0A CN101040489B (en) 2004-10-22 2005-10-13 Network device architecture for consolidating input/output and reducing latency

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US62139604P 2004-10-22 2004-10-22
US60/621,396 2004-10-22
US11/094,877 US7830793B2 (en) 2004-10-22 2005-03-30 Network device architecture for consolidating input/output and reducing latency
US11/094,877 2005-03-30

Publications (2)

Publication Number Publication Date
WO2006057730A2 WO2006057730A2 (en) 2006-06-01
WO2006057730A3 true WO2006057730A3 (en) 2007-03-08

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/037239 WO2006057730A2 (en) 2004-10-22 2005-10-13 Network device architecture for consolidating input/output and reducing latency

Country Status (3)

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US (1) US7830793B2 (en)
EP (1) EP1803257B1 (en)
WO (1) WO2006057730A2 (en)

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