WO2006057647A3 - Decoupling the number of logical threads from the number of simultaneous physical threads in a processor - Google Patents

Decoupling the number of logical threads from the number of simultaneous physical threads in a processor Download PDF

Info

Publication number
WO2006057647A3
WO2006057647A3 PCT/US2004/043036 US2004043036W WO2006057647A3 WO 2006057647 A3 WO2006057647 A3 WO 2006057647A3 US 2004043036 W US2004043036 W US 2004043036W WO 2006057647 A3 WO2006057647 A3 WO 2006057647A3
Authority
WO
WIPO (PCT)
Prior art keywords
threads
logical
physical
thread
state
Prior art date
Application number
PCT/US2004/043036
Other languages
French (fr)
Other versions
WO2006057647A2 (en
Inventor
Per Hammarlund
Alexandre Farcy
Morris Marden
Douglas Carmean
Pierre Michaud
Robert Hinton
Stephan Jourdan
Original Assignee
Intel Corp
Per Hammarlund
Alexandre Farcy
Morris Marden
Douglas Carmean
Pierre Michaud
Robert Hinton
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Per Hammarlund, Alexandre Farcy, Morris Marden, Douglas Carmean, Pierre Michaud, Robert Hinton filed Critical Intel Corp
Priority to JP2006547293A priority Critical patent/JP4599365B2/en
Priority to DE112004002505T priority patent/DE112004002505T5/en
Priority to CN2004800394192A priority patent/CN1926514B/en
Publication of WO2006057647A2 publication Critical patent/WO2006057647A2/en
Publication of WO2006057647A3 publication Critical patent/WO2006057647A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/485—Task life-cycle, e.g. stopping, restarting, resuming execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Abstract

Systems and methods of managing threads provide for supporting a plurality of logical threads with a plurality of simultaneous physical threads in which the number of logical threads may be greater than or less than the number of physical threads. In one approach, each of the plurality of logical threads is maintained in one of a wait state, an active state, a drain state, and a stall state. A state machine and hardware sequencer can be used to transition the logical threads between states based on triggering events and whether or not an interruptible point has been encountered in the logical threads. The logical threads are scheduled on the physical threads to meet, for example, priority, performance or fairness goals. It is also possible to specify the resources that are available to each logical thread in order to meet these and other, goals. In one example, a single. logical thread can speculatively use more than one physical thread, pending a selection of which physical thread should be committed.
PCT/US2004/043036 2003-12-29 2004-12-20 Decoupling the number of logical threads from the number of simultaneous physical threads in a processor WO2006057647A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2006547293A JP4599365B2 (en) 2003-12-29 2004-12-20 Decoupling the number of logical threads from the number of simultaneous physical threads in a processor
DE112004002505T DE112004002505T5 (en) 2003-12-29 2004-12-20 Decouple the number of logical threads from the number of concurrent physical threads in a processor
CN2004800394192A CN1926514B (en) 2003-12-29 2004-12-20 Decoupling the number of logical threads from the number of simultaneous physical threads in a processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/745,527 US7797683B2 (en) 2003-12-29 2003-12-29 Decoupling the number of logical threads from the number of simultaneous physical threads in a processor
US10/745,527 2003-12-29

Publications (2)

Publication Number Publication Date
WO2006057647A2 WO2006057647A2 (en) 2006-06-01
WO2006057647A3 true WO2006057647A3 (en) 2006-07-20

Family

ID=34886484

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/043036 WO2006057647A2 (en) 2003-12-29 2004-12-20 Decoupling the number of logical threads from the number of simultaneous physical threads in a processor

Country Status (6)

Country Link
US (1) US7797683B2 (en)
JP (1) JP4599365B2 (en)
KR (1) KR100856144B1 (en)
CN (2) CN1926514B (en)
DE (2) DE112004002505T5 (en)
WO (1) WO2006057647A2 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7765547B2 (en) * 2004-11-24 2010-07-27 Maxim Integrated Products, Inc. Hardware multithreading systems with state registers having thread profiling data
US7793291B2 (en) * 2004-12-22 2010-09-07 International Business Machines Corporation Thermal management of a multi-processor computer system
US7454596B2 (en) * 2006-06-29 2008-11-18 Intel Corporation Method and apparatus for partitioned pipelined fetching of multiple execution threads
US9146745B2 (en) * 2006-06-29 2015-09-29 Intel Corporation Method and apparatus for partitioned pipelined execution of multiple execution threads
US7698540B2 (en) * 2006-10-31 2010-04-13 Hewlett-Packard Development Company, L.P. Dynamic hardware multithreading and partitioned hardware multithreading
US8307246B2 (en) * 2008-10-29 2012-11-06 Aternity Information Systems Ltd. Real time monitoring of computer for determining speed of various processes
US9032254B2 (en) 2008-10-29 2015-05-12 Aternity Information Systems Ltd. Real time monitoring of computer for determining speed and energy consumption of various processes
US8487909B2 (en) * 2011-07-27 2013-07-16 Cypress Semiconductor Corporation Method and apparatus for parallel scanning and data processing for touch sense arrays
US9542236B2 (en) 2011-12-29 2017-01-10 Oracle International Corporation Efficiency sequencer for multiple concurrently-executing threads of execution
US9715411B2 (en) 2014-02-05 2017-07-25 International Business Machines Corporation Techniques for mapping logical threads to physical threads in a simultaneous multithreading data processing system
US9213569B2 (en) * 2014-03-27 2015-12-15 International Business Machines Corporation Exiting multiple threads in a computer
US9898351B2 (en) * 2015-12-24 2018-02-20 Intel Corporation Method and apparatus for user-level thread synchronization with a monitor and MWAIT architecture
CN106325512A (en) * 2016-08-24 2017-01-11 韩龙潇 Terminal for monitoring surrounding in use state

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5815727A (en) * 1994-12-20 1998-09-29 Nec Corporation Parallel processor for executing plural thread program in parallel using virtual thread numbers
US20030018680A1 (en) * 2001-07-18 2003-01-23 Lino Iglesias Smart internetworking operating system for low computational power microprocessors

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2078315A1 (en) * 1991-09-20 1993-03-21 Christopher L. Reeve Parallel processing apparatus and method for utilizing tiling
US5442797A (en) * 1991-12-04 1995-08-15 Casavant; Thomas L. Latency tolerant risc-based multiple processor with event driven locality managers resulting from variable tagging
JPH05181670A (en) * 1992-01-06 1993-07-23 Fujitsu Ltd Microprogram system computer
JP2991598B2 (en) * 1993-09-09 1999-12-20 富士通株式会社 LSI design apparatus and LSI design method
US5913925A (en) * 1996-12-16 1999-06-22 International Business Machines Corporation Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order
US6192514B1 (en) * 1997-02-19 2001-02-20 Unisys Corporation Multicomputer system
US5999734A (en) * 1997-10-21 1999-12-07 Ftl Systems, Inc. Compiler-oriented apparatus for parallel compilation, simulation and execution of computer programs and hardware models
US7085670B2 (en) * 1998-02-17 2006-08-01 National Instruments Corporation Reconfigurable measurement system utilizing a programmable hardware element and fixed hardware resources
US6557064B1 (en) * 1999-02-19 2003-04-29 Hewlett-Packard Development Company Set up time adjust
US6496925B1 (en) * 1999-12-09 2002-12-17 Intel Corporation Method and apparatus for processing an event occurrence within a multithreaded processor
US6708269B1 (en) * 1999-12-30 2004-03-16 Intel Corporation Method and apparatus for multi-mode fencing in a microprocessor system
US7103586B2 (en) * 2001-03-16 2006-09-05 Gravic, Inc. Collision avoidance in database replication systems
US7127561B2 (en) * 2001-12-31 2006-10-24 Intel Corporation Coherency techniques for suspending execution of a thread until a specified memory access occurs
US7487504B2 (en) * 2002-02-06 2009-02-03 International Business Machines Corporation Thread dispatch for multiprocessor computer systems
US7155708B2 (en) * 2002-10-31 2006-12-26 Src Computers, Inc. Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5815727A (en) * 1994-12-20 1998-09-29 Nec Corporation Parallel processor for executing plural thread program in parallel using virtual thread numbers
US20030018680A1 (en) * 2001-07-18 2003-01-23 Lino Iglesias Smart internetworking operating system for low computational power microprocessors

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ERIC BRON: "Re: What about speculative execution ?", 20 October 2000 (2000-10-20), XP002378251, Retrieved from the Internet <URL:http://www.aceshardware.com/forums/read_post.jsp?id=20009849&forumid=1> [retrieved on 20060424] *
MARR D T ET AL: "Hyper-Threading Technology architecture and microarchitecture", INTEL TECHNOLOGY JOURNAL INTEL CORP USA, no. 1, 2002, XP002378250, ISSN: 1535-864X, Retrieved from the Internet <URL:http://courses.ece.uiuc.edu/ece511/papers/Marr.2002.itj.pdf> [retrieved on 20060424] *

Also Published As

Publication number Publication date
DE112004002505T5 (en) 2006-11-23
US20050193278A1 (en) 2005-09-01
US7797683B2 (en) 2010-09-14
CN1926514A (en) 2007-03-07
CN1926514B (en) 2011-06-08
JP2007517322A (en) 2007-06-28
CN102193828A (en) 2011-09-21
JP4599365B2 (en) 2010-12-15
KR20060111626A (en) 2006-10-27
WO2006057647A2 (en) 2006-06-01
KR100856144B1 (en) 2008-09-03
CN102193828B (en) 2013-06-12
DE112004003142A5 (en) 2013-03-21

Similar Documents

Publication Publication Date Title
US8799929B2 (en) Method and apparatus for bandwidth allocation mode switching based on relative priorities of the bandwidth allocation modes
DE60032481T2 (en) METHOD AND DEVICE FOR THREAD-SWITCHING IN A MULTITHREAD PROCESSOR
DE60029619T2 (en) METHOD, APPARATUS, MEDIUM AND PROGRAM FOR RECEIVING AND LEAVING MULTIPLE FIRES IN A MULTIPLE PROCESSOR
DE60038693T2 (en) METHOD AND DEVICE FOR SWITCHING OFF A CLOCK SIGNAL IN A VIOLINARY PROCESSOR
US10417056B2 (en) Systems and methods for performing concurrency restriction and throttling over contended locks
US9274832B2 (en) Method and electronic device for thread scheduling
US8898435B2 (en) Optimizing system throughput by automatically altering thread co-execution based on operating system directives
US7318128B1 (en) Methods and apparatus for selecting processes for execution
WO2006057647A3 (en) Decoupling the number of logical threads from the number of simultaneous physical threads in a processor
US7096470B2 (en) Method and apparatus for implementing thread replacement for optimal performance in a two-tiered multithreading structure
JP3987384B2 (en) Run queue management
JP4205369B2 (en) Sleep queue management
US20170161106A1 (en) Providing thread fairness in a hyper-threaded microprocessor
Bouron et al. The battle of the schedulers:{FreeBSD}{ULE} vs. linux {CFS}
US6845504B2 (en) Method and system for managing lock contention in a computer system
US7941643B2 (en) Multi-thread processor with multiple program counters
US9830201B2 (en) Low overhead contention-based switching between ticket lock and queued lock
Liu et al. SAWS: Synchronization aware GPGPU warp scheduling for multiple independent warp schedulers
CN111052094B (en) Spin lock efficiency enhancement for user space using C-state and turbo acceleration
US7984439B2 (en) Efficient mechanism for preventing starvation in counting semaphores
Mao et al. Coordinating prefetching and STT-RAM based last-level cache management for multicore systems
Abeydeera et al. SAM: Optimizing multithreaded cores for speculative parallelism
US6988185B2 (en) Select-free dynamic instruction scheduling
US7509643B2 (en) Method and apparatus for supporting asymmetric multi-threading in a computer system
Usui et al. Squash: Simple qos-aware high-performance memory scheduler for heterogeneous systems with hardware accelerators

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200480039419.2

Country of ref document: CN

AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

WWE Wipo information: entry into national phase

Ref document number: 2006547293

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 1020067012966

Country of ref document: KR

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWP Wipo information: published in national office

Ref document number: 1020067012966

Country of ref document: KR

RET De translation (de og part 6b)

Ref document number: 112004002505

Country of ref document: DE

Date of ref document: 20061123

Kind code of ref document: P

WWE Wipo information: entry into national phase

Ref document number: 112004002505

Country of ref document: DE

122 Ep: pct application non-entry in european phase
REG Reference to national code

Ref country code: DE

Ref legal event code: 8607