WO2006045755A3 - Method and device for increasing the availability of a memory unit and memory unit - Google Patents

Method and device for increasing the availability of a memory unit and memory unit Download PDF

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Publication number
WO2006045755A3
WO2006045755A3 PCT/EP2005/055438 EP2005055438W WO2006045755A3 WO 2006045755 A3 WO2006045755 A3 WO 2006045755A3 EP 2005055438 W EP2005055438 W EP 2005055438W WO 2006045755 A3 WO2006045755 A3 WO 2006045755A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory unit
availability
increasing
data
instructions
Prior art date
Application number
PCT/EP2005/055438
Other languages
German (de)
French (fr)
Other versions
WO2006045755A2 (en
Inventor
Reinhard Weiberle
Bernd Mueller
Werner Harter
Ralf Angerbauer
Thomas Kottke
Yorck Collani
Rainer Gmehlich
Wolfgang Pfeiffer
Florian Hartwich
Karsten Graebitz
Original Assignee
Bosch Gmbh Robert
Reinhard Weiberle
Bernd Mueller
Werner Harter
Ralf Angerbauer
Thomas Kottke
Yorck Collani
Rainer Gmehlich
Wolfgang Pfeiffer
Florian Hartwich
Karsten Graebitz
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bosch Gmbh Robert, Reinhard Weiberle, Bernd Mueller, Werner Harter, Ralf Angerbauer, Thomas Kottke, Yorck Collani, Rainer Gmehlich, Wolfgang Pfeiffer, Florian Hartwich, Karsten Graebitz filed Critical Bosch Gmbh Robert
Publication of WO2006045755A2 publication Critical patent/WO2006045755A2/en
Publication of WO2006045755A3 publication Critical patent/WO2006045755A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories

Abstract

The invention relates to a method and to a device for increasing the availability, after an error recognition in a volatile memory unit, in particular a cache memory. Access to the data and/or instructions stored in the volatile memory unit takes place by means of said addresses associated therewith, and data and/or instructions identified as defective are blanked out, and the addresses associated with said data and/or instructions are no longer used.
PCT/EP2005/055438 2004-10-25 2005-10-20 Method and device for increasing the availability of a memory unit and memory unit WO2006045755A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004051936A DE102004051936A1 (en) 2004-10-25 2004-10-25 Method and apparatus for increasing the availability of a storage unit and storage unit
DE102004051936.6 2004-10-25

Publications (2)

Publication Number Publication Date
WO2006045755A2 WO2006045755A2 (en) 2006-05-04
WO2006045755A3 true WO2006045755A3 (en) 2006-07-27

Family

ID=35502729

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2005/055438 WO2006045755A2 (en) 2004-10-25 2005-10-20 Method and device for increasing the availability of a memory unit and memory unit

Country Status (2)

Country Link
DE (1) DE102004051936A1 (en)
WO (1) WO2006045755A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016104012A1 (en) * 2016-03-04 2017-09-07 Infineon Technologies Ag Processing a data word

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5708789A (en) * 1993-11-01 1998-01-13 Sgs-Thomson Microelectronics, Inc. Structure to utilize a partially functional cache memory by invalidation of faulty cache memory locations
GB2332290A (en) * 1997-11-14 1999-06-16 Memory Corp Plc Memory management unit incorporating memory fault masking
US20040105318A1 (en) * 2002-05-20 2004-06-03 Kawasaki Microelectronics, Inc. Content addressable memory device that can be saved by reduction of memory capacity

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5708789A (en) * 1993-11-01 1998-01-13 Sgs-Thomson Microelectronics, Inc. Structure to utilize a partially functional cache memory by invalidation of faulty cache memory locations
GB2332290A (en) * 1997-11-14 1999-06-16 Memory Corp Plc Memory management unit incorporating memory fault masking
US20040105318A1 (en) * 2002-05-20 2004-06-03 Kawasaki Microelectronics, Inc. Content addressable memory device that can be saved by reduction of memory capacity

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"DYNAMIC CACHE LINE DELETE", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 32, no. 6A, 1 November 1989 (1989-11-01), pages 439, XP000043272, ISSN: 0018-8689 *

Also Published As

Publication number Publication date
DE102004051936A1 (en) 2006-05-04
WO2006045755A2 (en) 2006-05-04

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