WO2005114670B1 - Pipelined data relocation and improved chip architectures - Google Patents
Pipelined data relocation and improved chip architecturesInfo
- Publication number
- WO2005114670B1 WO2005114670B1 PCT/US2005/016341 US2005016341W WO2005114670B1 WO 2005114670 B1 WO2005114670 B1 WO 2005114670B1 US 2005016341 W US2005016341 W US 2005016341W WO 2005114670 B1 WO2005114670 B1 WO 2005114670B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- controller
- memory
- registers
- transferring
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Quality & Reliability (AREA)
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR20067023780A KR101152283B1 (en) | 2004-05-13 | 2005-05-09 | Pipelined data relocation and improved chip architectures |
EP05742859A EP1756832A1 (en) | 2004-05-13 | 2005-05-09 | Pipelined data relocation and improved chip architectures |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/846,289 | 2004-05-13 | ||
US10/846,289 US7490283B2 (en) | 2004-05-13 | 2004-05-13 | Pipelined data relocation and improved chip architectures |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2005114670A1 WO2005114670A1 (en) | 2005-12-01 |
WO2005114670B1 true WO2005114670B1 (en) | 2006-02-09 |
Family
ID=34982249
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2005/016341 WO2005114670A1 (en) | 2004-05-13 | 2005-05-09 | Pipelined data relocation and improved chip architectures |
Country Status (5)
Country | Link |
---|---|
US (3) | US7490283B2 (en) |
EP (1) | EP1756832A1 (en) |
KR (1) | KR101152283B1 (en) |
TW (1) | TWI287730B (en) |
WO (1) | WO2005114670A1 (en) |
Families Citing this family (152)
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- 2005-05-09 EP EP05742859A patent/EP1756832A1/en not_active Withdrawn
- 2005-05-09 WO PCT/US2005/016341 patent/WO2005114670A1/en not_active Application Discontinuation
- 2005-05-09 KR KR20067023780A patent/KR101152283B1/en active IP Right Grant
- 2005-05-13 TW TW94115678A patent/TWI287730B/en not_active IP Right Cessation
-
2009
- 2009-01-13 US US12/353,185 patent/US8621323B2/en active Active
-
2013
- 2013-12-13 US US14/106,261 patent/US9122591B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
KR101152283B1 (en) | 2012-06-11 |
WO2005114670A1 (en) | 2005-12-01 |
TWI287730B (en) | 2007-10-01 |
KR20070049603A (en) | 2007-05-11 |
US7490283B2 (en) | 2009-02-10 |
US8621323B2 (en) | 2013-12-31 |
US9122591B2 (en) | 2015-09-01 |
US20140108886A1 (en) | 2014-04-17 |
US20050257120A1 (en) | 2005-11-17 |
US20090125785A1 (en) | 2009-05-14 |
TW200614049A (en) | 2006-05-01 |
EP1756832A1 (en) | 2007-02-28 |
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