WO2005110049A3 - Processor for video data - Google Patents

Processor for video data Download PDF

Info

Publication number
WO2005110049A3
WO2005110049A3 PCT/US2005/016367 US2005016367W WO2005110049A3 WO 2005110049 A3 WO2005110049 A3 WO 2005110049A3 US 2005016367 W US2005016367 W US 2005016367W WO 2005110049 A3 WO2005110049 A3 WO 2005110049A3
Authority
WO
WIPO (PCT)
Prior art keywords
video data
dynamically configurable
processor
attributes
dynamically
Prior art date
Application number
PCT/US2005/016367
Other languages
French (fr)
Other versions
WO2005110049A2 (en
Inventor
Paul L Master
W James Scheuermann
Original Assignee
Quicksilver Tech Inc
Paul L Master
W James Scheuermann
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quicksilver Tech Inc, Paul L Master, W James Scheuermann filed Critical Quicksilver Tech Inc
Priority to JP2007513287A priority Critical patent/JP4583445B2/en
Priority to EP05747411A priority patent/EP1745557A4/en
Publication of WO2005110049A2 publication Critical patent/WO2005110049A2/en
Publication of WO2005110049A3 publication Critical patent/WO2005110049A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H04N19/523—Motion estimation or motion compensation with sub-pixel accuracy
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/117—Filters, e.g. for pre-processing or post-processing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/12—Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/43—Hardware specially adapted for motion estimation or compensation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Discrete Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Television Systems (AREA)
  • Image Processing (AREA)

Abstract

A video processor according to the invention is dynamically configurable as to the attributes of the video data upon which the processor operates. Some embodiments dynamically configure the processor via a sequence of instructions, where the instructions include information on the attributes of the current video data. Some embodiments include a dynamically configurable adder array that computes difference functions thereby generating error vectors. Some embodiments include a dynamically configurable adder array that computes filtering functions applied to the video data, e.g. interpolation or decimation of the incoming video prior to motion detection. Some embodiments of the invention provide dynamically configurable hardware searches, for example, for detecting motion. Some embodiments of the invention are implemented using an adaptive computing machines (ACMs). An ACM includes a plurality of heterogeneous computational elements, each coupled to an interconnection network.
PCT/US2005/016367 2004-05-10 2005-05-10 Processor for video data WO2005110049A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007513287A JP4583445B2 (en) 2004-05-10 2005-05-10 Video data processor
EP05747411A EP1745557A4 (en) 2004-05-10 2005-05-10 Processor for video data

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US57008704P 2004-05-10 2004-05-10
US60/570,087 2004-05-10
US11/125,852 2005-05-09
US11/125,852 US8018463B2 (en) 2004-05-10 2005-05-09 Processor for video data

Publications (2)

Publication Number Publication Date
WO2005110049A2 WO2005110049A2 (en) 2005-11-24
WO2005110049A3 true WO2005110049A3 (en) 2006-09-21

Family

ID=35394608

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/016367 WO2005110049A2 (en) 2004-05-10 2005-05-10 Processor for video data

Country Status (5)

Country Link
US (1) US8018463B2 (en)
EP (1) EP1745557A4 (en)
JP (1) JP4583445B2 (en)
CN (1) CN101702779A (en)
WO (1) WO2005110049A2 (en)

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US8130825B2 (en) * 2004-05-10 2012-03-06 Nvidia Corporation Processor for video data encoding/decoding
US20080111923A1 (en) * 2006-11-09 2008-05-15 Scheuermann W James Processor for video data
US8837575B2 (en) * 2007-03-29 2014-09-16 Cisco Technology, Inc. Video processing architecture
KR101305514B1 (en) * 2007-04-17 2013-09-06 (주)휴맥스 Bitstream decoding device and method
KR100926752B1 (en) 2007-12-17 2009-11-16 한국전자통신연구원 Fine Motion Estimation Method and Apparatus for Video Coding
US7873938B2 (en) * 2008-06-27 2011-01-18 Transwitch Corporation Method for constructing a variable bitwidth video processor
US8543635B2 (en) 2009-01-27 2013-09-24 Xilinx, Inc. Digital signal processing block with preadder stage
US8479133B2 (en) 2009-01-27 2013-07-02 Xilinx, Inc. Method of and circuit for implementing a filter in an integrated circuit
WO2011128272A2 (en) * 2010-04-13 2011-10-20 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Hybrid video decoder, hybrid video encoder, data stream
FR3100629B1 (en) * 2019-09-10 2023-04-07 St Microelectronics Grenoble 2 CAN bus communication

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US5973742A (en) * 1996-05-24 1999-10-26 Lsi Logic Corporation System and method for performing motion estimation with reduced memory loading latency
US6041078A (en) * 1997-03-25 2000-03-21 Level One Communications, Inc. Method for simplifying bit matched motion estimation

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US5646618A (en) * 1995-11-13 1997-07-08 Intel Corporation Decoding one or more variable-length encoded signals using a single table lookup
US5973742A (en) * 1996-05-24 1999-10-26 Lsi Logic Corporation System and method for performing motion estimation with reduced memory loading latency
US6041078A (en) * 1997-03-25 2000-03-21 Level One Communications, Inc. Method for simplifying bit matched motion estimation

Also Published As

Publication number Publication date
CN101702779A (en) 2010-05-05
US8018463B2 (en) 2011-09-13
JP2007538431A (en) 2007-12-27
WO2005110049A2 (en) 2005-11-24
US20070200857A1 (en) 2007-08-30
EP1745557A2 (en) 2007-01-24
EP1745557A4 (en) 2009-03-25
JP4583445B2 (en) 2010-11-17

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