WO2005078463A1 - 試験装置 - Google Patents
試験装置 Download PDFInfo
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- WO2005078463A1 WO2005078463A1 PCT/JP2005/002350 JP2005002350W WO2005078463A1 WO 2005078463 A1 WO2005078463 A1 WO 2005078463A1 JP 2005002350 W JP2005002350 W JP 2005002350W WO 2005078463 A1 WO2005078463 A1 WO 2005078463A1
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- test
- control
- signal
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- modules
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31907—Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
Definitions
- the present invention relates to a test device.
- the present invention relates to a test apparatus including a plurality of test module slots in which different types of test modules are selectively mounted.
- test module In a test apparatus that performs an analog test of a device under test, one test module generates a test signal and supplies it to the device under test, and another test module measures the output signal of the device under test. To test the device under test. Then, in order to properly operate each of the plurality of test modules, each of the plurality of control modules converts a plurality of trigger signals and a plurality of clock signals into a trigger signal and a clock corresponding to the type of each test module. The signal is selected based on the test program and supplied to the test module. To realize the operation of this control module, the creator of the test program arbitrarily selects the trigger signal and clock signal input to the control module and the trigger signal and clock signal output to the control module power test module. A test table for testing the device under test, taking into account the connection between the input and output in the control module, and creating a management table to manage the connection between the input and output in the control module. Has been created.
- test apparatus provided with a plurality of test module slots in which different types of test modules for respectively generating different types of test signals for testing a device under test are selectively mounted.
- test modules are replaced.
- the management table must be recreated, and each time a test module is replaced, a test program must be created according to the mounting position of the test module. A preparation process was needed.
- an object of the present invention is to provide a test apparatus that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims.
- the dependent claims define further advantageous embodiments of the present invention.
- a plurality of test module slots in which different types of test modules for respectively generating different types of test signals for testing a device under test are provided.
- a plurality of test modules each of which is a control apparatus for supplying control signals for controlling operation of a plurality of test modules mounted in each of the plurality of test module slots to the plurality of test modules;
- a setting information supply means for supplying hardware setting information to be set in advance to a control module, which provides a control signal corresponding to the specific test module to a specific test module, and an enable signal for the specific test module And enable control modules to supply control signals to specific test modules.
- a control signal that receives an enable signal from a specific test module based on hardware setting information, and a control signal that corresponds to a specific test module to a specific test module.
- Setting means for causing the setting to be made to be supplied.
- the control module has a plurality of interfaces for inputting each of a plurality of different types of control signals, and the setting information supply means selects a specific control signal from the plurality of control signals,
- the hardware setting information is supplied to the control module via a specific interface for inputting a specific control signal of the plurality of interfaces to the control module, and the setting means controls the control input to the specific interface power control module.
- the control module may be configured to send signals to a particular test module.
- the control module includes a plurality of control signals input by each of the plurality of interfaces.
- a multiplexer circuit for selecting a control signal to be supplied to a specific test module, and a specific circuit based on a setting request signal supplied from the setting means when a specific test module card also receives an enable signal.
- a flip-flop circuit for holding information indicating that hardware setting information is input as a select signal for controlling selection of a control signal by the multiplexer circuit.
- the control signal is a trigger signal for controlling the operation of the test module
- the multiplexer circuit selects a plurality of types of different trigger signals input by a plurality of interfaces, respectively, and selects a trigger signal to be supplied to a specific test module. May be supplied.
- the control signal is a clock signal for controlling the operation of the test module
- the multiplexer circuit includes a plurality of types of different clock signals input by a plurality of interfaces.
- a clock signal to be supplied to a specific test module May be supplied
- each of the plurality of interfaces inputs as a control signal
- a first multiplexer circuit for selecting a trigger signal to be supplied to a specific test module; and a setting for receiving an enable signal from a specific test module. Based on the setting request signal supplied from the means, based on the setting request signal, information indicating that specific interface capability hardware setting information is input is used as a select signal for controlling selection of a trigger signal by the first multiplexer circuit.
- a first flip-flop circuit to be held and a plurality of different clock signal powers to control the operation of the test module, each of which is input as a control signal by a plurality of interfaces.
- a second multiplexer circuit to enable When receiving the hardware configuration information, the information indicating that the hardware setting information is also input to the specific interface based on the setting request signal supplied from the setting means is received by the second multiplexer circuit.
- a second flip-flop circuit for holding a select signal for controlling selection of a signal.
- a first site system for controlling an operation of a first test module of the plurality of test modules A control device, and a second site control device for controlling an operation of a second test module of the plurality of test modules, wherein the enable signal control means causes the first test module to generate an enable signal, and The enable signal is supplied to the first control module of the plurality of control modules that supply the control signal to the module, and the setting information supply means transmits the control signal generated based on the control of the first site control device to the first control module.
- the first interface power supplied to the control module is supplied with hardware setting information, and the setting means causes the control signal input to the first interface module to be supplied to the first control module power first test module.
- the first control module is set, and the enable signal control means is configured to enable the second test module.
- the enable signal is supplied to the second control module among the plurality of control modules that supply the control signal to the second test module, and the setting information supply unit generates the enable signal based on the control of the second site control device.
- the second interface module supplies hardware setting information for inputting the set control signal to the second control module, and the setting means converts the control signal input to the second control module to the second test module.
- the second control module to be supplied to the second control module may be set.
- the test apparatus tests a plurality of devices under test simultaneously, and the enable signal control means supplies a test signal to a first device under test among the plurality of devices under test.
- the first interface module supplies hardware setting information for inputting a control signal for controlling the test of the first control module to the first control module, and the setting means converts the control signal input to the first interface module to the first interface module.
- the first control module to be supplied to the test module is set, and the enable signal control means includes a plurality of devices under test.
- a test signal is supplied to a second device under test among the chairs.
- a control signal is supplied to a second test module among the plurality of test modules to generate an enable signal and to supply a control signal to the second test module.
- the enable signal is supplied to the second control module of the second device, and the setting information supply means controls the test of the second device under test.
- a second interface power for inputting a control signal to the second control module is supplied with hardware setting information, and the setting means is configured to supply the control signal input to the second interface module to the second test module. Let's set the second control module.
- the plurality of test modules are analog measurement modules for performing an analog test of the device under test, and the plurality of control modules transmit control signals for controlling the operation of the plurality of analog measurement modules to the plurality of analog measurement modules. It may be supplied to each module.
- the test of the device under test can be started quickly, and the time required for the test of the device under test can be shortened.
- FIG. 1 is a diagram showing an example of a configuration of a test apparatus 100 according to an embodiment of the present invention.
- FIG. 2 is a diagram showing a first example of a configuration of a trigger control module 114a.
- FIG. 3 is a diagram showing a second example of the configuration of the trigger control module 114a.
- FIG. 4 is a diagram showing a third example of the configuration of the trigger control module 114a.
- FIG. 1 shows an example of a configuration of a test apparatus 100 according to an embodiment of the present invention.
- the test apparatus 100 includes a control device group 102, a plurality of trigger signal sources 104a to 104d, a plurality of clock signal sources 106a to 106d, an analog synchronization control unit 108, a plurality of test modules 118a to 118c, and a plurality of test module slots. 120a- 120c.
- the control device group 102 includes an overall control device 101 and a plurality of site control devices 103a to 103b.
- the analog synchronization control unit 108 has a trigger matrix 110 and a clock matrix 112.
- Trigger matrix 110 includes a plurality of trigger control modules 114a-114c
- clock matrix 112 includes a plurality of clock control modules 116a-116c.
- the test apparatus 100 generates a test signal and supplies it to the devices under test 150a to 150c, and measures an output signal output as a result of the device under test 150a to 150c operating based on the test signal.
- the quality of the device under test 150a-150c is determined based on the test.
- the test apparatus 100 is realized by an open architecture, and uses a module based on an open architecture as the test modules 118a to 118c for supplying test signals to the devices under test 150a to 15Oc. That is, different types of test modules 118a-118c that respectively generate different types of test signals for testing the devices under test 150a-150c are selectively mounted in the test module slots 120a-120c.
- the test modules 118a to 118c generate, for example, an arbitrary analog waveform and supply it to the device under test 150a to 150c, and the device under test 150a according to the analog waveform supplied from the arbitrary waveform shaper.
- An analog measurement module that captures the analog waveform output by the 150c and performs an analog test of the device under test 150a—150c such as a phase characteristic tester that tests the phase characteristics of the analog waveform.
- Each of the trigger control module 114a—114c and the clock control module 116a—116c controls the operation of a plurality of test modules 118a—118c installed in each of the plurality of test module slots 120a—120c.
- a trigger signal and a clock signal are supplied to the plurality of test modules 118a to 118c, respectively.
- the trigger signal and the clock signal are examples of the control signal of the present invention.
- the trigger control modules 114a to 114c have a plurality of interfaces for inputting a plurality of different types of trigger signals respectively supplied from the plurality of trigger signal sources 104a to 104d. Further, the clock control modules 116a to 116c have a plurality of interfaces for inputting a plurality of different types of clock signals supplied from the plurality of clock signal sources 106a to 106d, respectively. And trigger system The control modules 114a to 114c receive the trigger signals generated by the trigger signal sources 104a to 104d, respectively, and, based on the control of the control device group 102, generate a trigger signal having a displacement of the trigger signal source 104a to 104d. Select and supply to test modules 118a-118c respectively.
- the clock control modules 116a to 116c receive the clock signals generated by the clock signal sources 106a to 106d, respectively, and control the clock signals generated by any of the clock signal sources 106a to 106d based on the control of the control device group 102. Select and supply to test modules 118a-118c respectively.
- the trigger signal sources 104a to 104d and the clock signal sources 106a to 106d are, for example, a digital synchronization control unit, a performance board, and the like.
- the test modules 118a-118c, the trigger control modules 114a-114c, or the clock control modules 116a-116c may function as the trigger signal sources 104a-104d or the clock signal sources 106a-106d.
- the overall control device 101 acquires and stores a test control program, a test program, test data, and the like used by the test device 100 for testing the devices under test 150a to 150c via an external network or the like.
- the site control devices 103a-103b have functions as setting information supply means, enable signal control means, and setting means according to the present invention, control a plurality of test modules 118a-118c, and a plurality of devices under test 150a- Test each of the 150c simultaneously in parallel.
- the connection relationship between the site controllers 103a-103b and the test modules 11 8a-118c is switched according to the number of pins of the device under test 150a-150c, the wiring configuration of the performance board, the type of test modules 118a-118c, etc.
- the site controllers 103a-103b test a plurality of devices under test 150a-150c in parallel. Further, the site controllers 103a-103b execute different test sequences according to the performance of the devices under test 150a-150c. For example, the site controller 103a controls the operation of a plurality of test modules including the test module 118a of the plurality of test modules 118a-118c, and the site controller 103b controls the operation of the plurality of test modules 118a-118c. Controls the operation of multiple test modules, including the test module 118b.
- each of the site controllers 103a-103b divides the plurality of test modules 118a-118c into the number of sites of the site controllers 103a-103b, and controls the operation of the test modules included in each site.
- the site control devices 103a to 103b acquire a test control program from the central control device 101 and execute the program.
- the site controllers 103a-103b obtain the test program and test data used for testing the devices under test 150a-150c from the central controller 101, and acquire the test programs of the devices under test 150a-150c. Supply them to the test modules 118a-118c used for each test.
- the site controllers 103a to 103b supply the test signals generated by the plurality of trigger signal sources 104a to 104d and the clock signals generated by the plurality of clock signal sources 106a to 106d to the test modules 118a to 118c. This instructs test modules 118a-118c to start the test based on the test program and test data. Then, the site controllers 103a-103b receive an interrupt or the like from the test modules 118a-118c, for example, indicating that the test has been completed, and notify the overall controller 101.
- each of the trigger control modules 114a to 114c and the clock control modules 116a to 116c is set in advance by hardware before the test of the device under test 150a to 150c is started. It is determined which of the plurality of trigger signals or the plurality of clock signals generated by the plurality of trigger signal sources 104a-104d or the plurality of clock signal sources 106a-106d is to be output.
- the site control device 103a functions as setting information supply means of the present invention, and sends a trigger signal corresponding to the specific test module 118a to a specific test module 118a among the plurality of test modules 118a to 118c.
- hardware setting information to be set in advance is supplied to the trigger control module 114a and the clock control module 116a that supply a clock signal.
- one of the plurality of trigger signal sources 104a-104d is supplied to the trigger control module 114a with a status signal, which is an example of hardware setting information
- the other one of the clock signal sources 106a-106d is supplied with the status signal.
- a status signal which is an example of hardware setting information
- a specific trigger signal is selected from a plurality of trigger signals generated by the plurality of trigger signal sources 104a to 104d, respectively, and a specific trigger signal is selected from a plurality of interfaces of the trigger control module 114a.
- a status signal is supplied to the clock control module 116a via a specific interface.
- the site control device 103a functions as an enable signal control unit of the present invention, supplies an enable signal generation request to the test module 118a via the system control bus, and sends the enable signal to a specific test module 118a. Is generated, and the enable signal is supplied to the trigger control module 114a and the clock control module 116a that supply the trigger signal and the clock signal to the specific test module 118a.
- the site control device 103a functions as setting means of the present invention, and based on the hardware setting information, the trigger control module 114a that has received the enable signal from the specific test module 118a and the trigger control module 114a.
- the clock control module 116a is set to supply a trigger signal and a clock signal corresponding to the specific test module 118a to the specific test module 118a.
- a setting request signal is supplied to the trigger control module 114a via the system control bus, and a trigger signal input from the specific interface to the trigger control module 114a is supplied to the specific test module 118a.
- the hardware of the control module 114a is set.
- a setting request signal is supplied to the clock control module 116a via the system control bus, and a clock signal input from the specific interface to the clock control module 116a is supplied to the specific test module 118a. Then, the hardware of the clock control module 116a is set.
- the status signal is supplied from the trigger signal sources 104a to 104d to the trigger control modules 114a to 114c, and the status signals are supplied to the clock control modules 116a to 116c from the clock signal sources 106a to 106d. Also, by enabling the test modules 118a-118c to supply the enable signals to the trigger control modules 114a-114c and the clock control modules 116a-116c, the test of the devices under test 150a-150c can be performed. Rules 114a-114c and clock control modules 116a-116c.
- test modules 118a-118c mounted in the test module slots 120a-120c in the test equipment 100 realized by the open architecture can be replaced arbitrarily, the trigger control modules 114a-114c and clock control
- the trigger control modules 114a-114c and clock control There is no need to create a management table that manages the connection between inputs and outputs in modules 116a-116c.
- test programs according to the mounting positions of test modules 118a-118c there is no need to create test programs according to the mounting positions of test modules 118a-118c. Therefore, the test of the devices under test 150a-150c can be started quickly, and the time required for the test of the devices under test 150a-150c can be shortened.
- FIG. 2 shows a first example of the configuration of the trigger control module 114a according to the present embodiment.
- the trigger control module 114a according to this example includes a multiplexer circuit 200, a priority encoder 202, and a flip-flop circuit 204.
- the trigger control module 114a according to the present example controls the supply of a trigger signal corresponding to the device under test 150a to 150c to the test module 118a according to the status information held by the flip-flop circuit 204.
- the hardware setting of the trigger control module 114a before the test of the devices under test 150a to 150c is started will be described.
- the priority encoder 202 transmits the signal from the plurality of trigger signal sources 104a-104d.
- a signal supplied through a plurality of interfaces is taken in, status information indicating which of the trigger signal sources 104a to 104d is supplying a status signal is calculated, and the calculated status information is supplied to the flip-flop circuit 204.
- the flip-flop circuit 204 Holds the status information supplied from the priority encoder 202 when the setting request signal is supplied, based on the setting request signal, as a select signal for controlling selection of a control signal by the multiplexer circuit 200. Thereby, the hardware setting of the trigger control module 114a is performed, and the connection between the input and the output is determined. Next, the operation of the trigger control module 114a during the test operation of the devices under test 150a to 150c will be described.
- the flip-flop circuit 204 supplies the status information held before the start of the test as described above to the multiplexer circuit 200 as a select signal. Then, when the trigger signal generated by the trigger signal sources 104a to 104d based on the instruction of the control device group 102 is supplied to the trigger control module 114a through a plurality of interfaces, the multiplexer circuit 200 Based on the select signal supplied from the circuit 204, a plurality of trigger signals input to each of the plurality of interfaces are selected. A trigger signal to be supplied to a specific test module 118a is selected and supplied to the test module 118a. .
- the trigger control modules 114b to 114c have the same configuration and functions as the above-described trigger control module 114a.
- the clock control modules 116a to 116c have the same configuration and function as the above-described trigger control module 114a except for the difference between the trigger signal and the clock signal. That is, the clock control modules 116a to 116c include a multiplexer circuit, a priority encoder, and a flip-flop circuit having the same configuration and function as the multiplexer circuit 200, the priority encoder 202, and the flip-flop circuit 204.
- the trigger control is performed by causing the priority encoder 202 to generate status information and cause the flip-flop circuit 204 to hold it as a select signal before starting the test of the devices under test 150a to 150c.
- FIG. 3 shows a second example of the configuration of the trigger control module 114a according to the present embodiment.
- the site control apparatus 103a causes the test module 118a that supplies a test signal to the device under test 150a to generate an enable signal and supplies the trigger signal to the test module 118a.
- the site controller 103a sends a trigger signal for controlling the test of the device under test 150a to the trigger control module 114a.
- the first interface power input to a also provides hardware configuration information.
- the site control device 103a sets the trigger control module 114a that supplies the trigger signal input to the trigger control module 114a from the first interface to the test module 118a. Further, the site controller 103a causes the test module 118b that supplies the test signal to the device under test 150b to generate an enable signal, and causes the trigger control module 114b that supplies the trigger signal to the test module 118b to supply the enable signal. Then, the site controller 103a also supplies hardware setting information to the second interface which inputs a trigger signal for controlling the test of the device under test 150b to the trigger control module 114b. Then, the site control device 103a sets the trigger control module 114b that causes the trigger test module 118b to supply the trigger signal input from the second interface to the trigger control module 114b.
- the trigger control module 114a includes a multiplexer circuit 300, a priority encoder 302, a flip-flop circuit 304, a flip-flop circuit 306, and a plurality of AND circuits 308a to 308d.
- the trigger control module 114a according to the present example controls the supply of the trigger signal of a type corresponding to the type of the device under test 150a to 150c to the test module 118a by the status information held by the flip-flop circuit 306, The supply of the trigger signal corresponding to the test modules 118a to 118c to the test module 118a is further controlled by the status information held by the circuit 304.
- At least one of the trigger signal sources 104a to 104d supplies a status signal corresponding to the type of the device under test 150a to be tested by the test module 118a to the trigger control module 114a based on an instruction from the control device group 102. Is input to the flip-flop circuit 306.
- the flip-flop circuit 306 When the enable signal is supplied to the flip-flop circuit 306 by the test module 118a based on the instruction of the control device group 102, and the setting request signal is supplied from the control device group 102 to the flip-flop circuit 306, the flip-flop circuit 306 Are supplied from a plurality of trigger signal sources 104a-104d when the setting request signal is supplied based on the setting request signal.
- the held signal is held as status information that is selection information of a trigger signal according to the type of the device under test 150a.
- a status signal corresponding to the test module 118a is supplied to the trigger control module 114a by at least one of the trigger signal sources 104a to 104d based on a command from the control device group 102, a plurality of logic Input to the product circuits 308a-308d. Further, the flip-flop circuit 306 outputs the held status information based on the setting request signal supplied from the control device group 102 and inputs the status information to the plurality of AND circuits 308a to 308d.
- Each of the plurality of AND circuits 308a to 308d performs a logical AND operation on each of the signals supplied from the plurality of trigger signal sources 104a to 104d and the status information input from the flip-flop circuit 306, and generates a priority encoder.
- the priority encoder 302 takes in the operation result of the status signal supplied from the AND circuits 308a to 308d, and selects one of the trigger signal sources 104a to 104d according to the type of the device under test 150a. Status information indicating whether a status signal and a status signal corresponding to the test module 118 a are being supplied is calculated and supplied to the flip-flop circuit 304.
- the flip-flop circuit 304 holds, based on the setting request signal, the status information supplied from the priority encoder 302 when the setting request signal is supplied, as a select signal for controlling selection of a control signal by the multiplexer circuit 300. I do. Thereby, the hardware setting of the trigger control module 114a is performed, and the connection between the input and the output is determined.
- the test of the flip-flop circuit 304 is started as described above.
- the previously held status information is supplied to the multiplexer circuit 300 as a select signal.
- the multiplexer circuit 300 Based on the select signal supplied from the circuit 304, a plurality of trigger signals input to each of the plurality of interfaces are selected.
- a trigger signal to be supplied to a specific test module 118a is selected and supplied to the test module 118a. .
- the trigger control modules 114b to 114c have the same configuration and functions as the above-described trigger control module 114a.
- the clock control modules 116a to 116c have the same configuration and function as the above-described trigger control module 114a except for the difference between the trigger signal and the clock signal. That is, the clock control modules 116a to 116c include a multiplexer circuit 300, a priority encoder 302, a flip-flop circuit 304, a flip-flop circuit 306, and a plurality of AND circuits 308a to 308d. It has a priority encoder, a flip-flop circuit, a flip-flop circuit, and a plurality of AND circuits.
- the trigger control module 114a of this example before the test of the devices under test 150a to 150c starts, status information is generated by the flip-flop circuit 306 and the priority encoder 302, and the status information is held in the flip-flop circuit 304 as a select signal. By doing so, the hardware settings of the trigger control modules 114a to 114c and the clock control modules 116a to 116c can be set. Then, the test operation can be performed by appropriately selecting the trigger signal sources 104a to 104d and the clock signal sources 106a to 106d according to the types of the devices under test 150a to 150c and the test modules 118a to 118c.
- FIG. 4 shows a third example of the configuration of the trigger control module 114a according to the present embodiment.
- the control apparatus group 102 causes the test module 118a belonging to the first site controlled by the site control apparatus 103a to generate an enable signal, and causes the test module 118a to trigger.
- the enable signal is supplied to the trigger control module 114a that supplies the signal.
- the control device group 102 transmits the trigger signal generated based on the control of the site control device 103a to the trigger control module.
- the first interface power input to the rule 114a also provides hardware configuration information.
- the control device group 102 causes the trigger control module 114a to supply the trigger control signal input from the first interface to the trigger control module 114a to the test module 118a from the trigger control module 114a. Further, the control device group 102 causes the test module 118b belonging to the second site controlled by the site control device 103b to generate an enable signal, and supplies a trigger control signal to the test module 118b and supplies an enable signal to the trigger control module 114b. Let it. Then, the control device group 102 supplies the second interface power hardware setting information for inputting the trigger signal generated based on the control of the site control device 103b to the trigger control module 114b. Then, the control device group 102 causes the trigger control module 114b to supply a trigger control signal input from the second interface to the trigger control module 114b to set the trigger control module 114b.
- the site control apparatus 103a causes the test module 118a that supplies a test signal to the device under test 150a to generate an enable signal, and causes the trigger control module 114a that supplies a trigger signal to the test module 118a to supply the enable signal. . Then, the site control apparatus 103a supplies first interface power hardware setting information for inputting a trigger signal for controlling the test of the device under test 150a to the trigger control module 114a. Then, the site control device 103a sets the trigger control module 114a that causes the test module 118a to supply the trigger signal input to the trigger control module 114a from the first interface.
- the site controller 103b causes the test module 118b that supplies the test signal to the device under test 150b to generate an enable signal, and causes the trigger control module 114b that supplies the trigger signal to the test module 118b to supply the enable signal. Then, the site controller 103b also supplies hardware setting information to the second interface that inputs a trigger signal for controlling the test of the device under test 150b to the trigger control module 114b. Then, the site control device 103b causes the trigger test module 118b to supply the trigger signal input from the second interface to the trigger control module 114b to the trigger test module 118b.
- the trigger control module 114a includes the multiplexer circuit 400 and the It has an authority encoder 402, a flip-flop circuit 404, a flip-flop circuit 406, a plurality of AND circuits 408a to 408d, a flip-flop circuit 410, and a plurality of AND circuits 412a to 412d.
- the trigger control module 114a controls the supply of a trigger signal of a type corresponding to the type of the site control devices 103a to 103b to the test module 118a based on the status information held by the flip-flop circuit 410, and The status information held by the flip-flop circuit 406 further controls the supply of a trigger signal of a type corresponding to the type of the device under test 150a to 150c to the test module 118a, and the status information held by the flip-flop circuit 404 further controls the test module.
- the hardware settings of the trigger control module 114a before the test of the devices under test 150a to 150c is started will be described.
- a status signal corresponding to the type of the site control device 103a is supplied to the trigger control module 114a by at least one of the trigger signal sources 104a to 104d based on an instruction from the control device group 102, the signal is input to the flip-flop circuit 410. Is done.
- the enable signal is supplied to the flip-flop circuit 410 by the test module 118a based on the instruction of the control device group 102, and the setting request signal is supplied to the flip-flop circuit 410 from the control device group 102, the flip-flop circuit is activated.
- the control circuit 410 Based on the setting request signal, the control circuit 410 selects signals supplied from the plurality of trigger signal sources 104a-104d when the setting request signal is supplied, and selects a trigger signal according to the type of the site control device 103a. The information is held as status information.
- a status signal corresponding to the type of the device under test 150a is supplied to the trigger control module 114a by at least one of the trigger signal sources 104a to 104d based on a command from the control device group 102, AND circuit 412a-412d of the input. Further, the flip-flop circuit 410 outputs the held status information based on the setting request signal supplied from the control device group 102 and inputs the status information to the plurality of AND circuits 412a to 412d. Each of the plurality of AND circuits 412a-412d performs a logical AND operation on each of the plurality of trigger signal sources 104a-104d, which is supplied with the output signal, and the status information input to the flip-flop circuit 406. , To the flip-flop circuit 406.
- the AND circuits 412a to 412d operate in accordance with the type of the site control device 103a.
- the plurality of status signals supplied to the module 114a and the plurality of status signals supplied to the trigger control module 114a according to the type of the device under test 150a are logically operated and supplied to the flip-flop circuit 406.
- an enable signal is supplied to the flip-flop circuit 406 by the test module 118a based on an instruction from the control device group 102, and when a setting request signal is supplied from the control device group 102 to the flip-flop circuit 406, Based on the setting request signal, the control circuit 406 converts the signals supplied from the plurality of AND circuits 412a to 412d when the setting request signal is supplied to the type of the site control device 103a and the type of the device under test 150a. It is held as status information which is selection information of a trigger signal corresponding to the type.
- a status signal corresponding to the test module 118a is supplied to the trigger control module 114a by at least one of the trigger signal sources 104a to 104d based on a command from the control device group 102, It is input to the product circuits 408a-408d. Further, the flip-flop circuit 406 outputs the held status information based on the setting request signal supplied from the control device group 102 and inputs the status information to the plurality of AND circuits 408a to 408d. Each of the plurality of AND circuits 408a to 408d performs a logical AND operation on each of the signals supplied from the plurality of trigger signal sources 104a to 104d and the status information input from the flip-flop circuit 406, and generates a priority encoder. Supply to 402.
- the AND circuits 408a to 408d send a plurality of status signals supplied to the trigger control module 114a according to the type of the site control device 103a and the trigger control module 114a according to the type of the device under test 150a.
- the logical AND operation of the supplied plural status signals and the plural status signals supplied to the trigger control module 114a according to the device under test 150a are logically operated and supplied to the priority encoder 402.
- the priority encoder 402 captures the operation result of the status signal supplied from the AND circuits 408a to 408d, and selects one of the trigger signal sources 104a to 104d according to the type of the casite control device 103a.
- a status signal, a status signal corresponding to the type of the device under test 150a, and status information indicating whether a status signal corresponding to the test module 118a is supplied are calculated and supplied to the flip-flop circuit 404.
- the test module 118a When the setting signal is supplied to the flip-flop circuit 404 from the control device group 102 to the flip-flop circuit 404, the flip-flop circuit 404 receives the setting request signal based on the setting request signal.
- the status information supplied from the priority encoder 402 is held as a select signal that controls selection of a control signal by the multiplexer circuit 400.
- the hardware setting of the trigger control module 114a is performed, and the connection between the input and the output is determined.
- the flip-flop circuit 404 supplies the status information held before the start of the test as described above to the multiplexer circuit 400 as a select signal.
- a trigger signal generated by the trigger signal sources 104a to 104d based on an instruction from the control device group 102 is supplied to the trigger control module 114a via a plurality of interfaces
- the multiplexer circuit 400 Based on the select signal supplied from the circuit 404, a plurality of trigger signals input to each of the plurality of interfaces are selected, and a trigger signal to be supplied to a specific test module 118a is selected and supplied to the test module 118a.
- the trigger control modules 114b to 114c have the same configuration and function as the above-described trigger control module 114a.
- the clock control modules 116a to 116c have the same configuration and function as the above-described trigger control module 114a except for the difference between the trigger signal and the clock signal. That is, the clock control modules 116a-116c include a multiplexer circuit 400, a priority encoder 402, a flip-flop circuit 404, a flip-flop circuit 406, a plurality of AND circuits 408a-408d, a flip-flop circuit 410, and a plurality of AND circuits.
- It has a multiplexer circuit, a priority encoder, a flip-flop circuit, a flip-flop circuit, a plurality of AND circuits, a flip-flop circuit, and a plurality of AND circuits each having the same configuration and function as 412d.
- the trigger control module 114a of the present example before the test of the devices under test 150a to 150c starts, status information is generated by the flip-flop circuit 410, the flip-flop circuit 406, and the priority encoder 402, and By holding the circuit 404 as a select signal, the trigger control module 114a-114c and the clock Hardware settings for the network control modules 116a-116c. Then, the type of the site controller 103a-103b, the type of the device under test 150a-150c, and the trigger signal sources 104a-104d and the clock signal sources 106a-106d according to the test modules 118a-118c are appropriately selected. Test operation can be performed.
- the test apparatus 100 even when the test module 118a to 118c is mounted at an arbitrary position when the open architecture is realized, The connection between the input and output of the trigger control module 114a-114c and the clock control module 116a-116c can be easily and accurately controlled. Therefore, as in the test apparatus according to the related art, a management table for managing the connection between the input and output of the trigger control modules 114a-114c and the clock control modules 116a-116c, and a mounting position of the test modules 118a-118c are provided. Since it is not necessary to create a test program according to the requirement, the time required for testing the devices under test 150a to 150c can be reduced.
- the test of the device under test can be started quickly, and the time required for the test of the device under test can be shortened.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2005518036A JP4721906B2 (ja) | 2004-02-17 | 2005-02-16 | 試験装置 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US10/780,286 US7096139B2 (en) | 2004-02-17 | 2004-02-17 | Testing apparatus |
US10/780,286 | 2004-02-17 |
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WO2005078463A1 true WO2005078463A1 (ja) | 2005-08-25 |
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PCT/JP2005/002350 WO2005078463A1 (ja) | 2004-02-17 | 2005-02-16 | 試験装置 |
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US (1) | US7096139B2 (ja) |
JP (1) | JP4721906B2 (ja) |
WO (1) | WO2005078463A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008268213A (ja) * | 2007-04-23 | 2008-11-06 | Advantest Corp | プログラムおよび試験装置 |
US8547125B2 (en) | 2010-01-26 | 2013-10-01 | Advantest Corporation | Test apparatus and test module |
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JP5089237B2 (ja) * | 2007-05-08 | 2012-12-05 | 株式会社アドバンテスト | テストユニット装置および試験装置 |
US8037371B1 (en) | 2007-05-14 | 2011-10-11 | National Semiconductor Corporation | Apparatus and method for testing high-speed serial transmitters and other devices |
US7809517B1 (en) * | 2007-09-07 | 2010-10-05 | National Semiconductor Corporation | Apparatus and method for measuring phase noise/jitter in devices under test |
TWM330475U (en) * | 2007-10-30 | 2008-04-11 | Princeton Technology Corp | Test system |
US20110208466A1 (en) * | 2007-11-29 | 2011-08-25 | Airbus Operations Gmbh | Test equipment and method for testing an aircraft oxygen system control device |
BRPI0722227A2 (pt) * | 2007-11-29 | 2014-06-03 | Airbus Operations Gmbh | Testador para testar a confiabilidade operacional de um circuito de distribuição de oxigênio para cabine de pilotagem, uso do mesmo, e, método para testar a confiabilidade operacional de um circuito de distribuição de oxigênio para cabine de pilotagem. |
US8103912B2 (en) * | 2008-09-07 | 2012-01-24 | EADS North America, Inc. | Sequencer and test system including the sequencer |
JP5183447B2 (ja) * | 2008-12-12 | 2013-04-17 | 株式会社アドバンテスト | 試験装置および診断方法 |
DE102010003558A1 (de) | 2010-03-31 | 2011-10-06 | Robert Bosch Gmbh | Verfahren zum Ansteuern einer Anzahl an Modulen |
JP6972075B2 (ja) * | 2019-09-30 | 2021-11-24 | アンリツ株式会社 | 移動端末試験システム |
US11122408B1 (en) * | 2020-05-04 | 2021-09-14 | Wireless Metrix | System for monitoring audio quality of clustered wireless devices |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60135777A (ja) * | 1983-12-24 | 1985-07-19 | Fanuc Ltd | 制御装置の試験方式 |
JPS63298174A (ja) * | 1987-05-29 | 1988-12-05 | Advantest Corp | Icテストシステム |
JP2001051026A (ja) * | 1999-08-13 | 2001-02-23 | Fujitsu Denso Ltd | 電子回路監視装置 |
JP2002131392A (ja) * | 2000-10-24 | 2002-05-09 | Ando Electric Co Ltd | アナログ・ディジタル特性試験回路 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5638383A (en) * | 1992-07-24 | 1997-06-10 | Trw Inc. | Advanced integrated avionics testing system |
US6101457A (en) * | 1992-10-29 | 2000-08-08 | Texas Instruments Incorporated | Test access port |
US5777873A (en) * | 1996-04-29 | 1998-07-07 | Mitsubishi Semiconductor America, Inc. | Automated test fixture control system |
US6988232B2 (en) * | 2001-07-05 | 2006-01-17 | Intellitech Corporation | Method and apparatus for optimized parallel testing and access of electronic circuits |
-
2004
- 2004-02-17 US US10/780,286 patent/US7096139B2/en not_active Expired - Fee Related
-
2005
- 2005-02-16 WO PCT/JP2005/002350 patent/WO2005078463A1/ja active Application Filing
- 2005-02-16 JP JP2005518036A patent/JP4721906B2/ja not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60135777A (ja) * | 1983-12-24 | 1985-07-19 | Fanuc Ltd | 制御装置の試験方式 |
JPS63298174A (ja) * | 1987-05-29 | 1988-12-05 | Advantest Corp | Icテストシステム |
JP2001051026A (ja) * | 1999-08-13 | 2001-02-23 | Fujitsu Denso Ltd | 電子回路監視装置 |
JP2002131392A (ja) * | 2000-10-24 | 2002-05-09 | Ando Electric Co Ltd | アナログ・ディジタル特性試験回路 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008268213A (ja) * | 2007-04-23 | 2008-11-06 | Advantest Corp | プログラムおよび試験装置 |
US8547125B2 (en) | 2010-01-26 | 2013-10-01 | Advantest Corporation | Test apparatus and test module |
Also Published As
Publication number | Publication date |
---|---|
JP4721906B2 (ja) | 2011-07-13 |
US20050182583A1 (en) | 2005-08-18 |
US7096139B2 (en) | 2006-08-22 |
JPWO2005078463A1 (ja) | 2007-10-18 |
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