WO2005062168A3 - User-programmable low-overhead multithreading - Google Patents

User-programmable low-overhead multithreading Download PDF

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Publication number
WO2005062168A3
WO2005062168A3 PCT/US2004/038987 US2004038987W WO2005062168A3 WO 2005062168 A3 WO2005062168 A3 WO 2005062168A3 US 2004038987 W US2004038987 W US 2004038987W WO 2005062168 A3 WO2005062168 A3 WO 2005062168A3
Authority
WO
WIPO (PCT)
Prior art keywords
multithreading
triggers
user
asynchronous
hardware
Prior art date
Application number
PCT/US2004/038987
Other languages
French (fr)
Other versions
WO2005062168A2 (en
Inventor
Perry Wang
Hong Wang
John Shen
Ashok Seshadri
Anthony Mah
William Greene
Ravi Chandra
Piyush Desai
Steve Shih-Wei Liao
Original Assignee
Intel Corp
Perry Wang
Hong Wang
John Shen
Ashok Seshadri
Anthony Mah
William Greene
Ravi Chandra
Piyush Desai
Steve Shih-Wei Liao
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Perry Wang, Hong Wang, John Shen, Ashok Seshadri, Anthony Mah, William Greene, Ravi Chandra, Piyush Desai, Steve Shih-Wei Liao filed Critical Intel Corp
Priority to CN200480041283.9A priority Critical patent/CN101218561B/en
Priority to DE112004002296T priority patent/DE112004002296B4/en
Publication of WO2005062168A2 publication Critical patent/WO2005062168A2/en
Publication of WO2005062168A3 publication Critical patent/WO2005062168A3/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4843Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30076Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/3009Thread control instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/54Interprogram communication
    • G06F9/542Event management; Broadcasting; Multicasting; Notifications

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Image Processing (AREA)

Abstract

A virtual multithreading hardware mechanism provides multi-threading on a single-threaded processor. Thread switches are triggered by user-defined triggers. Synchronous triggers may be defined in the form of special trigger instructions. Asynchronous triggers may be defined via special marking instructions that identify an asynchronous trigger condition. The asynchronous trigger condition may be based on a plurality of atomic processor events. Minimal context information, such as only an instruction pointer address, is maintained by the hardware upon a thread switch. In to contrast to traditional simultaneous multithreading schemes, the virtual multithreading hardware provides thread switches that are transparent to an operating system and that may be performed without operating system intervention.
PCT/US2004/038987 2003-12-05 2004-11-19 User-programmable low-overhead multithreading WO2005062168A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN200480041283.9A CN101218561B (en) 2003-12-05 2004-11-19 Processor, system and method of user-programmable low-overhead multithreading
DE112004002296T DE112004002296B4 (en) 2003-12-05 2004-11-19 User programmable multithreading with low overhead

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/728,649 US7631307B2 (en) 2003-12-05 2003-12-05 User-programmable low-overhead multithreading
US10/728,649 2003-12-05

Publications (2)

Publication Number Publication Date
WO2005062168A2 WO2005062168A2 (en) 2005-07-07
WO2005062168A3 true WO2005062168A3 (en) 2008-01-03

Family

ID=34633761

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/038987 WO2005062168A2 (en) 2003-12-05 2004-11-19 User-programmable low-overhead multithreading

Country Status (4)

Country Link
US (1) US7631307B2 (en)
CN (1) CN101218561B (en)
DE (1) DE112004002296B4 (en)
WO (1) WO2005062168A2 (en)

Families Citing this family (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7487502B2 (en) 2003-02-19 2009-02-03 Intel Corporation Programmable event driven yield mechanism which may activate other threads
US20050166177A1 (en) * 2004-01-27 2005-07-28 Ylian Saint-Hilaire Thread module chaining
US7490325B2 (en) 2004-03-13 2009-02-10 Cluster Resources, Inc. System and method for providing intelligent pre-staging of data in a compute environment
US20070266388A1 (en) 2004-06-18 2007-11-15 Cluster Resources, Inc. System and method for providing advanced reservations in a compute environment
EP1622009A1 (en) * 2004-07-27 2006-02-01 Texas Instruments Incorporated JSM architecture and systems
US8176490B1 (en) 2004-08-20 2012-05-08 Adaptive Computing Enterprises, Inc. System and method of interfacing a workload manager and scheduler with an identity manager
CA2586763C (en) 2004-11-08 2013-12-17 Cluster Resources, Inc. System and method of providing system jobs within a compute environment
US7810083B2 (en) * 2004-12-30 2010-10-05 Intel Corporation Mechanism to emulate user-level multithreading on an OS-sequestered sequencer
WO2006069494A1 (en) * 2004-12-31 2006-07-06 Intel Corporation Parallelization of bayesian network structure learning
US8863143B2 (en) 2006-03-16 2014-10-14 Adaptive Computing Enterprises, Inc. System and method for managing a hybrid compute environment
US7950012B2 (en) * 2005-03-16 2011-05-24 Oracle America, Inc. Facilitating communication and synchronization between main and scout threads
US9231886B2 (en) 2005-03-16 2016-01-05 Adaptive Computing Enterprises, Inc. Simple integration of an on-demand compute environment
CA2603577A1 (en) 2005-04-07 2006-10-12 Cluster Resources, Inc. On-demand access to compute resources
US7472256B1 (en) 2005-04-12 2008-12-30 Sun Microsystems, Inc. Software value prediction using pendency records of predicted prefetch values
US20070094213A1 (en) * 2005-07-14 2007-04-26 Chunrong Lai Data partitioning and critical section reduction for Bayesian network structure learning
US20070094214A1 (en) * 2005-07-15 2007-04-26 Li Eric Q Parallelization of bayesian network structure learning
US20070079294A1 (en) * 2005-09-30 2007-04-05 Robert Knight Profiling using a user-level control mechanism
US7774779B2 (en) * 2005-11-18 2010-08-10 At&T Intellectual Property I, L.P. Generating a timeout in a computer software application
US9003421B2 (en) * 2005-11-28 2015-04-07 Intel Corporation Acceleration threads on idle OS-visible thread execution units
US8065690B2 (en) * 2005-12-01 2011-11-22 Cisco Technology, Inc. Method and system for event-based remote procedure call implementation in a distributed computing system
US9754265B2 (en) * 2006-05-01 2017-09-05 At&T Intellectual Property I, L.P. Systems and methods to automatically activate distribution channels provided by business partners
US7502913B2 (en) * 2006-06-16 2009-03-10 Microsoft Corporation Switch prefetch in a multicore computer chip
GB2443507A (en) * 2006-10-24 2008-05-07 Advanced Risc Mach Ltd Debugging parallel programs
US20080141268A1 (en) * 2006-12-12 2008-06-12 Tirumalai Partha P Utility function execution using scout threads
WO2008091248A1 (en) * 2007-01-23 2008-07-31 Agere Systems Inc. Application switching in a single threaded architecture for devices
US8495627B2 (en) * 2007-06-27 2013-07-23 International Business Machines Corporation Resource allocation based on anticipated resource underutilization in a logically partitioned multi-processor environment
US8645974B2 (en) * 2007-08-02 2014-02-04 International Business Machines Corporation Multiple partition adjunct instances interfacing multiple logical partitions to a self-virtualizing input/output device
US8176487B2 (en) * 2007-08-02 2012-05-08 International Business Machines Corporation Client partition scheduling and prioritization of service partition work
US8574393B2 (en) * 2007-12-21 2013-11-05 Tsinghua University Method for making touch panel
US7996663B2 (en) * 2007-12-27 2011-08-09 Intel Corporation Saving and restoring architectural state for processor cores
US8225120B2 (en) * 2008-02-01 2012-07-17 International Business Machines Corporation Wake-and-go mechanism with data exclusivity
US8171476B2 (en) * 2008-02-01 2012-05-01 International Business Machines Corporation Wake-and-go mechanism with prioritization of threads
US8316218B2 (en) 2008-02-01 2012-11-20 International Business Machines Corporation Look-ahead wake-and-go engine with speculative execution
US8516484B2 (en) * 2008-02-01 2013-08-20 International Business Machines Corporation Wake-and-go mechanism for a data processing system
US8640141B2 (en) * 2008-02-01 2014-01-28 International Business Machines Corporation Wake-and-go mechanism with hardware private array
US8127080B2 (en) 2008-02-01 2012-02-28 International Business Machines Corporation Wake-and-go mechanism with system address bus transaction master
US8312458B2 (en) * 2008-02-01 2012-11-13 International Business Machines Corporation Central repository for wake-and-go mechanism
US8341635B2 (en) * 2008-02-01 2012-12-25 International Business Machines Corporation Hardware wake-and-go mechanism with look-ahead polling
US8732683B2 (en) * 2008-02-01 2014-05-20 International Business Machines Corporation Compiler providing idiom to idiom accelerator
US8880853B2 (en) * 2008-02-01 2014-11-04 International Business Machines Corporation CAM-based wake-and-go snooping engine for waking a thread put to sleep for spinning on a target address lock
US8386822B2 (en) * 2008-02-01 2013-02-26 International Business Machines Corporation Wake-and-go mechanism with data monitoring
US8145849B2 (en) 2008-02-01 2012-03-27 International Business Machines Corporation Wake-and-go mechanism with system bus response
US8725992B2 (en) 2008-02-01 2014-05-13 International Business Machines Corporation Programming language exposing idiom calls to a programming idiom accelerator
US8452947B2 (en) 2008-02-01 2013-05-28 International Business Machines Corporation Hardware wake-and-go mechanism and content addressable memory with instruction pre-fetch look-ahead to detect programming idioms
US8612977B2 (en) * 2008-02-01 2013-12-17 International Business Machines Corporation Wake-and-go mechanism with software save of thread state
US8788795B2 (en) * 2008-02-01 2014-07-22 International Business Machines Corporation Programming idiom accelerator to examine pre-fetched instruction streams for multiple processors
US8250396B2 (en) * 2008-02-01 2012-08-21 International Business Machines Corporation Hardware wake-and-go mechanism for a data processing system
US8082315B2 (en) * 2009-04-16 2011-12-20 International Business Machines Corporation Programming idiom accelerator for remote update
US8886919B2 (en) * 2009-04-16 2014-11-11 International Business Machines Corporation Remote update programming idiom accelerator with allocated processor resources
US8230201B2 (en) * 2009-04-16 2012-07-24 International Business Machines Corporation Migrating sleeping and waking threads between wake-and-go mechanisms in a multiple processor data processing system
US8145723B2 (en) * 2009-04-16 2012-03-27 International Business Machines Corporation Complex remote update programming idiom accelerator
US8327059B2 (en) * 2009-09-30 2012-12-04 Vmware, Inc. System and method to enhance memory protection for programs in a virtual machine environment
US11720290B2 (en) 2009-10-30 2023-08-08 Iii Holdings 2, Llc Memcached server functionality in a cluster of data processing nodes
US8423750B2 (en) 2010-05-12 2013-04-16 International Business Machines Corporation Hardware assist thread for increasing code parallelism
US8667253B2 (en) 2010-08-04 2014-03-04 International Business Machines Corporation Initiating assist thread upon asynchronous event for processing simultaneously with controlling thread and updating its running status in status register
US8793474B2 (en) 2010-09-20 2014-07-29 International Business Machines Corporation Obtaining and releasing hardware threads without hypervisor involvement
US8713290B2 (en) 2010-09-20 2014-04-29 International Business Machines Corporation Scaleable status tracking of multiple assist hardware threads
US8694832B2 (en) 2011-03-03 2014-04-08 International Business Machines Corporation Assist thread analysis and debug mechanism
US9201689B2 (en) * 2011-04-22 2015-12-01 Cray Inc. Software emulation of massive hardware threading for tolerating remote memory references
WO2013095570A1 (en) 2011-12-22 2013-06-27 Intel Corporation Instruction that specifies an application thread performance state
WO2013147887A1 (en) 2012-03-30 2013-10-03 Intel Corporation Context switching mechanism for a processing core having a general purpose cpu core and a tightly coupled accelerator
US9286081B2 (en) * 2012-06-12 2016-03-15 Apple Inc. Input device event processing
US9582320B2 (en) * 2013-03-14 2017-02-28 Nxp Usa, Inc. Computer systems and methods with resource transfer hint instruction
JP6477216B2 (en) * 2015-05-08 2019-03-06 富士通株式会社 Arithmetic device, thread switching method, and multi-thread program
US10019283B2 (en) * 2015-06-22 2018-07-10 Advanced Micro Devices, Inc. Predicting a context portion to move between a context buffer and registers based on context portions previously used by at least one other thread
CN106980546B (en) * 2016-01-18 2021-08-27 阿里巴巴集团控股有限公司 Task asynchronous execution method, device and system
US10558463B2 (en) 2016-06-03 2020-02-11 Synopsys, Inc. Communication between threads of multi-thread processor
US10628320B2 (en) * 2016-06-03 2020-04-21 Synopsys, Inc. Modulization of cache structure utilizing independent tag array and data array in microprocessor
US10318302B2 (en) 2016-06-03 2019-06-11 Synopsys, Inc. Thread switching in microprocessor without full save and restore of register file
US10613859B2 (en) 2016-08-18 2020-04-07 Synopsys, Inc. Triple-pass execution using a retire queue having a functional unit to independently execute long latency instructions and dependent instructions
US10552158B2 (en) 2016-08-18 2020-02-04 Synopsys, Inc. Reorder buffer scoreboard having multiple valid bits to indicate a location of data
US10210650B1 (en) * 2017-11-30 2019-02-19 Advanced Micro Devices, Inc. Primitive level preemption using discrete non-real-time and real time pipelines
US11513840B2 (en) * 2018-05-07 2022-11-29 Micron Technology, Inc. Thread creation on local or remote compute elements by a multi-threaded, self-scheduling processor
WO2020186630A1 (en) * 2019-03-21 2020-09-24 Huawei Technologies Co., Ltd. Serializing divergent accesses using peeling
US11474861B1 (en) * 2019-11-27 2022-10-18 Meta Platforms Technologies, Llc Methods and systems for managing asynchronous function calls
US11194503B2 (en) 2020-03-11 2021-12-07 Samsung Electronics Co., Ltd. Storage device having a configurable command response trigger

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999021081A1 (en) * 1997-10-23 1999-04-29 International Business Machines Corporation Method and apparatus for selecting thread switch events in a multithreaded processor
US20020055964A1 (en) * 2000-04-19 2002-05-09 Chi-Keung Luk Software controlled pre-execution in a multithreaded processor
US20030018686A1 (en) * 1999-04-29 2003-01-23 Stavros Kalafatis Method and system to perform a thread switching operation within a multithreaded processor based on detection of a stall condition
US20030061445A1 (en) * 2001-08-29 2003-03-27 Palle Birk Methods and apparatus for improving throughput of cache-based embedded processors

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2055964A (en) * 1934-09-26 1936-09-29 Granberg Meter Corp Flow shut-off mechanism
US3061445A (en) * 1959-04-30 1962-10-30 Abbott Lab Effervescent sweetening tablet
US3018686A (en) * 1961-01-10 1962-01-30 Sawyer S Inc Tachistoscope
US4539637A (en) * 1982-08-26 1985-09-03 At&T Bell Laboratories Method and apparatus for handling interprocessor calls in a multiprocessor system
JP3034873B2 (en) * 1988-07-01 2000-04-17 株式会社日立製作所 Information processing device
US5247676A (en) * 1989-06-29 1993-09-21 Digital Equipment Corporation RPC based computer system using transparent callback and associated method
US5179702A (en) * 1989-12-29 1993-01-12 Supercomputer Systems Limited Partnership System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling
US5390329A (en) * 1990-06-11 1995-02-14 Cray Research, Inc. Responding to service requests using minimal system-side context in a multiprocessor environment
US6098169A (en) * 1997-12-23 2000-08-01 Intel Corporation Thread performance analysis by monitoring processor performance event registers at thread switch
US6272520B1 (en) * 1997-12-31 2001-08-07 Intel Corporation Method for detecting thread switch events
US6560626B1 (en) * 1998-04-02 2003-05-06 Microsoft Corporation Thread interruption with minimal resource usage using an asynchronous procedure call
US6401155B1 (en) * 1998-12-22 2002-06-04 Philips Electronics North America Corporation Interrupt/software-controlled thread processing
US7222150B1 (en) * 2000-08-15 2007-05-22 Ikadega, Inc. Network server card and method for handling requests received via a network interface
US20020138706A1 (en) * 2001-03-21 2002-09-26 Littera, Inc. Reader-writer lock method and system
US6928645B2 (en) * 2001-03-30 2005-08-09 Intel Corporation Software-based speculative pre-computation and multithreading
US7047533B2 (en) * 2001-09-10 2006-05-16 Hewlett-Packard Development Company, L.P. Wait utility and method
US7117346B2 (en) * 2002-05-31 2006-10-03 Freescale Semiconductor, Inc. Data processing system having multiple register contexts and method therefor
US7228348B1 (en) * 2002-08-13 2007-06-05 Finisar Corporation System and method for triggering communications data capture
US8176298B2 (en) * 2002-10-08 2012-05-08 Netlogic Microsystems, Inc. Multi-core multi-threaded processing systems with instruction reordering in an in-order pipeline
US7010672B2 (en) * 2002-12-11 2006-03-07 Infineon Technologies Ag Digital processor with programmable breakpoint/watchpoint trigger generation circuit
US7376954B2 (en) * 2003-08-28 2008-05-20 Mips Technologies, Inc. Mechanisms for assuring quality of service for programs executing on a multithreaded processor
US6931354B2 (en) * 2003-11-13 2005-08-16 International Business Machines Corporation Method, apparatus and computer program product for efficient, large counts of per thread performance events

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999021081A1 (en) * 1997-10-23 1999-04-29 International Business Machines Corporation Method and apparatus for selecting thread switch events in a multithreaded processor
US20030018686A1 (en) * 1999-04-29 2003-01-23 Stavros Kalafatis Method and system to perform a thread switching operation within a multithreaded processor based on detection of a stall condition
US20020055964A1 (en) * 2000-04-19 2002-05-09 Chi-Keung Luk Software controlled pre-execution in a multithreaded processor
US20030061445A1 (en) * 2001-08-29 2003-03-27 Palle Birk Methods and apparatus for improving throughput of cache-based embedded processors

Also Published As

Publication number Publication date
DE112004002296T5 (en) 2006-09-28
US7631307B2 (en) 2009-12-08
US20050125802A1 (en) 2005-06-09
DE112004002296B4 (en) 2010-07-08
CN101218561A (en) 2008-07-09
CN101218561B (en) 2013-03-06
WO2005062168A2 (en) 2005-07-07

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