WO2005015488A1 - Chipkarte, chipkartenmodul sowie verfahren zur herstellung eines chipkartenmoduls - Google Patents
Chipkarte, chipkartenmodul sowie verfahren zur herstellung eines chipkartenmoduls Download PDFInfo
- Publication number
- WO2005015488A1 WO2005015488A1 PCT/DE2004/001363 DE2004001363W WO2005015488A1 WO 2005015488 A1 WO2005015488 A1 WO 2005015488A1 DE 2004001363 W DE2004001363 W DE 2004001363W WO 2005015488 A1 WO2005015488 A1 WO 2005015488A1
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- semiconductor chip
- chip
- chip card
- contact
- semiconductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07743—External electrical contacts
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07745—Mounting details of integrated circuit chips
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07745—Mounting details of integrated circuit chips
- G06K19/07747—Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
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- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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Definitions
- Chip card, chip card module and method for producing a chip card module 5 The invention relates to a chip card for contact-based data transmission, which consists of a card body and a chip card module inserted into the card body.
- the invention relates to a chip card module and a method for producing such a chip card module.
- Chip cards and chip card modules have been known for a long time and are described, for example, in DE 195 00 925 AI.
- .5 chip card module shown there in FIG. 4 has a substrate on which a semiconductor chip and the metallic connection areas are arranged, the semiconductor chip being connected to the connection areas via bond wires.
- the semiconductor chip and the bond wires are of a 'protecting them
- the semiconductor chip and the metallic connection areas are arranged on one side of the substrate. On the other side of the substrate are the contact areas for the contact-based data exchange of the chip card. Access openings to the contact
- the chip card module shown there is installed in a chip card by inserting it into the opening provided there and gluing it to the card body.
- the procedure is usually such that the semiconductor chips with their active 0 tops are fixed on a carrier tape facing upwards. Fixation on the carrier tape is usually done by gluing. At appropriate locations, the carrier tape has metallic surfaces, the underside of which is later used for contacting 5 the chip card module with the peripheral devices. Contacting of the connection areas on the active top sides of the semiconductor chip with these contact areas is carried out using wirebond technology.
- the wire bond method has the major disadvantage that the use of wire bond wires limits the miniaturization of the chip card module very strongly. It is not possible to achieve chip card modules with very low overall heights, since the wire bond wires have a spatial expansion that is not to be undercut.
- FIG. 11 of DE 195 00 925 AI mentioned at the beginning shows an alternative embodiment for a chip card module in which the contact areas and connection areas
- Chip scale packaging is also often referred to as "CSP”.
- the CSP which is a subspecies of flip-chip technology, is based on
- the active upper side of the semiconductor chips is drawn directly onto conductor tracks, and then onto these conductor tracks directly the solder balls, with which the semiconductor chip is then attached to a substrate.
- CSP technology A major disadvantage of CSP technology, however, is that the 5 active top side of the semiconductor chips available does not usually offer enough space to make all the necessary external contacts. Furthermore, the CSP technology is unsuitable for the production of chip card modules if only because the semiconductor chips that are used in chip .0 card modules are extremely strong miniaturization, i. H. an extremely strong "shrink".
- a chip card module with: a semiconductor chip with a rear side, with an active top side and with side surfaces; a plastic housing compound enveloping the semiconductor chip, which has at least one surface which is coplanar with the active upper side of the semiconductor chip; a first dielectric layer, which is also arranged on this surface and on the active upper side of the semiconductor chip; one or more redistribution metallization levels separated by further dielectric layers, which are connected to the active top side of the semiconductor chip; and - external contact areas which are formed on the outermost rewiring level, to which a contact metallization for contact-based data transmission is applied.
- This chip card module is distinguished by a very low overall height and does not have the problem of the chip scale package, since rewiring levels are provided in such a chip card module.
- chip cards for contact-based data transmission can be produced according to the present invention, which consist of a card body and an above chip card module installed in the card body.
- the present invention it is particularly favorable to produce the above-mentioned chip card modules using a method in which a semiconductor wafer with semiconductor chips arranged in rows and columns is first provided.
- the semiconductor chips have rear sides and active upper sides, the active upper sides being provided with inner contact surfaces. hen are. These inner contact surfaces are also called contact pads.
- the semiconductor wafer is then separated into individual semiconductor chips.
- the semiconductor chips are then applied to a carrier device, the individual semiconductor chips with their active upper sides being brought onto the upper side of the carrier device.
- a plastic package is then applied to the carrier device, so that a common carrier of plastic package is formed, the semiconductor chips being embedded in the plastic package.
- the carrier device is then removed and a first dielectric layer is applied to the now exposed active top sides of the semiconductor chips, which are embedded in a matrix of plastic, which now covers the active top sides of the semiconductor chips and the exposed surfaces of the encapsulated plastic housing compound.
- At least one or more redistribution metallization levels separated by further dielectric layers are then deposited onto this deposited first dielectric layer.
- the outermost rewiring metallization level then has external contact areas, to which the contact metallization is then applied, which serves for the contact-based data exchange of the chip card with its periphery.
- the common carrier made of plastic housing mass is separated into individual chip card modules.
- the common carrier made of plastic housing compound is made on the carrier device by means of injection molding processes with the aid of a molding tool.
- the common carrier can also be produced from plastic housing compound by centrifugal casting.
- the rewiring metallization levels can be applied to the common carrier made of plastic housing compound by applying a closed metal layer and subsequent structuring of the metal layer using photoresist technology.
- the rewiring metallization levels are applied to the common carrier made of plastic housing compound by printing technology, in particular by screen printing technology.
- FIG. 1 shows a chip card module from the prior art.
- FIGS. 2a to 2e show lateral cross-sectional views of a process sequence for forming a chip card module 1 with a plastic housing 2 according to the present invention.
- FIG. 1 shows a chip card module 1 'which has an electrically insulating substrate 2' on which a semiconductor chip 3 'is arranged. Furthermore, the chip card module l 1 has metallic connection areas 4 ′, the semiconductor chip 3 ′ being connected to the connection areas 4 ′ via bond wires 5 ′. The semiconductor chip 3 'and the bonding wires 5' are surrounded by a plastic casting compound 6 'protecting them. On one side of the electrically insulating substrate 2 ', the semiconductor chip 3' and the metallic connection surfaces 4 'are orderly. On the other side of the substrate 2 ', the contact areas 8' for a contact-based data exchange of the chip card module 1 "with its periphery are arranged. In the electrically insulating substrate 2 ', access openings 7' to the contact areas 8 'are left out. FIG. 1 is immediately closed derive that the bond wires 5 'make up the factor that limits the construction volume.
- a carrier device 8 is initially provided, which in the present case consists of a carrier frame 10 and an adhesive film 12.
- the carrier device 8 is subsequently equipped with semiconductor chips 3.
- the semiconductor chips 3 are applied with their active upper sides 5 to the upper side 9 of the adhesive film 12. This is preceded by the fact that a completely processed semiconductor wafer 4 is provided which has semiconductor chips 3 arranged in rows and columns.
- the semiconductor chips 3 have active top sides 5 and back sides 6, the active top sides 5 being provided with contact surfaces 7.
- the semiconductor wafer 4 is then separated into individual semiconductor chips 3, for example by sawing.
- the semiconductor chips 3 are encased with a plastic housing compound, so that a common carrier 11 made of plastic housing compound is formed on the carrier device 8 is, in which the semiconductor chips 3 are embedded.
- a common carrier 11 made of plastic housing compound is formed on the carrier device 8 is, in which the semiconductor chips 3 are embedded.
- the individual semiconductor chips 3 can be encased in wafer molding in the stencil printing process, in conventional encapsulation processes, in spin-on processes and in coating processes.
- the laminated adhesive film 12 is peeled off after the plastic housing compound has hardened.
- the carrier frame 10 is first removed and the adhesive film 12 adhering to the common carrier made of plastic housing compound 11 is either peeled off or peeled off.
- the common carrier 11 is divided, which is indicated by dash-dotted lines in FIG. 2e, so that individual chip card modules 1 with a plastic housing 2 are present.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE502004008355T DE502004008355D1 (de) | 2003-07-28 | 2004-06-28 | Chipkarte, chipkartenmodul sowie verfahren zur herstellung eines chipkartenmoduls |
EP04738809A EP1649412B1 (de) | 2003-07-28 | 2004-06-28 | Chipkarte, chipkartenmodul sowie verfahren zur herstellung eines chipkartenmoduls |
US11/341,892 US7575173B2 (en) | 2003-07-28 | 2006-01-30 | Smart card, smart card module, and a method for production of a smart card module |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10334578.7 | 2003-07-28 | ||
DE10334578A DE10334578A1 (de) | 2003-07-28 | 2003-07-28 | Chipkarte, Chipkartenmodul sowie Verfahren zur Herstellung eines Chipkartenmoduls |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/341,892 Continuation US7575173B2 (en) | 2003-07-28 | 2006-01-30 | Smart card, smart card module, and a method for production of a smart card module |
Publications (1)
Publication Number | Publication Date |
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WO2005015488A1 true WO2005015488A1 (de) | 2005-02-17 |
Family
ID=34129469
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2004/001363 WO2005015488A1 (de) | 2003-07-28 | 2004-06-28 | Chipkarte, chipkartenmodul sowie verfahren zur herstellung eines chipkartenmoduls |
Country Status (4)
Country | Link |
---|---|
US (1) | US7575173B2 (de) |
EP (1) | EP1649412B1 (de) |
DE (2) | DE10334578A1 (de) |
WO (1) | WO2005015488A1 (de) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007007233A2 (en) * | 2005-07-07 | 2007-01-18 | Koninklijke Philips Electronics N.V. | Package, method of manufacturing the same and use thereof |
WO2007087660A1 (de) * | 2006-02-02 | 2007-08-09 | At & S Austria Technologie & Systemtechnik Aktiengesellschaft | Leiterplattenelement mit wenigstens einem eingebetteten bauelement sowie verfahren zum einbetten zumindest eines bauelements in einem leiterplattenelement |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2895547B1 (fr) * | 2005-12-26 | 2008-06-06 | Oberthur Card Syst Sa | Procede de fabrication d'une carte a microcircuit |
DE102007034949A1 (de) * | 2007-07-26 | 2009-02-05 | Siemens Ag | Einheitlich normierte Leistungspackages |
TWI360207B (en) | 2007-10-22 | 2012-03-11 | Advanced Semiconductor Eng | Chip package structure and method of manufacturing |
TWI456715B (zh) * | 2009-06-19 | 2014-10-11 | Advanced Semiconductor Eng | 晶片封裝結構及其製造方法 |
TWI466259B (zh) * | 2009-07-21 | 2014-12-21 | Advanced Semiconductor Eng | 半導體封裝件、其製造方法及重佈晶片封膠體的製造方法 |
TWI405306B (zh) * | 2009-07-23 | 2013-08-11 | Advanced Semiconductor Eng | 半導體封裝件、其製造方法及重佈晶片封膠體 |
US20110084372A1 (en) | 2009-10-14 | 2011-04-14 | Advanced Semiconductor Engineering, Inc. | Package carrier, semiconductor package, and process for fabricating same |
US8378466B2 (en) | 2009-11-19 | 2013-02-19 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with electromagnetic interference shielding |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
US8372689B2 (en) | 2010-01-21 | 2013-02-12 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof |
US8320134B2 (en) | 2010-02-05 | 2012-11-27 | Advanced Semiconductor Engineering, Inc. | Embedded component substrate and manufacturing methods thereof |
TWI411075B (zh) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US8278746B2 (en) | 2010-04-02 | 2012-10-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages including connecting elements |
US8624374B2 (en) | 2010-04-02 | 2014-01-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof |
US8941222B2 (en) | 2010-11-11 | 2015-01-27 | Advanced Semiconductor Engineering Inc. | Wafer level semiconductor package and manufacturing methods thereof |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
US11907791B2 (en) * | 2013-01-18 | 2024-02-20 | Amatech Group Lijited | Smart cards with metal layer(s) and methods of manufacture |
ITUB20155233A1 (it) * | 2015-10-30 | 2017-04-30 | Automation 4 Industiral Solutions S R L | Metodo di impianto per la realizzazione di dispositivi rfid |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4424396A1 (de) * | 1994-07-11 | 1996-01-18 | Ibm | Trägerelement zum Einbau in Chipkarten oder anderen Datenträgerkarten |
US6013945A (en) * | 1993-08-10 | 2000-01-11 | Giesecke & Devrient Gmbh | Electronic module for data cards |
DE19845665A1 (de) * | 1998-10-05 | 2000-04-20 | Orga Kartensysteme Gmbh | Verfahren zur Herstellung eines Trägerelements für einen IC-Baustein zum Einbau in Chipkarten |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4421607A1 (de) * | 1994-06-21 | 1996-01-04 | Giesecke & Devrient Gmbh | Verfahren zur Herstellung von Datenträgern |
DE19500925C2 (de) * | 1995-01-16 | 1999-04-08 | Orga Kartensysteme Gmbh | Verfahren zur Herstellung einer kontaktlosen Chipkarte |
US6607135B1 (en) * | 1997-06-23 | 2003-08-19 | Rohm Co., Ltd. | Module for IC card, IC card, and method for manufacturing module for IC card |
FR2796183B1 (fr) * | 1999-07-07 | 2001-09-28 | A S K | Ticket d'acces sans contact et son procede de fabrication |
DE10004410A1 (de) * | 2000-02-02 | 2001-08-16 | Infineon Technologies Ag | Halbleiterbauelement mit an der Unterseite befindlichen Kontakten und Verfahren zur Herstellung |
WO2001062517A1 (fr) * | 2000-02-22 | 2001-08-30 | Toray Engineering Company,Limited | Carte d'identification sans contact ou analogue et procede de fabrication correspondant |
DE10126734B4 (de) * | 2001-05-31 | 2009-02-26 | Qimonda Ag | Umverdrahtungsverfahren und damit hergestelltes Bauelement |
-
2003
- 2003-07-28 DE DE10334578A patent/DE10334578A1/de not_active Withdrawn
-
2004
- 2004-06-28 DE DE502004008355T patent/DE502004008355D1/de active Active
- 2004-06-28 WO PCT/DE2004/001363 patent/WO2005015488A1/de active Search and Examination
- 2004-06-28 EP EP04738809A patent/EP1649412B1/de not_active Expired - Fee Related
-
2006
- 2006-01-30 US US11/341,892 patent/US7575173B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6013945A (en) * | 1993-08-10 | 2000-01-11 | Giesecke & Devrient Gmbh | Electronic module for data cards |
DE4424396A1 (de) * | 1994-07-11 | 1996-01-18 | Ibm | Trägerelement zum Einbau in Chipkarten oder anderen Datenträgerkarten |
DE19845665A1 (de) * | 1998-10-05 | 2000-04-20 | Orga Kartensysteme Gmbh | Verfahren zur Herstellung eines Trägerelements für einen IC-Baustein zum Einbau in Chipkarten |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007007233A2 (en) * | 2005-07-07 | 2007-01-18 | Koninklijke Philips Electronics N.V. | Package, method of manufacturing the same and use thereof |
WO2007007233A3 (en) * | 2005-07-07 | 2007-07-05 | Koninkl Philips Electronics Nv | Package, method of manufacturing the same and use thereof |
WO2007087660A1 (de) * | 2006-02-02 | 2007-08-09 | At & S Austria Technologie & Systemtechnik Aktiengesellschaft | Leiterplattenelement mit wenigstens einem eingebetteten bauelement sowie verfahren zum einbetten zumindest eines bauelements in einem leiterplattenelement |
EP2259311A2 (de) | 2006-02-02 | 2010-12-08 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Verfahren zum Einbetten zumindest eines Bauelements in einem Leiterplattenelement |
EP2259311A3 (de) * | 2006-02-02 | 2014-01-15 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Verfahren zum Einbetten zumindest eines Bauelements in einem Leiterplattenelement |
Also Published As
Publication number | Publication date |
---|---|
US7575173B2 (en) | 2009-08-18 |
US20060175419A1 (en) | 2006-08-10 |
DE10334578A1 (de) | 2005-03-10 |
EP1649412B1 (de) | 2008-10-29 |
EP1649412A1 (de) | 2006-04-26 |
DE502004008355D1 (de) | 2008-12-11 |
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