WO2004081944A1

WO2004081944A1 - Non-volatile, integrated memory cell, and method for writing or reading information into/out of the memory cell

Info

Publication number: WO2004081944A1
Application number: PCT/DE2004/000456
Authority: WO
Inventors: Manfred Pröll; Stephan Schröder; Evangelos Stavrou; Kön VAN DER ZANDEN
Original assignee: Infineon Technologies Ag
Priority date: 2003-03-11
Filing date: 2004-03-09
Publication date: 2004-09-23
Also published as: DE10310573A1

Abstract

The invention relates to a non-volatile, integrated memory cell (4) comprising a word line (20), a bit line (10) which crosses the word line (20) and is arranged on a point of intersection above or below the word line, and a layer (40) consisting of a phase change material which is arranged between the bit line and the word line and forms an electrical resistance (Rx) between the word line (20) and the bit line (10). The phase change material has a transition temperature (Tcrit) above which it is amorphous, and below which it is either amorphous with a first electrical resistance or crystalline with a second electrical resistance. The first and second electrical resistances are different. Logical states ('0', '1') can be stored by heating the layer (40) by means of a targeted current flow (Ix) and then cooling said layer in a controlled manner by means of a reduced current flow (Ix). According to the strength of the current flow (Ix), an amorphous state is obtained when the layer is cooled rapidly and a crystalline state is obtained when the layer is cooled slowly. Said state can be determined by measuring the electrical resistance (Rx) in order to read the logical information.

Description

description

Non-volatile, integrated memory cell and method for writing or reading information into / from the memory cell

The invention relates to a non-volatile, integrated memory cell, a semiconductor memory having a multiplicity of non-volatile, integrated memory cells and a method for writing and reading information into / from the non-volatile, integrated memory cell ,

In semiconductor memory chips, information is typically stored in cells in which the logical content of the information is represented by an electrical charge. In the case of rewritable memory cells, dynamic memories are often used, with which a high packing density of the cells can be achieved on a substrate surface. In dynamic memory cells, the electrical charges are stored in capacitors, for example trench capacitors, which are formed in the substrate. A disadvantage of this dynamic storage concept is that, due to charge losses in the form of leakage currents, so-called refresh processes have to be carried out at periodic intervals in order to refresh the charge content in the capacitor. This causes a loss of time and also requires circuitry to enable refreshing.

Another disadvantage is that the manufacturing process requires a large number of lithographic steps with deposition processes of very different materials. This makes the manufacturing process more expensive. Another disadvantage is that the dynamic memory cells are sensitive to external radiation. One solution to the problem is to replace the concept of dynamic but volatile charge storage with the provision of non-volatile memory cells. So-called magnetic memories, also called MRAM (magnetic random access memory), have been proposed for this purpose. In this concept, as can be seen in FIG. 1, layer stacks of thin magnetic layers are arranged between the crossing points of word and bit lines that define the memory cells. Logical states "1" and "0" are represented by the magnetic state of the layers of the layer stack relative to one another. The layer stack usually has two ferromagnetic layers, which can be separated by a thin oxide layer, for example as a tunnel layer.

The magnetic orientation of the one ferromagnetic layer is generally static, i.e. unchangeable during a save or read operation. The magnetic orientation of the other ferromagnetic layer can take a direction parallel or anti-parallel. A storage process is made possible in this other layer if the magnetic field resulting from a current flow in the word or write line is superimposed on the magnetic field which is formed by a current flowing simultaneously in the bit line. If the superposition of the two magnetic fields exceeds a critical value, the direction of magnetization can be rotated u from a parallel to an antiparallel state - or vice versa - so that changed storage information is present in the magnetic storage cell.

However, if a current only flows through one of the two lines, either the word line or the bit line, the induced magnetic field is too weak to cause a change in the direction of magnetization. In this way, only a certain magnetic memory cell in a memory cell field are described, which is arranged at the intersection of an activated word and bit line.

When the stored information is read out, a subcritical current is generated which flows through the magnetic layer stack at a voltage applied between a word line and the bit line. This exploits the effect that the electrical resistance of the magnetic memory cell depends on the mutual alignment of the magnetization directions. This electrical current can be measured with an evaluation unit. The voltage and the current flow are thus known, so that the resistance of the magnetic memory cell can be determined from this. The change in resistance depending on the magnetization state is attributed to the tunnel (TMR) or giant magnetoresistive (GMR) effect.

The MRAM concept enables memory cells with non-volatile memory content to be produced, the production of which requires a comparatively low technological outlay.

However, there are disadvantages with this storage concept. For example, there is a manufacturing-related spread of coercive field strengths, i.e. Field strengths, which for the

Switching the direction of magnetization of the magnetic layer of a respective memory cell are at least necessary. The magnetic electrical properties are based on the scattering of the thicknesses of individual layers in the layer stack. Even small deviations in the thickness of the intermediate oxide layer in the layer stack from a desired value are particularly critical.

Furthermore, in the case of a high storage density, i.e. a large degree of miniaturization, a cross talk of

Writes from adjacent memory cells to other memory cells are quite possible. This effect is particularly at small distances between adjacent memory cells due to the magnetic dipole interaction of the layers concerned.

Therefore, the further miniaturization of memory chips in the case of the MRAM concept must also be viewed very critically. For magnetic materials with particularly small dimensions there is also the so-called superparamagnetic limit, below which it is no longer possible to store information in the form of a magnetization direction.

It is therefore the object of the present invention to provide a non-volatile memory which can be produced with little technological effort and which avoids the aforementioned disadvantages. In particular, the task is to offer a memory in which the storage process in adjacent memory cells does not cause any interactions. It is a particular object of the present invention to offer a memory cell whose non-volatile memory content can be evaluated by measuring an electrical current.

The object is achieved by a non-volatile, integrated memory cell, comprising: a word line, a bit line which crosses the word line and is arranged at a crossing point above or below the word line, a layer comprising a phase change material which is between the bit line and the word line and an electrical resistance between the word and the bit line, wherein the phase change material has a transition temperature above which the phase change material has an amorphous structure and below which the phase change material either an amorphous structure with a first electrical resistance or a crystalline

Having a structure with a second electrical resistance, the first and second electrical resistance being different.

The object is also achieved by means of a semiconductor memory with a multiplicity of the non-volatile, integrated memory cells mentioned. In addition, the object is achieved by a method for writing and reading out information in the non-volatile, integrated memory cell according to independent claims 9 and 10.

The method enables information to be stored on the basis of a phase state of a layer. The change of a phase state, i.e. a storage process is achieved by a change in temperature. The heat absorption required for the temperature change is achieved by a current which flows through the storage layer between the word and bit lines. The following applies

p ~ T T?

where P _{w is} the thermal output, I _{x is} the current flowing through the layer and R _{x is} the resistance formed by the layer. In addition to the material properties, the resistance R _x also depends on the cross-sectional area of the layer. R _x ~ 1 / A applies, where A is the cross-sectional area.

If conventional materials are heated in this way, which, for example, have a crystalline phase structure at room temperature, the phase structure can be changed by the targeted heating due to the current flowing between the word line and the bit line. The material can assume an amorphous phase state, for example.

If the layer cools down again after the current is switched off, the original phase state usually occurs again. Within the scope of the invention it is now provided that materials lien with special properties known as phase change materials. With them, the phase state after falling below a critical transition temperature depends on the rate of temperature decrease. You can therefore assume two different phase states at room temperature, for example. For the invention, use is made of the fact that the rate of temperature decrease can be controlled by a targeted control of the current flowing through the layer. For example, with a decrease in temperature that is greater than a material-dependent limit, an amorphous phase state, and with a decrease in temperature that is smaller than the material-dependent limit, a crystalline state can be set for the phase change material.

If at a given operating temperature of the semiconductor memory for the phase change material in question of the layer between the word and bit lines, depending on the material, there are three or even more stable phase states which are set as a function of the rate of temperature decrease, then the invention even makes ternary memories Logic or higher order possible.

The storage process consists in exceeding the transition temperature, ie the temperature from which at least two different phase states can be achieved by cooling, and the specifically controlled cooling process. The transition temperature can be exceeded by applying a sufficiently high voltage to the bit and word lines so that the current intensity exceeds a corresponding value or by choosing the cross-sectional area A of the phase change layer to be sufficiently small so that the resistance R _{x is} a for the corresponding power consumption P _w exceeds the corresponding value.

The phase change material of the present invention has yet another property that is used to read out the stored information is necessary: the specific resistance of the material depends on the internal phase structure. A second voltage, which is lower than that of the voltage applied for the storage, is now applied between the word and bit lines. Provided that a current is impressed due to the low voltage which is too low to cause a phase change, the current intensity I _x depends in particular on the resistance of the phase change layer according to the relationship I _x = U / R _x . It is provided to measure the current strength with an evaluation unit at a predetermined voltage between the word and bit lines in order to obtain information about the phase state of the memory layer.

The properties of phase change materials are described, for example, in Wamwangi, D., Walter, N., Wuttig, M. in "Crystallization kinetics of Ge ₄ SbιTe ₅ ", abstracts of the meeting HL 35, lecture HL 35.4, the DPG spring conference in Dresden, March 24th - March 28th, 2003 (http://dpg.rz.uni-ulm.de/prog/html/hl_35.html) Such materials are known for example in connection with the use in rewritable optical storage media such as DVD ( Digital video discs).

The phase change materials according to the invention have a transition temperature of at most 600 ° C., preferably less than 400 ° C. These materials enable operation that is gentle on the entire semiconductor memory component. In particular, the glass layers encasing the conductor tracks made of titanium nitride or tungsten silicide are not made to flow. Particularly advantageous results can be achieved if future phase change materials are found whose critical transition temperature is less than 200 ° C.

According to an embodiment of the invention it is provided as

Phase change material a binary or a ternary (pseudo- binary) alloy to use. This has a particularly high long-term stability.

According to a further embodiment of the present invention, it is provided to use a material comprising germanium, antimony or tellurium for the ternary alloy. These materials have proven to be particularly stable in various proportions. For example, Ge ₄ SbιTe ₅ can be used.

The short-term heating and cooling process has the effect that the interaction of adjacent memory cells in a semiconductor memory comprising a large number of the non-volatile integrated memory cells according to the invention is particularly low. Due to the local heating only, crosstalk during a write process from one cell to the next is very unlikely, even with the highest integration density. This enables higher integration densities than, for example, an MRAM memory.

Furthermore, manufacturing-related scattering of the layer thicknesses does not have the disadvantageous effect that is the case with the MRAM. The electrical resistance of the phase change layer varies at best linearly with the layer thickness, while an exponential relationship arises, for example, in the case of the tunnel magnetoresistive effect. For this purpose, according to the invention a stack of layers comprising stacking materials is not necessary, although the case is to be included, the memory according to the invention can be implemented in a technologically much simpler manner than the non-volatile MRAM memory.

Furthermore, there are no physical limits for the memory according to the invention that would prevent further miniaturization. Both cost reduction and a largely scalable semiconductor memory are therefore achieved. The invention will now be explained in more detail using an exemplary embodiment with the aid of a drawing. In it show:

FIG. 1 shows an embodiment of an arrangement of magnetoresistive memory cells according to the prior art,

FIG. 2 shows an exemplary embodiment of the phase change memory according to the present invention,

FIG. 3 shows a diagram with a time-controlled current intensity and the temperature resulting therefrom for storing information in the memory cells according to the invention.

Figure 1 shows a schematic representation of a magnetic memory with many non-volatile memory cells 3- 3 "". The memory cells 3-3 "" are arranged between word lines 20, 21 and bit lines 10, 11 as a layer stack. The memory cell 3 comprises, for example antiferromagnetic layer 30, a ferromagnetic layer 32 and an oxide layer 31 arranged between them. A storage state "1" is represented, for example, by the antiparallel orientation of the magnetization directions 37 and 38 of the two magnetic layers The magnetic memory shown in Figure 1 is a non-volatile memory according to the prior art.

FIG. 2 shows an exemplary embodiment of a semiconductor memory according to the invention with three memory cells 4, 4 ', 4''shown in sections. Layers comprising a phase change material are arranged between a word line 20 (and for example a word line 21 (not shown), etc.) and bit lines 10, 11, 12. In the embodiment, the layer comprises a ternary alloy from Ge ₄ SbιTe ₅ . Tempering this material above the phase transition temperature T _{kr t} causes a change in resistance from 200 Ωcm to 3.1 • 10 ^"3 Ωcm. The change in resistance corresponds to a phase change from an amorphous phase state in a crystalline rock salt phase state.

The word line 20 and the bit lines 10 - 12 are each connected to a voltage source U _x or U ₂ . Furthermore, they are connected to a basic potential via terminating resistors R _t . The bit lines 10, 11, 12 are also connected to evaluation units 50, 51, 52 for evaluating the current signal.

In the state shown in FIG. 2, the memory cells 4, 4 ″ are characterized by an amorphous state of the phase change

Layer 40, and the memory cells 4 'are characterized by a crystalline state. The amorphous state represents the logical "1" and the crystalline state represents the logical "0". A write-in and read-out process on the memory cells 4 'is described by way of example below.

FIG. 3 shows the time course of the current intensity impressed into the word line for a write-in process. In the exemplary embodiment, the voltage Ui is advantageously set equal to the negative amount of the voltage U ₂ . This can be achieved, for example, by a voltage inverter. The course of the current over time is shown by broken lines in FIG. 3. The logical "0" should first be overwritten by a logical "1", ie the crystalline state must be converted into an amorphous phase. At time ti, the word line 20 switches through the memory layer 40 to the bit line 11 between the voltage potential Ui and the voltage potential U ₂ . The potentials are dimensioned such that a sufficiently strong current flows through the memory layer 40 only of the memory cell 4 '. Heating takes place in such a way that the transition temperature T _kri _t n of the phase change layer 40 is skipped, as can be seen in the figure in the solid line. The phase change to the amorphous phase is completed at the latest after a time t ₂ . The time difference t ₂ - t _x is 6.5 ns (nanoseconds). At time t ₂ , the connection of word line 20 and bit line 11 to voltage sources Ui and U _{2 is} opened, ie the current is switched off.

As a result, the temperature of the phase change layer 40 cools down. Since there is no longer any heat source at all, the cooling rate assumes a value that is above a critical cooling rate. As a result, the phase change material maintains its amorphous phase. After a time interval of approximately 25 ns, the temperature has dropped to a value Ti. The entry cycle is completed after time T ₃ and a subsequent writing or reading process can take place. The memory cell 4 'is now in the amorphous phase, ie the logical "1" has been stored.

At a point in time t, the logical “0” is now to be written into the memory cell 4 ′ again, ie a crystalline phase is to be formed in the phase change material. Again, the voltage sources Ui and U _{2 are} connected to the word or bit line 20, 11 in order to generate a maximum current. The phase change layer 40 is thereby amorphized. After a time of 6.5 ns repeatedly, the voltage source U _{2 is} now not disconnected from the bit line 11, but rather switched to the basic potential. The voltage difference between the voltage source Ui and the voltage source U ₂ now bears only half of the maximum voltage difference. A current is still flowing, which generates residual heat in the phase change layer. This is not enough for the temperature above However, keeping the critical transition temperature for the amorphization causes the phase change layer 40 to cool down more slowly.

After a time t ₆ , the phase change layer 40 is thus cooled to a temperature T ₂ , which is above the temperature Ti, which was reached after the cooling process in the first storage. The cooling rate is therefore lower than in the first case and is also below a critical cooling rate. As a result, the phase change material of layer 40 recrystallizes. After a time t ₆ , the residual current is also switched off, so that a further write-in or read-out process can be started. Due to the crystalline phase of the phase change layer 40, a logic "0" is now stored again.

A readout process is carried out in which one of the two voltage sources Ui or U ₂ is in turn switched to ground potential, so that a subcritical current flows through the storage layer 40. The strength of this current signal can be evaluated with the evaluation unit 51. If there is an amorphous phase, the resistance is comparatively high and there is therefore a low current flow for a given voltage difference. If, in turn, there is a crystalline phase, the resistance is comparatively low and a large current is determined. Technically, the evaluation unit is implemented by a comparator against a reference current. LIST OF REFERENCE NUMBERS

3,3 ', 3 "MRAM memory cells (state of the art)

4, 4 ', 4' 'phase change memory cells

10-12 bit line

20, 21 word line

50-52 evaluation units

R _x electrical resistance of the phase change medium

T _r it transition temperature of the phase change medium

Claims

Claims:

1. Non-volatile, integrated memory cell (4), comprising

- a word line (20), - a bit line (10) which crosses the word line (20) and is arranged at a crossing point above or below the word line,

a layer (40) comprising a phase change material which is arranged between the bit line and the word line and forms an electrical resistance (R _x ) between the word line (20) and the bit line (10),

- The phase change material being a transition temperature

(Tkrit), a) above which the phase change material has an amorphous structure, and b) below which the phase change material, depending on the rate of cooling based on the transition temperature (T _kr i _t ), either an amorphous structure with a first electrical resistance or one has a crystalline structure with a second electrical resistance, the first and the second electrical resistance being different.

2. Memory cell according to claim 1, characterized in that the transition temperature (T _kr i _t ) of the phase change material is less than 600 ° Celsius.

3. Memory cell according to claim 2, characterized in that the transition temperature (T _kr i _t ) of the phase change material is less than 400 ° Celsius.

4. Memory cell according to one of claims 1 to 3, characterized in that the phase change material comprises a binary, a ternary, a quaternary or a pseudobinary alloy.

5. Memory cell according to claim 4, d a d u r c h g e k e n n z e i c h n e t that the ternary alloy comprises germanium, antimony and tellurium.

6. The memory cell of claim 1, a first voltage source connected to the word line (20) and a second voltage source connected to the bit line (10) to inject a current into the phase change layer (40).

7. Memory cell according to claim 1, characterized by an evaluation unit for measuring a current flowing between the first and the second voltage source for determining the electrical resistance (R _x ) of the layer.

8. Semiconductor memory with a plurality of non-volatile, integrated memory cells according to one of claims 1 to 7, wherein in each case at the intersection of the overlapping word (20) and bit lines (10) a layer (40) comprising the phase change material between the word ( 20) and the bit line (10) is arranged.

9. A method for writing information into the non-volatile, integrated memory cell according to one of claims 1 to 7, comprising

- Applying a voltage with a first value between the word line (20) and the bit line (10), so that a current

(I _x ) flows between the word (20) and the bit line (10) through the layer (40) with an electrical resistance (R _x ),

Converting a power (P _w ) of the current (I _x ) into a heating of the layer so that the transition temperature (T _kr i _t ) in the layer (40) is exceeded, the phase change material changing into an amorphous phase, - to store a first logic value ("0") in the layer (40) reducing the voltage to a second value which is less than the first value in order to slowly cool the layer, the phase change material of the layer (40) being different from the amorphous phase changes into a crystalline phase, or

- for storing a second logic value ("1") in the layer (40) reducing the voltage to a third value, which is smaller than the second value, in order to cool the layer (40) rapidly, the phase change material of the layer (40 ) remains in the amorphous phase.

10. A method for reading information from the non-volatile, integrated memory cell (4) according to one of claims 1 to 7, comprising

- applying a voltage between the word line (20) and the bit line (10) so that a current (I _x ) between the word (20) and the bit line (10) flows through the layer (40) with the phase change material, Measuring the strength of the current (I _x ) flowing through the layer comprising the phase change material through the evaluation unit,

- Comparison of the measured strength of the current (I _x ) with a reference value, - Assignment of a logical value ("0", "1") depending on the comparison result.