WO2004064254A3 - A logic circuit - Google Patents
A logic circuit Download PDFInfo
- Publication number
- WO2004064254A3 WO2004064254A3 PCT/GB2004/000135 GB2004000135W WO2004064254A3 WO 2004064254 A3 WO2004064254 A3 WO 2004064254A3 GB 2004000135 W GB2004000135 W GB 2004000135W WO 2004064254 A3 WO2004064254 A3 WO 2004064254A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- inputs
- control
- switching
- subcircuit
- control output
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1737—Controllable logic circuits using multiplexers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/607—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters
Abstract
A circuit for selecting one of a second set of binary inputs according to the number of high input signals applied to a first set of binary inputs, the circuit comprising: a first subcircuit having said first set of binary inputs, and logic for generating a set of control output signals, wherein each control output signal represents whether or not the first set of binary inputs has exactly a predetermined number of high input signals, and wherein each control output signal corresponds to a different said predetermined number of high input signals; and a second subcircuit having said second set of binary inputs, a set of control inputs for receiving control output signals from the first subcircuit, and logic comprising a plurality of switching components including one or more pass gates, each said switching component being switchable to connect or isolate one of the second set of inputs to a common output, wherein the control inputs are used to control the switching of the switching components, and wherein the first and second subcircuits are configured such that only one switching component can be switched to connect at any one time.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US43985203P | 2003-01-14 | 2003-01-14 | |
US60/439852 | 2003-01-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2004064254A2 WO2004064254A2 (en) | 2004-07-29 |
WO2004064254A3 true WO2004064254A3 (en) | 2004-09-10 |
Family
ID=31888459
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/GB2004/000135 WO2004064254A2 (en) | 2003-01-14 | 2004-01-14 | A logic circuit |
Country Status (3)
Country | Link |
---|---|
US (1) | US6909767B2 (en) |
GB (1) | GB2398944B (en) |
WO (1) | WO2004064254A2 (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7260595B2 (en) * | 2002-12-23 | 2007-08-21 | Arithmatica Limited | Logic circuit and method for carry and sum generation and method of designing such a logic circuit |
US7725512B1 (en) * | 2006-04-26 | 2010-05-25 | Altera Corporation | Apparatus and method for performing multiple exclusive or operations using multiplication circuitry |
KR100851993B1 (en) * | 2007-02-09 | 2008-08-13 | 주식회사 하이닉스반도체 | Apparatus for supplying overdriving signal |
US7468685B1 (en) * | 2007-08-20 | 2008-12-23 | Fairchild Semiconductor Corporation | Clockless serialization using delay circuits |
CN103019126B (en) * | 2013-01-05 | 2018-03-27 | 范仲金 | Numerical control switch system |
JP2016086253A (en) * | 2014-10-24 | 2016-05-19 | ソニー株式会社 | Power-on reset circuit and high frequency communication device |
CN105743497B (en) * | 2014-12-08 | 2018-12-07 | 中芯国际集成电路制造(上海)有限公司 | Frequency divider and its method and phaselocked loop and semiconductor device comprising the frequency divider |
RU2609743C1 (en) * | 2015-09-21 | 2017-02-02 | Олег Александрович Козелков | Logic module |
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US3711692A (en) * | 1971-03-15 | 1973-01-16 | Goodyear Aerospace Corp | Determination of number of ones in a data field by addition |
US5995029A (en) * | 1996-11-06 | 1999-11-30 | Hyundai Electronics Industries Co., Ltd. | Parallel bit counter using bit sorters |
US6430251B1 (en) * | 2000-10-24 | 2002-08-06 | Sun Microsystems, Inc. | 4-Bit population count circuit |
US6470443B1 (en) * | 1996-12-31 | 2002-10-22 | Compaq Computer Corporation | Pipelined multi-thread processor selecting thread instruction in inter-stage buffer based on count information |
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US3634658A (en) | 1970-03-19 | 1972-01-11 | Sperry Rand Corp | Parallel bit counter |
US3757098A (en) | 1972-05-12 | 1973-09-04 | Rca Corp | Carry generation means for multiple character adder |
US4168530A (en) | 1978-02-13 | 1979-09-18 | Burroughs Corporation | Multiplication circuit using column compression |
JPS6022767B2 (en) | 1979-10-01 | 1985-06-04 | 株式会社東芝 | binary multiplier cell circuit |
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US4463344A (en) | 1981-12-31 | 1984-07-31 | International Business Machines Corporation | Method and apparatus for generating a noiseless sliding block code for a (2,7) channel with rate 1/2 |
FR2540376B3 (en) | 1983-02-04 | 1987-01-09 | Coustenoble Jean P | PORTABLE APPARATUS FOR RECORDING ELECTROCARDIOGRAMS |
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KR100359965B1 (en) | 1995-04-11 | 2003-03-15 | 캐논 가부시끼가이샤 | Processor, its operation method, and data processor |
TW298687B (en) | 1995-04-21 | 1997-02-21 | Hitachi Ltd | |
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US6029187A (en) | 1997-10-28 | 2000-02-22 | Atmel Corporation | Fast regular multiplier architecture |
US5964827A (en) | 1997-11-17 | 1999-10-12 | International Business Machines Corporation | High-speed binary adder |
US6173414B1 (en) | 1998-05-12 | 2001-01-09 | Mcdonnell Douglas Corporation | Systems and methods for reduced error detection latency using encoded data |
US6175852B1 (en) | 1998-07-13 | 2001-01-16 | International Business Machines Corporation | High-speed binary adder |
EP0992882A3 (en) * | 1998-10-06 | 2003-03-05 | Texas Instruments Inc. | Bit field processor |
US6269386B1 (en) | 1998-10-14 | 2001-07-31 | Intel Corporation | 3X adder |
US6490608B1 (en) | 1999-12-09 | 2002-12-03 | Synopsys, Inc. | Fast parallel multiplier implemented with improved tree reduction schemes |
CN1468396A (en) | 2000-08-04 | 2004-01-14 | 自动平行设计公司 | A parallel counter and a logic circuit for performing multiplication |
US7136888B2 (en) | 2000-08-04 | 2006-11-14 | Arithmatica Limited | Parallel counter and a logic circuit for performing multiplication |
US6883011B2 (en) | 2000-08-04 | 2005-04-19 | Arithmatica Limited | Parallel counter and a multiplication logic circuit |
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US7260595B2 (en) | 2002-12-23 | 2007-08-21 | Arithmatica Limited | Logic circuit and method for carry and sum generation and method of designing such a logic circuit |
-
2004
- 2004-01-14 WO PCT/GB2004/000135 patent/WO2004064254A2/en active Application Filing
- 2004-01-14 GB GB0400799A patent/GB2398944B/en not_active Expired - Fee Related
- 2004-01-14 US US10/757,712 patent/US6909767B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3711692A (en) * | 1971-03-15 | 1973-01-16 | Goodyear Aerospace Corp | Determination of number of ones in a data field by addition |
US5995029A (en) * | 1996-11-06 | 1999-11-30 | Hyundai Electronics Industries Co., Ltd. | Parallel bit counter using bit sorters |
US6470443B1 (en) * | 1996-12-31 | 2002-10-22 | Compaq Computer Corporation | Pipelined multi-thread processor selecting thread instruction in inter-stage buffer based on count information |
US6430251B1 (en) * | 2000-10-24 | 2002-08-06 | Sun Microsystems, Inc. | 4-Bit population count circuit |
Non-Patent Citations (1)
Title |
---|
U. TIETZE, C. SCHENK: "Halbleiterschaltungstechnik", 1993, SPRINGER VERLAG, 10. AUFLAGE BERLIN, XP002284919, 561846 * |
Also Published As
Publication number | Publication date |
---|---|
GB2398944A (en) | 2004-09-01 |
WO2004064254A2 (en) | 2004-07-29 |
GB2398944B (en) | 2005-07-20 |
US6909767B2 (en) | 2005-06-21 |
US20040201411A1 (en) | 2004-10-14 |
GB0400799D0 (en) | 2004-02-18 |
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