WO2004063929A3 - Memory interleaving - Google Patents

Memory interleaving Download PDF

Info

Publication number
WO2004063929A3
WO2004063929A3 PCT/US2004/000084 US2004000084W WO2004063929A3 WO 2004063929 A3 WO2004063929 A3 WO 2004063929A3 US 2004000084 W US2004000084 W US 2004000084W WO 2004063929 A3 WO2004063929 A3 WO 2004063929A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory interleaving
interleaving
memory
channels
power
Prior art date
Application number
PCT/US2004/000084
Other languages
French (fr)
Other versions
WO2004063929A2 (en
Inventor
Gilbert Wolrich
Mark Rosenbluth
Matthew Adiletta
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to EP04700076A priority Critical patent/EP1627309A2/en
Publication of WO2004063929A2 publication Critical patent/WO2004063929A2/en
Publication of WO2004063929A3 publication Critical patent/WO2004063929A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication

Abstract

Memory interleaving includes providing a non-power of two number of channels in a computing system and interleaving memory access among the channels.
PCT/US2004/000084 2003-01-10 2004-01-02 Memory interleaving WO2004063929A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP04700076A EP1627309A2 (en) 2003-01-10 2004-01-02 Memory interleaving

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/340,220 US6941438B2 (en) 2003-01-10 2003-01-10 Memory interleaving
US10/340,220 2003-01-10

Publications (2)

Publication Number Publication Date
WO2004063929A2 WO2004063929A2 (en) 2004-07-29
WO2004063929A3 true WO2004063929A3 (en) 2006-03-23

Family

ID=32711272

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/000084 WO2004063929A2 (en) 2003-01-10 2004-01-02 Memory interleaving

Country Status (6)

Country Link
US (2) US6941438B2 (en)
EP (1) EP1627309A2 (en)
KR (1) KR20050099967A (en)
CN (2) CN100380344C (en)
TW (1) TWI269162B (en)
WO (1) WO2004063929A2 (en)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7873837B1 (en) 2000-01-06 2011-01-18 Super Talent Electronics, Inc. Data security for electronic data flash card
US7702831B2 (en) * 2000-01-06 2010-04-20 Super Talent Electronics, Inc. Flash memory controller for electronic data flash card
US7676640B2 (en) * 2000-01-06 2010-03-09 Super Talent Electronics, Inc. Flash memory controller controlling various flash memory cells
US7702984B1 (en) 2000-01-06 2010-04-20 Super Talent Electronics, Inc. High volume testing for USB electronic data flash cards
US20060075395A1 (en) * 2004-10-01 2006-04-06 Lee Charles C Flash card system
US20060161725A1 (en) * 2005-01-20 2006-07-20 Lee Charles C Multiple function flash memory system
US7487505B2 (en) * 2001-08-27 2009-02-03 Intel Corporation Multithreaded microprocessor with register allocation based on number of active threads
US7225281B2 (en) * 2001-08-27 2007-05-29 Intel Corporation Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
US7216204B2 (en) * 2001-08-27 2007-05-08 Intel Corporation Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US7610451B2 (en) * 2002-01-25 2009-10-27 Intel Corporation Data transfer mechanism using unidirectional pull bus and push bus
US7337275B2 (en) * 2002-08-13 2008-02-26 Intel Corporation Free list and ring data structure management
US6941438B2 (en) * 2003-01-10 2005-09-06 Intel Corporation Memory interleaving
US7418540B2 (en) * 2004-04-28 2008-08-26 Intel Corporation Memory controller with command queue look-ahead
US8190809B2 (en) * 2004-11-23 2012-05-29 Efficient Memory Technology Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines
EP1825433A4 (en) * 2004-11-23 2010-01-06 Efficient Memory Technology Method and apparatus of multiple abbreviations of interleaved addressing of paged memories and intelligent memory banks therefor
US20070157030A1 (en) * 2005-12-30 2007-07-05 Feghali Wajdi K Cryptographic system component
US7793059B2 (en) * 2006-01-18 2010-09-07 Apple Inc. Interleaving policies for flash memory
WO2008009900A1 (en) * 2006-07-17 2008-01-24 Xyratex Technology Limited Methods of powering up a disk drive storage enclosure and storage enclosures
US9710384B2 (en) * 2008-01-04 2017-07-18 Micron Technology, Inc. Microprocessor architecture having alternative memory access paths
US9015399B2 (en) 2007-08-20 2015-04-21 Convey Computer Multiple data channel memory module architecture
US8095735B2 (en) * 2008-08-05 2012-01-10 Convey Computer Memory interleave for heterogeneous computing
US8649609B1 (en) 2011-03-24 2014-02-11 The United States Of America As Represented By The Adminstrator Of The National Aeronautics And Space Administration Field programmable gate array apparatus, method, and computer program
US9009441B2 (en) 2012-06-04 2015-04-14 Qualcomm Incorporated Memory channel selection in a multi-channel memory
US10430190B2 (en) 2012-06-07 2019-10-01 Micron Technology, Inc. Systems and methods for selectively controlling multithreaded execution of executable code segments
US9299124B2 (en) 2012-06-07 2016-03-29 Qualcomm Incorporated Padding for multi-channel memory
US9256531B2 (en) 2012-06-19 2016-02-09 Samsung Electronics Co., Ltd. Memory system and SoC including linear addresss remapping logic
US20140310503A1 (en) * 2013-04-12 2014-10-16 Texas Instruments Incorporated Memory interleaving on memory channels
US9495291B2 (en) 2013-09-27 2016-11-15 Qualcomm Incorporated Configurable spreading function for memory interleaving
KR102161448B1 (en) * 2014-02-03 2020-10-05 삼성전자 주식회사 System comprising multi channel memory and operating method for the same
CN105446911B (en) * 2014-05-29 2018-05-25 展讯通信（上海）有限公司 The memory access control method and device of terminal device
CN105446891B (en) * 2014-05-29 2018-08-21 展讯通信（上海）有限公司 The memory access control method and device of terminal device
KR102398611B1 (en) * 2015-05-07 2022-05-17 에스케이하이닉스 주식회사 Memory system
US9823984B2 (en) * 2015-06-25 2017-11-21 Intel Corporation Remapping of memory in memory control architectures
KR20180007374A (en) * 2016-07-12 2018-01-23 삼성전자주식회사 Electronic device performing software training on memory channel and memory channel training method thereof
US10642733B1 (en) * 2018-07-12 2020-05-05 Lightbits Labs Ltd. System and method for memory interface load balancing
US10817420B2 (en) * 2018-10-30 2020-10-27 Arm Limited Apparatus and method to access a memory location
US10642734B1 (en) * 2018-12-03 2020-05-05 Advanced Micro Devices, Inc. Non-power of two memory configuration

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4189767A (en) * 1978-06-05 1980-02-19 Bell Telephone Laboratories, Incorporated Accessing arrangement for interleaved modular memories
US4833657A (en) * 1985-10-30 1989-05-23 Kabushiki Kaisha Toshiba Semiconductor frame buffer memory
EP1191445A2 (en) * 2000-09-20 2002-03-27 Broadcom Corporation Memory controller with programmable configuration

Family Cites Families (164)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3373408A (en) 1965-04-16 1968-03-12 Rca Corp Computer capable of switching between programs without storage and retrieval of the contents of operation registers
US3478322A (en) 1967-05-23 1969-11-11 Ibm Data processor employing electronically changeable control storage
BE795789A (en) 1972-03-08 1973-06-18 Burroughs Corp MICROPROGRAM CONTAINING A MICRO-RECOVERY INSTRUCTION
US3881173A (en) 1973-05-14 1975-04-29 Amdahl Corp Condition code determination and data processing
IT986411B (en) 1973-06-05 1975-01-30 Olivetti E C Spa SYSTEM TO TRANSFER THE CONTROL OF PROCESSING FROM A FIRST PRIORITY LEVEL TO A SECOND PRIORITY LEVEL
FR2253415A5 (en) 1973-12-04 1975-06-27 Cii
US3913074A (en) 1973-12-18 1975-10-14 Honeywell Inf Systems Search processing apparatus
US4045782A (en) 1976-03-29 1977-08-30 The Warner & Swasey Company Microprogrammed processor system having external memory
US4130890A (en) 1977-06-08 1978-12-19 Itt Industries, Inc. Integrated DDC memory with bitwise erase
US4392758A (en) 1978-05-22 1983-07-12 International Business Machines Corporation Underscore erase
JPS56164464A (en) 1980-05-21 1981-12-17 Tatsuo Nogi Parallel processing computer
US4400770A (en) 1980-11-10 1983-08-23 International Business Machines Corporation Cache synonym detection and handling means
CA1179069A (en) 1981-04-10 1984-12-04 Yasushi Fukunaga Data transmission apparatus for a multiprocessor system
US4569016A (en) 1983-06-30 1986-02-04 International Business Machines Corporation Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system
US4868735A (en) 1984-05-08 1989-09-19 Advanced Micro Devices, Inc. Interruptible structured microprogrammed sixteen-bit address sequence controller
US4742451A (en) 1984-05-21 1988-05-03 Digital Equipment Corporation Instruction prefetch system for conditional branch instruction for central processor unit
US4777587A (en) 1985-08-30 1988-10-11 Advanced Micro Devices, Inc. System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses
US5021945A (en) 1985-10-31 1991-06-04 Mcc Development, Ltd. Parallel processor system for processing natural concurrencies and method therefor
US4745544A (en) 1985-12-12 1988-05-17 Texas Instruments Incorporated Master/slave sequencing processor with forced I/O
US4724521A (en) 1986-01-14 1988-02-09 Veri-Fone, Inc. Method for operating a local terminal to execute a downloaded application program
US5297260A (en) 1986-03-12 1994-03-22 Hitachi, Ltd. Processor having a plurality of CPUS with one CPU being normally connected to common bus
US4992934A (en) 1986-12-15 1991-02-12 United Technologies Corporation Reduced instruction set computing apparatus and methods
US5073864A (en) 1987-02-10 1991-12-17 Davin Computer Corporation Parallel string processor and method for a minicomputer
US5142683A (en) 1987-03-09 1992-08-25 Unisys Corporation Intercomputer communication control apparatus and method
US4866664A (en) 1987-03-09 1989-09-12 Unisys Corporation Intercomputer communication control apparatus & method
WO1989008883A1 (en) 1988-03-14 1989-09-21 Unisys Corporation Record lock processor for multiprocessing data system
US5008808A (en) 1988-06-23 1991-04-16 Storage Technology Corporation Consolidation of commands in a buffered input/output device
US5165025A (en) 1988-10-06 1992-11-17 Lass Stanley E Interlacing the paths after a conditional branch like instruction
US5142676A (en) 1988-12-28 1992-08-25 Gte Laboratories Incorporated Separate content addressable memories for storing locked segment addresses and locking processor identifications for controlling access to shared memory
US5155854A (en) 1989-02-03 1992-10-13 Digital Equipment Corporation System for arbitrating communication requests using multi-pass control unit based on availability of system resources
US5155831A (en) 1989-04-24 1992-10-13 International Business Machines Corporation Data processing system with fast queue store interposed between store-through caches and a main memory
US5166872A (en) 1989-07-17 1992-11-24 Ability Technologies Corporation System and method for controlling devices through communication processors and pluralities of address-associated device controllers sharing each communication processor
US5113516A (en) 1989-07-31 1992-05-12 North American Philips Corporation Data repacker having controlled feedback shifters and registers for changing data format
US5168555A (en) 1989-09-06 1992-12-01 Unisys Corporation Initial program load control
US5263169A (en) 1989-11-03 1993-11-16 Zoran Corporation Bus arbitration and resource management for concurrent vector signal processor architecture
DE3942977A1 (en) 1989-12-23 1991-06-27 Standard Elektrik Lorenz Ag METHOD FOR RESTORING THE CORRECT SEQUENCE OF CELLS, ESPECIALLY IN AN ATM SWITCHING CENTER, AND OUTPUT UNIT THEREFOR
US5247671A (en) 1990-02-14 1993-09-21 International Business Machines Corporation Scalable schedules for serial communications controller in data processing systems
DE69132495T2 (en) 1990-03-16 2001-06-13 Texas Instruments Inc Distributed processing memory
JPH0799812B2 (en) 1990-03-26 1995-10-25 株式会社グラフイックス・コミュニケーション・テクノロジーズ Signal coding apparatus, signal decoding apparatus, and signal coding / decoding apparatus
EP0449369B1 (en) 1990-03-27 1998-07-29 Koninklijke Philips Electronics N.V. A data processing system provided with a performance enhancing instruction cache
US5390329A (en) 1990-06-11 1995-02-14 Cray Research, Inc. Responding to service requests using minimal system-side context in a multiprocessor environment
US5432918A (en) 1990-06-29 1995-07-11 Digital Equipment Corporation Method and apparatus for ordering read and write operations using conflict bits in a write queue
US5404482A (en) 1990-06-29 1995-04-04 Digital Equipment Corporation Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills
US5347648A (en) 1990-06-29 1994-09-13 Digital Equipment Corporation Ensuring write ordering under writeback cache error conditions
AU630299B2 (en) 1990-07-10 1992-10-22 Fujitsu Limited A data gathering/scattering system in a parallel computer
US5367678A (en) 1990-12-06 1994-11-22 The Regents Of The University Of California Multiprocessor system having statically determining resource allocation schedule at compile time and the using of static schedule with processor signals to control the execution time dynamically
EP0522513A2 (en) 1991-07-09 1993-01-13 Hughes Aircraft Company High speed parallel microcode program controller
US5255239A (en) 1991-08-13 1993-10-19 Cypress Semiconductor Corporation Bidirectional first-in-first-out memory device with transparent and user-testable capabilities
US5623489A (en) 1991-09-26 1997-04-22 Ipc Information Systems, Inc. Channel allocation system for distributed digital switching network
US5392412A (en) 1991-10-03 1995-02-21 Standard Microsystems Corporation Data communication controller for use with a single-port data packet buffer
GB2260429B (en) 1991-10-11 1995-05-24 Intel Corp Versatile cache memory
US5392391A (en) 1991-10-18 1995-02-21 Lsi Logic Corporation High performance graphics applications controller
US5557766A (en) 1991-10-21 1996-09-17 Kabushiki Kaisha Toshiba High-speed processor for handling multiple interrupts utilizing an exclusive-use bus and current and previous bank pointers to specify a return bank
US5452437A (en) 1991-11-18 1995-09-19 Motorola, Inc. Methods of debugging multiprocessor system
US5357617A (en) 1991-11-22 1994-10-18 International Business Machines Corporation Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor
US5442797A (en) 1991-12-04 1995-08-15 Casavant; Thomas L. Latency tolerant risc-based multiple processor with event driven locality managers resulting from variable tagging
US5386532A (en) * 1991-12-30 1995-01-31 Sun Microsystems, Inc. Method and apparatus for transferring data between a memory and a plurality of peripheral units through a plurality of data channels
JP2823767B2 (en) 1992-02-03 1998-11-11 松下電器産業株式会社 Register file
US5448706A (en) * 1992-05-13 1995-09-05 Sharp Microelectronics Technology, Inc. Address generator for multi-channel circular-buffer style processing
US5459842A (en) 1992-06-26 1995-10-17 International Business Machines Corporation System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory
DE4223600C2 (en) 1992-07-17 1994-10-13 Ibm Multiprocessor computer system and method for transmitting control information and data information between at least two processor units of a computer system
US5274770A (en) 1992-07-29 1993-12-28 Tritech Microelectronics International Pte Ltd. Flexible register-based I/O microcontroller with single cycle instruction execution
US5692167A (en) 1992-07-31 1997-11-25 Intel Corporation Method for verifying the correct processing of pipelined instructions including branch instructions and self-modifying code in a microprocessor
US5442756A (en) 1992-07-31 1995-08-15 Intel Corporation Branch prediction and resolution apparatus for a superscalar computer processor
US5649109A (en) 1992-10-22 1997-07-15 Digital Equipment Corporation Apparatus and method for maintaining forwarding information in a bridge or router using multiple free queues having associated free space sizes
US5481683A (en) 1992-10-30 1996-01-02 International Business Machines Corporation Super scalar computer architecture using remand and recycled general purpose register to manage out-of-order execution of instructions
US5450603A (en) 1992-12-18 1995-09-12 Xerox Corporation SIMD architecture with transfer register or value source circuitry connected to bus
ATE188559T1 (en) 1992-12-23 2000-01-15 Centre Electron Horloger MULTI-TASKING CONTROL DEVICE WITH LOW ENERGY CONSUMPTION
US5404464A (en) 1993-02-11 1995-04-04 Ast Research, Inc. Bus control system and method that selectively generate an early address strobe
US5448702A (en) 1993-03-02 1995-09-05 International Business Machines Corporation Adapters with descriptor queue management capability
US5522069A (en) 1993-04-30 1996-05-28 Zenith Data Systems Corporation Symmetric multiprocessing system with unified environment and distributed system functions
WO1994027216A1 (en) 1993-05-14 1994-11-24 Massachusetts Institute Of Technology Multiprocessor coupling system with integrated compile and run time scheduling for parallelism
CA2122182A1 (en) 1993-05-20 1994-11-21 Rene Leblanc Method for rapid prototyping of programming problems
US5363448A (en) 1993-06-30 1994-11-08 United Technologies Automotive, Inc. Pseudorandom number generation and cryptographic authentication
CA2107299C (en) 1993-09-29 1997-02-25 Mehrad Yasrebi High performance machine for switched communications in a heterogenous data processing network gateway
US5446736A (en) 1993-10-07 1995-08-29 Ast Research, Inc. Method and apparatus for connecting a node to a wireless network using a standard protocol
US5450351A (en) 1993-11-19 1995-09-12 International Business Machines Corporation Content addressable memory implementation with random access memory
US5487159A (en) 1993-12-23 1996-01-23 Unisys Corporation System for processing shift, mask, and merge operations in one instruction
US5490204A (en) 1994-03-01 1996-02-06 Safco Corporation Automated quality assessment system for cellular networks
US5835755A (en) 1994-04-04 1998-11-10 At&T Global Information Solutions Company Multi-processor computer system for operating parallel client/server database processes
JP3547482B2 (en) 1994-04-15 2004-07-28 株式会社日立製作所 Information processing equipment
US5659722A (en) 1994-04-28 1997-08-19 International Business Machines Corporation Multiple condition code branching system in a multi-processor environment
US5542088A (en) 1994-04-29 1996-07-30 Intergraph Corporation Method and apparatus for enabling control of task execution
US5721870A (en) 1994-05-25 1998-02-24 Nec Corporation Lock control for a shared main storage data processing system
US5544236A (en) 1994-06-10 1996-08-06 At&T Corp. Access to unsubscribed features
US5574922A (en) 1994-06-17 1996-11-12 Apple Computer, Inc. Processor with sequences of processor instructions for locked memory updates
US5781774A (en) 1994-06-29 1998-07-14 Intel Corporation Processor having operating modes for an upgradeable multiprocessor computer system
FR2722041B1 (en) 1994-06-30 1998-01-02 Samsung Electronics Co Ltd HUFFMAN DECODER
JP3810449B2 (en) 1994-07-20 2006-08-16 富士通株式会社 Queue device
US5640538A (en) 1994-08-22 1997-06-17 Adaptec, Inc. Programmable timing mark sequencer for a disk drive
US5717760A (en) 1994-11-09 1998-02-10 Channel One Communications, Inc. Message protection system and method
JP3169779B2 (en) 1994-12-19 2001-05-28 日本電気株式会社 Multi-thread processor
US5610864A (en) 1994-12-23 1997-03-11 Micron Technology, Inc. Burst EDO memory device with maximized write cycle timing
US5550816A (en) 1994-12-29 1996-08-27 Storage Technology Corporation Method and apparatus for virtual switching
US5784712A (en) 1995-03-01 1998-07-21 Unisys Corporation Method and apparatus for locally generating addressing information for a memory access
US5649157A (en) 1995-03-30 1997-07-15 Hewlett-Packard Co. Memory controller with priority queues
TW360852B (en) 1995-04-12 1999-06-11 Matsushita Electric Ind Co Ltd Pipeline processor
US5886992A (en) 1995-04-14 1999-03-23 Valtion Teknillinen Tutkimuskeskus Frame synchronized ring system and method
US5592622A (en) 1995-05-10 1997-01-07 3Com Corporation Network intermediate system with message passing architecture
JPH08320797A (en) 1995-05-24 1996-12-03 Fuji Xerox Co Ltd Program control system
US5828746A (en) 1995-06-07 1998-10-27 Lucent Technologies Inc. Telecommunications network
US5828863A (en) 1995-06-09 1998-10-27 Canon Information Systems, Inc. Interface device connected between a LAN and a printer for outputting formatted debug information about the printer to the printer
US5541920A (en) 1995-06-15 1996-07-30 Bay Networks, Inc. Method and apparatus for a delayed replace mechanism for a streaming packet modification engine
KR0180169B1 (en) 1995-06-30 1999-05-01 배순훈 A variable length coder
US5613071A (en) 1995-07-14 1997-03-18 Intel Corporation Method and apparatus for providing remote memory access in a distributed memory multiprocessor system
US5680641A (en) 1995-08-16 1997-10-21 Sharp Microelectronics Technology, Inc. Multiple register bank system for concurrent I/O operation in a CPU datapath
US5940612A (en) 1995-09-27 1999-08-17 International Business Machines Corporation System and method for queuing of tasks in a multiprocessing system
US5689566A (en) 1995-10-24 1997-11-18 Nguyen; Minhtam C. Network with secure communications sessions
US5809530A (en) 1995-11-13 1998-09-15 Motorola, Inc. Method and apparatus for processing multiple cache misses using reload folding and store merging
KR0150072B1 (en) 1995-11-30 1998-10-15 양승택 Device for controlling memory data path in parallel processing computer system
US5796413A (en) 1995-12-06 1998-08-18 Compaq Computer Corporation Graphics controller utilizing video memory to provide macro command capability and enhanched command buffering
US5940866A (en) 1995-12-13 1999-08-17 International Business Machines Corporation Information handling system having a local address queue for local storage of command blocks transferred from a host processing side
US5699537A (en) 1995-12-22 1997-12-16 Intel Corporation Processor microarchitecture for efficient dynamic scheduling and execution of chains of dependent instructions
US5790813A (en) 1996-01-05 1998-08-04 Unisys Corporation Pre-arbitration system allowing look-around and bypass for significant operations
US6088783A (en) * 1996-02-16 2000-07-11 Morton; Steven G DPS having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word
US5761507A (en) 1996-03-05 1998-06-02 International Business Machines Corporation Client/server architecture supporting concurrent servers within a server with a transaction manager providing server/connection decoupling
US5809235A (en) 1996-03-08 1998-09-15 International Business Machines Corporation Object oriented network event management framework
US5797043A (en) 1996-03-13 1998-08-18 Diamond Multimedia Systems, Inc. System for managing the transfer of data between FIFOs within pool memory and peripherals being programmable with identifications of the FIFOs
US5784649A (en) 1996-03-13 1998-07-21 Diamond Multimedia Systems, Inc. Multi-threaded FIFO pool buffer and bus transfer control system
KR100219597B1 (en) 1996-03-30 1999-09-01 윤종용 Queuing control method in cd-rom drive
US5946487A (en) 1996-06-10 1999-08-31 Lsi Logic Corporation Object-oriented multi-media architecture
KR980004067A (en) 1996-06-25 1998-03-30 김광호 Data Transceiver and Method in Multiprocessor System
JP3541335B2 (en) 1996-06-28 2004-07-07 富士通株式会社 Information processing apparatus and distributed processing control method
US5937187A (en) 1996-07-01 1999-08-10 Sun Microsystems, Inc. Method and apparatus for execution and preemption control of computer process entities
US6023742A (en) 1996-07-18 2000-02-08 University Of Washington Reconfigurable computing architecture for providing pipelined data paths
US5745913A (en) 1996-08-05 1998-04-28 Exponential Technology, Inc. Multi-processor DRAM controller that prioritizes row-miss requests to stale banks
US6058465A (en) 1996-08-19 2000-05-02 Nguyen; Le Trong Single-instruction-multiple-data processing in a multimedia signal processor
US5812868A (en) 1996-09-16 1998-09-22 Motorola Inc. Method and apparatus for selecting a register file in a data processing system
US5860158A (en) 1996-11-15 1999-01-12 Samsung Electronics Company, Ltd. Cache control unit with a cache request transaction-oriented protocol
US5905876A (en) 1996-12-16 1999-05-18 Intel Corporation Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system
US5854922A (en) 1997-01-16 1998-12-29 Ford Motor Company Micro-sequencer apparatus and method of combination state machine and instruction memory
US5961628A (en) 1997-01-28 1999-10-05 Samsung Electronics Co., Ltd. Load and store unit for a vector processor
US5742587A (en) 1997-02-28 1998-04-21 Lanart Corporation Load balancing port switching hub
US5905889A (en) 1997-03-20 1999-05-18 International Business Machines Corporation Resource management system using next available integer from an integer pool and returning the integer thereto as the next available integer upon completion of use
US6381668B1 (en) * 1997-03-21 2002-04-30 International Business Machines Corporation Address mapping for system memory
US5983274A (en) 1997-05-08 1999-11-09 Microsoft Corporation Creation and use of control information associated with packetized network data by protocol drivers and device drivers
US5938736A (en) 1997-06-30 1999-08-17 Sun Microsystems, Inc. Search engine architecture for a high performance multi-layer switch element
US5887134A (en) 1997-06-30 1999-03-23 Sun Microsystems System and method for preserving message order while employing both programmed I/O and DMA operations
US6014729A (en) 1997-09-29 2000-01-11 Firstpass, Inc. Shared memory arbitration apparatus and method
US5915123A (en) 1997-10-31 1999-06-22 Silicon Spice Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements
TW406229B (en) * 1997-11-06 2000-09-21 Hitachi Ltd Data process system and microcomputer
US5948081A (en) 1997-12-22 1999-09-07 Compaq Computer Corporation System for flushing queued memory write request corresponding to a queued read request and all prior write requests with counter indicating requests to be flushed
US5970013A (en) 1998-02-26 1999-10-19 Lucent Technologies Inc. Adaptive addressable circuit redundancy method and apparatus with broadcast write
US6408325B1 (en) * 1998-05-06 2002-06-18 Sun Microsystems, Inc. Context switching technique for processors with large register files
US6505281B1 (en) * 1998-06-02 2003-01-07 Raymond C. Sherry Hard disk drives employing high speed distribution bus
TW374967B (en) * 1998-06-22 1999-11-21 Winbond Electronics Corp Ethernet switch having shared memory structure and method of the shared memory
US6424659B2 (en) * 1998-07-17 2002-07-23 Network Equipment Technologies, Inc. Multi-layer switching apparatus and method
US6356962B1 (en) * 1998-09-30 2002-03-12 Stmicroelectronics, Inc. Network device and method of controlling flow of data arranged in frames in a data-based network
US6212604B1 (en) * 1998-12-03 2001-04-03 Sun Microsystems, Inc. Shared instruction cache for multiple processors
SE9804529L (en) * 1998-12-23 2000-06-24 Axis Ab Flexible memory channel
CA2266283C (en) * 1999-03-19 2006-07-11 Wen Tong Data interleaver and method of interleaving data
US6570877B1 (en) * 1999-04-07 2003-05-27 Cisco Technology, Inc. Search engine for forwarding table content addressable memory
JP3546788B2 (en) * 1999-12-20 2004-07-28 日本電気株式会社 Memory control circuit
US6480943B1 (en) * 2000-04-29 2002-11-12 Hewlett-Packard Company Memory address interleaving and offset bits for cell interleaving of memory
US6513089B1 (en) * 2000-05-18 2003-01-28 International Business Machines Corporation Dual burst latency timers for overlapped read and write data transfers
US6826180B1 (en) * 2000-06-14 2004-11-30 Mindspeed Technologies, Inc. Communication packet processor with a look-up engine and content-addressable memory for storing summation blocks of context information for a core processor
JP3489573B2 (en) * 2001-07-11 2004-01-19 日本電気株式会社 Packet processing device
US7225281B2 (en) * 2001-08-27 2007-05-29 Intel Corporation Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
US7216204B2 (en) * 2001-08-27 2007-05-08 Intel Corporation Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US6868476B2 (en) * 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US6934729B2 (en) * 2001-10-18 2005-08-23 International Business Machines Corporation Method and system for performing shift operations
US7028118B2 (en) * 2001-12-12 2006-04-11 Texas Instruments Incorporated Multi-channel buffered serial port debugging
US7089379B1 (en) * 2002-06-28 2006-08-08 Emc Corporation Large high bandwidth memory system
US6941438B2 (en) * 2003-01-10 2005-09-06 Intel Corporation Memory interleaving

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4189767A (en) * 1978-06-05 1980-02-19 Bell Telephone Laboratories, Incorporated Accessing arrangement for interleaved modular memories
US4833657A (en) * 1985-10-30 1989-05-23 Kabushiki Kaisha Toshiba Semiconductor frame buffer memory
EP1191445A2 (en) * 2000-09-20 2002-03-27 Broadcom Corporation Memory controller with programmable configuration

Also Published As

Publication number Publication date
CN101042677A (en) 2007-09-26
TW200422828A (en) 2004-11-01
CN1517880A (en) 2004-08-04
WO2004063929A2 (en) 2004-07-29
EP1627309A2 (en) 2006-02-22
CN100380344C (en) 2008-04-09
US20050185437A1 (en) 2005-08-25
US7418571B2 (en) 2008-08-26
US20040139290A1 (en) 2004-07-15
US6941438B2 (en) 2005-09-06
TWI269162B (en) 2006-12-21
KR20050099967A (en) 2005-10-17

Similar Documents

Publication Publication Date Title
WO2004063929A3 (en) Memory interleaving
AU2003241617A1 (en) Memory and access devices
AU2003243543A1 (en) Layered computing systems and methods
AU2003223386A1 (en) Low-power high-performance memory cell and related methods
AU2003279039A1 (en) Data storage card having both linear and annular data regions
AUPR454001A0 (en) Interactive learning and career management system
AU2003291334A1 (en) Hardware simulation with access restrictions
AU2003228869A1 (en) Transporters and ion channels
AU2003290767A1 (en) Attestation using both fixed token and portable token
AU2003301943A1 (en) Interleaved mirrored memory systems
AU2003233541A1 (en) Modular monitoring and protection system with distributed voting logic
AU2003277406A1 (en) Fuel storage devices and apparatus including the same
AU2003285116A1 (en) Stored value currency conversion systems and methods
EP1511542A4 (en) Computer learning memory game and system
AU2003294246A1 (en) Circulating stem cells and uses related thereto
WO2002071246A3 (en) An apparatus for controlling access in a data processor
AU2003207469A1 (en) Dynamic fuel processor mechanization and control
AU2003278770A1 (en) Electrochemical cells and systems
AU2003249434A1 (en) Dynamic memory management
AU2003214783A1 (en) Multi-stage per cell magnetoresistive random access memory
AU2003241048A1 (en) Fuel cell operating cycles and systems
AU2003295260A1 (en) Memory management in a computer system using different swapping criteria
GB2442411A (en) Interleaved virtual local memory for a graphics processor
AU2003273524A1 (en) Direct memory access circuit with atm support
AU2003294921A1 (en) Memory architecture with series grouped memory cells

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1020057012816

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 2004700076

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1020057012816

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 2004700076

Country of ref document: EP