WO2004061960A3 - Semiconductor device power interconnect striping - Google Patents

Semiconductor device power interconnect striping Download PDF

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Publication number
WO2004061960A3
WO2004061960A3 PCT/US2003/039194 US0339194W WO2004061960A3 WO 2004061960 A3 WO2004061960 A3 WO 2004061960A3 US 0339194 W US0339194 W US 0339194W WO 2004061960 A3 WO2004061960 A3 WO 2004061960A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
striping
device power
power interconnect
power
Prior art date
Application number
PCT/US2003/039194
Other languages
French (fr)
Other versions
WO2004061960A2 (en
Inventor
Edward Osburn
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to EP03799882A priority Critical patent/EP1579503A2/en
Priority to CN200380107878.5A priority patent/CN1732567B/en
Priority to AU2003299597A priority patent/AU2003299597A1/en
Publication of WO2004061960A2 publication Critical patent/WO2004061960A2/en
Publication of WO2004061960A3 publication Critical patent/WO2004061960A3/en

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0254High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H05K1/0262Arrangements for regulating voltages or for using plural voltages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231Capacitors or dielectric substances
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • H05K1/112Pads for surface mounting, e.g. lay-out directly combined with via connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0263High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/0929Conductive planes
    • H05K2201/093Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007Types of components
    • H05K2201/1003Non-printed inductor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10507Involving several components
    • H05K2201/10515Stacked components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10507Involving several components
    • H05K2201/10545Related components mounted on both sides of the PCB
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10704Pin grid array [PGA]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/429Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Abstract

A method and an apparatus for improving the delivery and filtering of power to a semiconductor device is disclosed by organizing out interconnects (pins, balls, pads or other interconnects) used to carry power in a striped configuration that shortens the conductive path required between a power source and a semiconductor device and that reduces the resistance of that conductive path.
PCT/US2003/039194 2002-12-30 2003-12-08 Semiconductor device power interconnect striping WO2004061960A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP03799882A EP1579503A2 (en) 2002-12-30 2003-12-08 Semiconductor device power interconnect striping
CN200380107878.5A CN1732567B (en) 2002-12-30 2003-12-08 Semiconductor device power interconnect striping
AU2003299597A AU2003299597A1 (en) 2002-12-30 2003-12-08 Semiconductor device power interconnect striping

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/335,368 2002-12-30
US10/335,368 US7005736B2 (en) 2002-09-30 2002-12-30 Semiconductor device power interconnect striping

Publications (2)

Publication Number Publication Date
WO2004061960A2 WO2004061960A2 (en) 2004-07-22
WO2004061960A3 true WO2004061960A3 (en) 2005-01-27

Family

ID=32710908

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/039194 WO2004061960A2 (en) 2002-12-30 2003-12-08 Semiconductor device power interconnect striping

Country Status (6)

Country Link
US (3) US7005736B2 (en)
EP (1) EP1579503A2 (en)
CN (1) CN1732567B (en)
AU (1) AU2003299597A1 (en)
TW (1) TWI253734B (en)
WO (1) WO2004061960A2 (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6916995B2 (en) * 2003-02-25 2005-07-12 Broadcom Corporation Optimization of routing layers and board space requirements for ball grid array package implementations including single and multi-layer routing
US7145782B2 (en) 2004-07-16 2006-12-05 Intel Corporation Reducing loadline impedance in a system
US20080079135A1 (en) * 2006-09-29 2008-04-03 Jitesh Shah Package assembly pinout with superior crosstalk and timing performance
US7847404B1 (en) * 2007-03-29 2010-12-07 Integrated Device Technology, Inc. Circuit board assembly and packaged integrated circuit device with power and ground channels
US8120162B2 (en) * 2007-09-28 2012-02-21 Integrated Device Technology, Inc. Package with improved connection of a decoupling capacitor
US20090160475A1 (en) * 2007-12-20 2009-06-25 Anwar Ali Test pin reduction using package center ball grid array
US8350375B2 (en) * 2008-05-15 2013-01-08 Lsi Logic Corporation Flipchip bump patterns for efficient I-mesh power distribution schemes
TWI373653B (en) * 2008-09-01 2012-10-01 Au Optronics Corp Conducting layer jump connection structure
US9332629B2 (en) 2010-11-02 2016-05-03 Integrated Device Technology, Inc. Flip chip bump array with superior signal performance
EP2808890A4 (en) * 2012-01-27 2015-08-19 Panasonic Corp Multilayer printed board
US9345137B2 (en) 2013-11-04 2016-05-17 Lattice Semiconductor Corporation Partially depopulated interconnection arrays for packaged semiconductor devices and printed circuit boards
US9769926B2 (en) * 2015-04-23 2017-09-19 Dell Products L.P. Breakout via system
EP3312878A4 (en) * 2015-08-31 2018-11-14 Aisin Aw Co., Ltd. Semiconductor device, chip module, and semiconductor module
US10916494B2 (en) * 2019-01-02 2021-02-09 Qualcomm Incorporated Device comprising first solder interconnects aligned in a first direction and second solder interconnects aligned in a second direction
US11508683B2 (en) * 2019-06-17 2022-11-22 Western Digital Technologies, Inc. Semiconductor device with die bumps aligned with substrate balls
US11817378B2 (en) * 2020-07-08 2023-11-14 Qualcomm Incorporated Apparatus and method for providing a scalable ball grid array (BGA) assignment and a PCB circuit trace breakout pattern for RF chip interfaces

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1098555A2 (en) * 1999-11-02 2001-05-09 Canon Kabushiki Kaisha Printed-wiring board
US6232564B1 (en) * 1998-10-09 2001-05-15 International Business Machines Corporation Printed wiring board wireability enhancement
US20010035746A1 (en) * 2000-02-04 2001-11-01 Volterra Semiconductor, Delaware Corporation Transistor pattern for voltage regulator
US6404649B1 (en) * 2000-03-03 2002-06-11 Advanced Micro Devices, Inc. Printed circuit board assembly with improved bypass decoupling for BGA packages

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5061989A (en) * 1990-03-22 1991-10-29 Transcomputer, Inc. Mechanical translator for semiconductor chips
US5479319A (en) * 1992-12-30 1995-12-26 Interconnect Systems, Inc. Multi-level assemblies for interconnecting integrated circuits
US5796170A (en) * 1996-02-15 1998-08-18 Northern Telecom Limited Ball grid array (BGA) integrated circuit packages
US5859475A (en) * 1996-04-24 1999-01-12 Amkor Technology, Inc. Carrier strip and molded flex circuit ball grid array
JP2000100814A (en) * 1998-09-18 2000-04-07 Hitachi Ltd Semiconductor device
US5994766A (en) * 1998-09-21 1999-11-30 Vlsi Technology, Inc. Flip chip circuit arrangement with redistribution layer that minimizes crosstalk
US6310398B1 (en) * 1998-12-03 2001-10-30 Walter M. Katz Routable high-density interfaces for integrated circuit devices
US6037677A (en) * 1999-05-28 2000-03-14 International Business Machines Corporation Dual-pitch perimeter flip-chip footprint for high integration asics
US6207476B1 (en) * 1999-06-10 2001-03-27 Vlsi Technology, Inc. Methods of packaging an integrated circuit and methods of forming an integrated circuit package
US6448639B1 (en) * 2000-09-18 2002-09-10 Advanced Semiconductor Engineering, Inc. Substrate having specific pad distribution
TW498530B (en) * 2001-08-29 2002-08-11 Via Tech Inc Flip-chip pad and redistribution layer arrangement
US6730860B2 (en) * 2001-09-13 2004-05-04 Intel Corporation Electronic assembly and a method of constructing an electronic assembly

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6232564B1 (en) * 1998-10-09 2001-05-15 International Business Machines Corporation Printed wiring board wireability enhancement
EP1098555A2 (en) * 1999-11-02 2001-05-09 Canon Kabushiki Kaisha Printed-wiring board
US20010035746A1 (en) * 2000-02-04 2001-11-01 Volterra Semiconductor, Delaware Corporation Transistor pattern for voltage regulator
US6404649B1 (en) * 2000-03-03 2002-06-11 Advanced Micro Devices, Inc. Printed circuit board assembly with improved bypass decoupling for BGA packages

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ANONYMOUS: "AMD Athlon TM Processor Model 4 Data Sheet", INTERNET ARTICLE, November 2001 (2001-11-01), XP002296966, Retrieved from the Internet <URL:HTTP://WWW.AMD.COM/US-EN/ASSETS/CONTENT_TYPE/WHITE> *

Also Published As

Publication number Publication date
US20050248040A1 (en) 2005-11-10
US7005736B2 (en) 2006-02-28
US7319269B2 (en) 2008-01-15
TWI253734B (en) 2006-04-21
US7732260B2 (en) 2010-06-08
CN1732567A (en) 2006-02-08
US20040061242A1 (en) 2004-04-01
CN1732567B (en) 2011-01-26
AU2003299597A8 (en) 2004-07-29
AU2003299597A1 (en) 2004-07-29
US20080064207A1 (en) 2008-03-13
EP1579503A2 (en) 2005-09-28
WO2004061960A2 (en) 2004-07-22
TW200419761A (en) 2004-10-01

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