WO2004061726A1 - Nested design approach - Google Patents

Nested design approach Download PDF

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Publication number
WO2004061726A1
WO2004061726A1 PCT/US2002/040671 US0240671W WO2004061726A1 WO 2004061726 A1 WO2004061726 A1 WO 2004061726A1 US 0240671 W US0240671 W US 0240671W WO 2004061726 A1 WO2004061726 A1 WO 2004061726A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
master
subset
netlist
master substrate
Prior art date
Application number
PCT/US2002/040671
Other languages
French (fr)
Inventor
S. Harsaran Bhatia
S. Marie Cole
S. Michael Cranmer
L. Jason Frankel
Eric Kline
A. Kenneth Papae
R. Paul Walling
Original Assignee
International Business Machines Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corporation filed Critical International Business Machines Corporation
Priority to EP02795945A priority Critical patent/EP1573602A4/en
Priority to CNA02829968XA priority patent/CN1695149A/en
Priority to PCT/US2002/040671 priority patent/WO2004061726A1/en
Priority to AU2002360668A priority patent/AU2002360668A1/en
Priority to JP2004564625A priority patent/JP4700967B2/en
Publication of WO2004061726A1 publication Critical patent/WO2004061726A1/en
Priority to US11/160,307 priority patent/US7325213B2/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2113/00—Details relating to the application field
    • G06F2113/18—Chip packaging
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5382—Adaptable interconnections, e.g. for engineering changes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED

Definitions

  • the present invention generally relates to chip package designs and more
  • the packages protect the chip from environmental degradation and form electrical power and signal connections to the printed circuit board.
  • the chips generally
  • packages that have a master substrate and at least one subset substrate of the master substrate.
  • the subset substrate is a portion of the master substrate and has an identical pin out pattern as
  • the subset substrate has identical internal net lists as that portion of the master substrate.
  • the subset substrate is adapted to accommodate a smaller
  • the master substrate is the largest substrate in the menu.
  • the invention also prepares a menu of chip packages. The invention selects a master substrate
  • the master design represents the largest possible logical netlist and largest
  • netlist is not changed or revised in any way except that programmatic (e.g., from the
  • the invention designs the substrate with the largest
  • the subset netlists can be delivered to the customer much more quickly
  • Figure 1 is a schematic diagram of different ball grid array patterns which
  • FIGS 2A and 2B are schematic diagrams of the BSM assignments of the
  • Figures 3A and 3B are schematic diagrams of the die footprint on the TSM of
  • Figures 4A and 4B are schematic diagrams of the first internal layer wiring of the V2 power level connections for the chip package using the master netlist and a subset
  • Figures 5A and 5B are schematic diagrams of the first internal layer wiring of
  • Figures 6A and 6B are schematic diagrams of the first internal layer wiring of
  • Figures 7A and 7B are schematic diagrams of the first internal layer wiring of
  • Figures 8A and 8B are schematic diagrams of the second internal layer wiring
  • Figures 9A and 9B are schematic diagrams of the second internal layer wiring
  • Figures 10A and 10B are schematic diagrams of the second internal layer
  • FIGs 11 A and 1 IB are schematic diagrams of the third internal layer wiring
  • Figures 12A and 12B are schematic diagrams of the third internal layer wiring
  • Figures 13A and 134B are schematic diagrams of the second internal layer
  • Figures 14A and 14B are schematic diagrams of the BSM array pattern for the
  • the invention reduces the amount of design time and
  • the invention designs the wiring connections of a package to allow that package to be used generically with a wide variety of semiconductor
  • the invention creates a master (or super-substrate) design the of the largest substrate
  • the invention represents
  • the substrate at the bottom surface metallurgy (BSM) pads
  • the substrate is predetermine for a menu of substrates.
  • the pattern of the BSM pads is pre-assigned for all
  • netlists, and the physical topology of the I/O support the logical deletion of unneeded nets for subordinate packages.
  • the outermost I/O at the TSM plane remains the outermost row at the BSM plane (thus, the
  • the master substrate has a size of 42.5 X 42.5 mm.
  • the master substrate has a size of 42.5 X 42.5 mm.
  • Figure 1 illustrates a number of subsets of the master substrate (shown in different scaling)
  • the substrate could comprise ceramic, organic, plastic, semiconductor, etc.
  • Figures 2A and 2B show internal wiring net lists within chip packages
  • substrate shown in Figure 2A is substantially larger and would be useful with a substantially larger chip than the substrate shown in Figure 2B.
  • the package of Figure 2B can be designed
  • a master or super-substrate e.g., largest supportable netlist for the chip
  • Figures 3A-14B represent the various layers within two different substrates
  • the electrical connections and wiring positions are identical for the master and the subset except that the subset does not include the peripheral region 30 that is
  • the master design represents the largest possible logical netlist and largest
  • netlist is not changed or revised in any way except that programmatic (e.g., from the
  • the subset chip package (B) is derived simply by the deletion of wiring on each layer
  • the invention discloses a hierarchical system of congruent logical and
  • topological coherence chip package that has a master substrate and at least one subset substrate of the master substrate.
  • the master substrate has the largest logical and physical
  • the subset substrate is derived by programmatic
  • Congruent chip packages mean that for
  • the invention designs the substrate with the largest
  • the subset netlists can be delivered to the customer much more quickly

Abstract

A structure for a system of chip packages includes a master substrate (2A) and at least one subset substrate (2B) of the master substrate (2A). The subset substrate (2A) includes a portion of the master substrate (2A) that has an identical pin out pattern as the portion of the master substrate (2A). The subset substrate (2B) has identical internal net lists as the portion of the master substrate (2A). The subset substrate (2B) is adapted to accommodate a smaller chip than the master substrate (2A). The master substrate (2A) is the largest substrate in the system. The invention also prepares a system of chip packages. The invention selects a master substrate (2A) and then selects a subset substrate (2B) of the master substrate (2A).

Description

NESTED DESIGN APPROACH
BACKGROUND OF THE INVENTION
Field of the Invention
[0001] The present invention generally relates to chip package designs and more
particularly to an improved design that pre-assigns the contact pad array pattern and
associated net list for a family of chips.
Description of the Related Art
[0002] Semiconductor chips are generally encased in packages that are attached to a
printed circuit board. The packages protect the chip from environmental degradation and form electrical power and signal connections to the printed circuit board. The chips generally
perform different functions some of which are less complex than others. Therefore, the chips
often have different sizes (sometimes relating to their complexity).
[0003] One problem encountered by designers is that each chip package (substrate)
must be uniquely designed for each newly designed chip. This is true for even those chips
that are in the same family (same family corresponding to the same technology node and
device type, and sometimes extending to the same topology and or I/O structure and pinout).
The invention described below overcomes such problems by utilizing pre-assigned pin-out
patterns on the chip packages. SUMMARY OF THE INVENTION
[0004] In view of the foregoing and other problems, disadvantages, and drawbacks of
the conventional chip packages and associated design methodology limitations, the present
invention has been devised, and it is an object of the present invention to provide a structure
and method for an improved chip package and design methodology.
[0005] There is provided, according to one aspect of the invention, a menu of chip
packages that have a master substrate and at least one subset substrate of the master substrate.
The subset substrate is a portion of the master substrate and has an identical pin out pattern as
that portion of the master substrate. The subset substrate has identical internal net lists as that portion of the master substrate. The subset substrate is adapted to accommodate a smaller
chip than the master substrate. The master substrate is the largest substrate in the menu. The invention also prepares a menu of chip packages. The invention selects a master substrate
and then selects a subset substrate of the master substrate.
[0006] The master design represents the largest possible logical netlist and largest
physical wiring possible for the given die and package combination. Further, the logical
netlist is not changed or revised in any way except that programmatic (e.g., from the
outermost I/O proceeding inboard, in series, as required) deletions are allowed. Thus, the
derived subordinate netlist/package is an exact identical subset of the parent master
netlist/package.
[0007] Thus, as explained above, when different sizes of chips from the same family
are placed on multiple substrate sizes, the invention designs the substrate with the largest
body size first. Designs for the smaller body sizes are then subsets of the initial design. The bottom surface pad assignments for each physical location are made common between each
substrate size to enable this sharing of design structures to produce the cost and time savings
associated with the invention.
[0008] Traditionally, each substrate design has been done from scratch, which utilizes
much more design resources, and requires a long cycle time to produce each design or netlist.
With the invention, the subset netlists can be delivered to the customer much more quickly,
by just running through a program to obtain the subset netlist, and the smaller designs can
quickly be obtained, reducing the design cycle time.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The foregoing and other objects, aspects and advantages will be better
understood from the following detailed description of preferred embodiments of the invention with reference to the drawings, in which:
[0010] Figure 1 is a schematic diagram of different ball grid array patterns which
shows how the smaller chip package array patterns are subsets of the array pattern of the
master; and
[0011] Figures 2A and 2B are schematic diagrams of the BSM assignments of the
chip package using the master netlist and the BSM assignments of the chip package using a
subset netlist of the master netlist;
[0012] Figures 3A and 3B are schematic diagrams of the die footprint on the TSM of
the master netlist and a subset netlist of the master netlist;
[0013] Figures 4A and 4B are schematic diagrams of the first internal layer wiring of the V2 power level connections for the chip package using the master netlist and a subset
netlist of the master netlist;
[0014] Figures 5A and 5B are schematic diagrams of the first internal layer wiring of
the ground connections for the chip package using the master netlist and a subset netlist of the
master netlist;
[0015] Figures 6A and 6B are schematic diagrams of the first internal layer wiring of
the VI power level connections for the chip package using the master netlist and a subset
netlist of the master netlist;
[0016] Figures 7A and 7B are schematic diagrams of the first internal layer wiring of
the signal connections for the chip package using the master netlist and a subset netlist of the
master netlist of an intermediate level within a chip package;
[0017] Figures 8A and 8B are schematic diagrams of the second internal layer wiring
of the ground connections for the chip package using the master netlist and a subset netlist of the
master netlist;
[0018] Figures 9A and 9B are schematic diagrams of the second internal layer wiring
of the signal connections for the chip package using the master netlist and a subset netlist of
the master netlist;
[0019] Figures 10A and 10B are schematic diagrams of the second internal layer
wiring of the Nl power level connections for the chip package using the master netlist and a
subset netlist of the master netlist;
[0020] Figures 11 A and 1 IB are schematic diagrams of the third internal layer wiring
of the signal connections for the chip package using the master netlist and a subset netlist of
the master netlist;
[0021] Figures 12A and 12B are schematic diagrams of the third internal layer wiring
of the ground connections for the chip package using the master netlist and a subset netlist of
the master netlist;
[0022] Figures 13A and 134B are schematic diagrams of the second internal layer
wiring of the N2 power level connections for the chip package using the master netlist and a
subset netlist of the master netlist; and
[0023] Figures 14A and 14B are schematic diagrams of the BSM array pattern for the
chip package using the master netlist and a subset netlist of the master netlist.
DETAILED DESCRIPTION OF PREFERRED
EMBODIMENTS OF THE INVENTION
[0024] As mentioned above, the invention reduces the amount of design time and
effort required which allows new products to be brought to the market earlier and reduces the
cost of creating such products. Generally, the invention designs the wiring connections of a package to allow that package to be used generically with a wide variety of semiconductor
chips. The invention creates a master (or super-substrate) design the of the largest substrate
(chip package) that will be included within a menu of substrates. Substrates that are smaller
than the master substrate are subsets of the master design. Thus, the invention represents
both an improved design methodology, wherein design reuse of the super-substrate is
supported for all design subsets therefor, and an improved package, whereupon multiple new
packages for multiple die (chips) of different sizes, pursuant to common netlist hierarchy (I/O
and functional) considerations, may be extracted from the super-substrate by a simple
programmatic deletion of nets.
[0025] Therefore, once the master design is completed, smaller substrates can be
created by programmatically deleting net lists from the larger master substrate. With the invention, the pin-out from the top of the substrate (at the flip-chip bumps) to the bottom of
the substrate (at the bottom surface metallurgy (BSM) pads) is predetermine for a menu of substrates. Thus, with the invention, the pattern of the BSM pads is pre-assigned for all
substrates (packages) within a given menu and there is no need to customize the substrates for
each different chip. This is possible by virtue of the improved design re-use methodology wherein the super-substrate netlist is a logical super-set of inferior (smaller, subordinate)
netlists, and the physical topology of the I/O (both TSM and BSM planes) support the logical deletion of unneeded nets for subordinate packages. Such logical or programmatic deletion
of unneeded nets is predicated upon a 3-D fanout of said nets through the package such that
the outermost I/O at the TSM plane remains the outermost row at the BSM plane (thus, the
nets do not physically cross). This procedure supports the programmatic deletion of nets in
derived packages of subordinate chips in that nets corresponding to chip JVOS from the outermost periphery of the die are deleted first and deletion continues inboard to more internal I/O as required.
[0026] For example, as shown in Figure 1, the BSM design of a master substrate is
shown. In this example, the master substrate has a size of 42.5 X 42.5 mm. In addition,
Figure 1 illustrates a number of subsets of the master substrate (shown in different scaling)
down to the smallest substrate which is 25 x 25 mm. As shown in Figure 1, in order to create
a subset of the master substrate, it is only necessary to remove selected portions of the master
substrate. The remaining BSM pads do not need to be redesigned, nor do the electrical
connections which are formed above the BSM pads need to be redesigned. The substrate could comprise ceramic, organic, plastic, semiconductor, etc.
[0027] Figures 2A and 2B show internal wiring net lists within chip packages
(substrates). The net list in Figure 2A is the master substrate, while the one shown in Figure 2B is a subset of the master shown in Figure 2A. As can be seen by comparing Figures 2A
and 2B, the designs are identical except that the outer portion (peripheral portions) of the master design in Figure 2A has been eliminated from the subset design in Figure 2B. The
substrate shown in Figure 2A is substantially larger and would be useful with a substantially larger chip than the substrate shown in Figure 2B. The package of Figure 2B can be designed
in just a few hours by simple programmatic deletion of the external most unneeded nets in
2A. A fresh design of the package shown in Figure 2B would otherwise require about two
weeks. So again, the invention provides a design methodology improvement which results
from design reuse, predicated upon two features of the invention: 1) logical super-netlist
employing a master or super-substrate (e.g., largest supportable netlist for the chip and
package combination) method; and 2) physical super-topology employing uncrossed physical nets, deleting unneeded nets from the
outermost die I/O first and proceeding inward as required.
[0028] Figures 3A-14B represent the various layers within two different substrates
(chip packages). More specifically, the "A" figures represent the master substrate while the
"B" figures represent a subset of the master within the same menu. Figures 3A-3B and
14A-14B represent the top and bottom of the substrate, respectively. Figures 4A-13B
illustrate the successive layers within the substrate.
[0029] As can be seen by comparing the "A" and "B" figures within each layer of the
different substrates, the electrical connections and wiring positions are identical for the master and the subset except that the subset does not include the peripheral region 30 that is
included within the master substrate. As explained above, this allows the subsets of the
master to be very easily and quickly designed, which produces cost savings and reduces the time it takes to bring a product to market. The substrate or package designer can leverage the
invention, new design re-use methodology, to derive subordinate logical netlists and substrates/packages quickly
and easily, saving time and money.
[0030] The master design represents the largest possible logical netlist and largest
physical wiring possible for the given die and package combination. Further, the logical
netlist is not changed or revised in any way except that programmatic (e.g., from the
outermost I/O proceeding inboard, in series, as required) deletions are allowed. Thus, the
derived subordinate netlist/package is an exact identical subset of the parent master
netlist/package. The comparison of the A and B figures in each case show how, for each
layer, the subset chip package (B) is derived simply by the deletion of wiring on each layer
from the master chip package (A). [0031] The invention discloses a hierarchical system of congruent logical and
topological coherence chip package that has a master substrate and at least one subset substrate of the master substrate. The master substrate has the largest logical and physical
rendition supportable by the chip packages. The subset substrate is derived by programmatic
deletion of unneeded nets from the master substrate. Congruent chip packages mean that for
a given menu of chip packages having at least one master chip package and a derived, smaller
chip package, all of the wiring nets of the derived, smaller chip package are common to, and
congruent (i.e., coincident) with, a subset of the wiring nets of the master chip package.
[0032] Thus, as explained above, when different sizes of chips from the same family
are placed on multiple substrate sizes, the invention designs the substrate with the largest
body size first. Designs for the smaller body sizes are then subsets of the initial design. The bottom surface pad assignments for each physical location are made common between each
substrate size to enable this sharing of design structures to produce the cost and time savings
associated with the invention.
[0033] Traditionally, each substrate design has been done from scratch, which utilizes
much more design resources, and requires a long cycle time to produce each design or netlist.
With the invention, the subset netlists can be delivered to the customer much more quickly,
by just running through a program to obtain the subset netlist, and the smaller designs can
quickly be obtained, reducing the design cycle time.
[0034] While the invention has been described in terms of preferred embodiments,
those skilled in the art will recognize that the invention can be practiced with modification
within the spirit and scope of the appended claims.

Claims

CLAIMSWhat is claimed is:
1. A hierarchical system of chip packages comprising:
a master substrate; and at least one subset substrate of said master substrate.
2. The system in claim 1 , wherein said subset substrate comprises a congruent logical
and topologically coherent portion of said master substrate.
3. The system in claim 2, wherein said subset substrate has a pin out pattern commensurate to said portion of said master substrate, such that said subset substrate is both
a logical and physical subset of the master.
4. The system in claim 2, wherein said subset substrate has identical internal net lists as
said portion of said master substrate.
5. The system in claim 1 , wherein said subset substrate is adapted to accommodate a
smaller chip than said master substrate.
6. The system in claim 1 , wherein said master substrate is the largest substrate in said
hierarchical system.
7. The system in claim 1, wherein said master substrate comprises the largest logical and
physical rendition supportable by said chip packages; and said subset substrate is derived by programmatic deletion of unneeded nets from said
master substrate.
8. A hierarchical system of chip packages comprising:
a master substrate; and at least one subset substrate of said master substrate, wherein said master substrate
comprises the largest logical and physical rendition supportable by said chip packages; and said subset substrate is derived by programmatic deletion of unneeded nets from said
master substrate.
9. The system in claim 8, wherein said subset substrate comprises a congruent logical
and topologically coherent portion of said master substrate.
10. The system in claim 9, wherein said subset substrate has a pin out pattern
commensurate to said portion of said master substrate, such that said subset substrate is both
a logical and physical subset of the master.
1 1. The system in claim 9, wherein said subset substrate has identical internal net lists as
said portion of said master substrate.
12. The system in claim 8, wherein said subset substrate is adapted to accommodate a smaller chip than said master substrate.
13. The system in claim 8, wherein said master substrate is the largest substrate in said
hierarchical system.
14. A method of forming a hierarchical system of chip packages, said method comprising:
designing a master substrate; and
selecting at least one subset substrate of said master substrate.
15. The method in claim 14, wherein said subset substrate comprises a congment logical and topologically coherent portion of said master substrate.
16. The method in claim 15, wherein said subset substrate has a pin out pattern
commensurate to said portion of said master substrate, such that said subset substrate is both a logical and physical subset of the master.
17. The method in claim 15, wherein said subset substrate has identical internal net lists
as said portion of said master substrate.
18. The method in claim 14, wherein said subset substrate is adapted to accommodate a
smaller chip than said master substrate.
19. The method in claim 14, wherein said master substrate is the largest substrate in said
hierarchical system.
20. The method in claim 14, wherein said master substrate comprises the largest logical
and physical rendition supportable by said chip packages; and
said subset substrate is derived by programmatic deletion of unneeded nets from said
master substrate.
PCT/US2002/040671 2002-12-18 2002-12-18 Nested design approach WO2004061726A1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
EP02795945A EP1573602A4 (en) 2002-12-18 2002-12-18 Nested design approach
CNA02829968XA CN1695149A (en) 2002-12-18 2002-12-18 Nested design approach
PCT/US2002/040671 WO2004061726A1 (en) 2002-12-18 2002-12-18 Nested design approach
AU2002360668A AU2002360668A1 (en) 2002-12-18 2002-12-18 Nested design approach
JP2004564625A JP4700967B2 (en) 2002-12-18 2002-12-18 Hierarchical system of multiple boards in a chip package
US11/160,307 US7325213B2 (en) 2002-12-18 2005-06-17 Nested design approach

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2002/040671 WO2004061726A1 (en) 2002-12-18 2002-12-18 Nested design approach

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/160,307 Continuation US7325213B2 (en) 2002-12-18 2005-06-17 Nested design approach

Publications (1)

Publication Number Publication Date
WO2004061726A1 true WO2004061726A1 (en) 2004-07-22

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Application Number Title Priority Date Filing Date
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Country Status (5)

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EP (1) EP1573602A4 (en)
JP (1) JP4700967B2 (en)
CN (1) CN1695149A (en)
AU (1) AU2002360668A1 (en)
WO (1) WO2004061726A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006202977A (en) * 2005-01-20 2006-08-03 Sony Corp Substrate and manufacturing method thereof, and semiconductor package and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5953236A (en) * 1995-10-31 1999-09-14 Vlsi Technology, Inc. Method and apparatus for implementing engineering change orders in integrated circuit designs
US6340542B1 (en) * 1998-12-08 2002-01-22 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device, method of manufacturing a photomask, and a master mask

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5608638A (en) * 1995-02-06 1997-03-04 Advanced Micro Devices Device and method for automation of a build sheet to manufacture a packaged integrated circuit
US5777383A (en) * 1996-05-09 1998-07-07 Lsi Logic Corporation Semiconductor chip package with interconnect layers and routing and testing methods
JPH10150120A (en) * 1996-11-19 1998-06-02 Denso Corp Printed wiring board, bga type lsi package and electronic device
US6297565B1 (en) * 1998-03-31 2001-10-02 Altera Corporation Compatible IC packages and methods for ensuring migration path

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5953236A (en) * 1995-10-31 1999-09-14 Vlsi Technology, Inc. Method and apparatus for implementing engineering change orders in integrated circuit designs
US6340542B1 (en) * 1998-12-08 2002-01-22 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device, method of manufacturing a photomask, and a master mask

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1573602A4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006202977A (en) * 2005-01-20 2006-08-03 Sony Corp Substrate and manufacturing method thereof, and semiconductor package and manufacturing method thereof

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Publication number Publication date
EP1573602A4 (en) 2009-08-26
JP4700967B2 (en) 2011-06-15
AU2002360668A1 (en) 2004-07-29
EP1573602A1 (en) 2005-09-14
JP2006511954A (en) 2006-04-06
CN1695149A (en) 2005-11-09

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