WO2004034426A3 - Non-volatile memory device and method for forming - Google Patents

Non-volatile memory device and method for forming Download PDF

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Publication number
WO2004034426A3
WO2004034426A3 PCT/US2003/030588 US0330588W WO2004034426A3 WO 2004034426 A3 WO2004034426 A3 WO 2004034426A3 US 0330588 W US0330588 W US 0330588W WO 2004034426 A3 WO2004034426 A3 WO 2004034426A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
conductivity type
implanted
channel
region
Prior art date
Application number
PCT/US2003/030588
Other languages
French (fr)
Other versions
WO2004034426A2 (en
Inventor
Gowrishankar Chindalore
Paul A Ingersoll
Craig T Swift
Alexander B Hoefler
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Priority to AU2003277017A priority Critical patent/AU2003277017A1/en
Priority to JP2004543036A priority patent/JP2006502581A/en
Publication of WO2004034426A2 publication Critical patent/WO2004034426A2/en
Publication of WO2004034426A3 publication Critical patent/WO2004034426A3/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

In one embodiment, a semiconductor device (10) has a highly doped layer (26) having a first conductivity type uniformly implanted into a semiconductor substrate (20), where a channel region (28) is located between a top surface of the substrate (20) and the highly doped layer (26). In an alternate embodiment, a semiconductor device (70) has a counterdoped channel (86) and an anti-punch through region (74) below the channel. A gate stack (32) is formed over the substrate (20). A source (52) and drain (54, 53) having a second conductivity type are implanted into the substrate. The resulting non-volatile memory cell provides a low natural threshold voltage to minimize threshold voltage drift during a read cycle. In addition, a halo region (46), having the second conductivity type and implanted at an angle in the drain side, may be used to assist in hot carrier injection which allows a higher programming speed.
PCT/US2003/030588 2002-10-09 2003-09-23 Non-volatile memory device and method for forming WO2004034426A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2003277017A AU2003277017A1 (en) 2002-10-09 2003-09-23 Non-volatile memory device and method for forming
JP2004543036A JP2006502581A (en) 2002-10-09 2003-09-23 Nonvolatile memory device and method of forming the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/267,153 2002-10-09
US10/267,153 US6887758B2 (en) 2002-10-09 2002-10-09 Non-volatile memory device and method for forming

Publications (2)

Publication Number Publication Date
WO2004034426A2 WO2004034426A2 (en) 2004-04-22
WO2004034426A3 true WO2004034426A3 (en) 2004-08-12

Family

ID=32068349

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/030588 WO2004034426A2 (en) 2002-10-09 2003-09-23 Non-volatile memory device and method for forming

Country Status (7)

Country Link
US (1) US6887758B2 (en)
JP (1) JP2006502581A (en)
KR (1) KR20050055003A (en)
CN (2) CN101197292B (en)
AU (1) AU2003277017A1 (en)
TW (1) TWI322498B (en)
WO (1) WO2004034426A2 (en)

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Also Published As

Publication number Publication date
CN101197292A (en) 2008-06-11
KR20050055003A (en) 2005-06-10
CN101197292B (en) 2010-06-23
AU2003277017A8 (en) 2004-05-04
CN100420036C (en) 2008-09-17
TWI322498B (en) 2010-03-21
JP2006502581A (en) 2006-01-19
CN1689165A (en) 2005-10-26
TW200427071A (en) 2004-12-01
AU2003277017A1 (en) 2004-05-04
US20040070030A1 (en) 2004-04-15
US6887758B2 (en) 2005-05-03
WO2004034426A2 (en) 2004-04-22

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