WO2003098434A3 - Method for ordering processor operations for modulo-scheduling - Google Patents

Method for ordering processor operations for modulo-scheduling Download PDF

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Publication number
WO2003098434A3
WO2003098434A3 PCT/US2003/015167 US0315167W WO03098434A3 WO 2003098434 A3 WO2003098434 A3 WO 2003098434A3 US 0315167 W US0315167 W US 0315167W WO 03098434 A3 WO03098434 A3 WO 03098434A3
Authority
WO
WIPO (PCT)
Prior art keywords
current operation
operations
ordered list
scheduling
modulo
Prior art date
Application number
PCT/US2003/015167
Other languages
French (fr)
Other versions
WO2003098434A2 (en
Inventor
Ralph D Hill
Original Assignee
Quicksilver Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quicksilver Tech Inc filed Critical Quicksilver Tech Inc
Priority to AU2003239454A priority Critical patent/AU2003239454A1/en
Publication of WO2003098434A2 publication Critical patent/WO2003098434A2/en
Publication of WO2003098434A3 publication Critical patent/WO2003098434A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/445—Exploiting fine grain parallelism, i.e. parallelism at instruction level
    • G06F8/4452—Software pipelining

Abstract

A method for ordering a plurality of operations that are dependent upon one another in an ordered list to be used for scheduling is provided. The method comprises identifying a current operation in the plurality of operations that is not in the ordered list. Also, it is determined if the current operation has any predecessor operations that are not in the ordered list. If the current operation has predecessor operations, predecessor operations are added to the ordered list. The current operation is then added to the ordered list and a successor operation to the current operation is identified. The successor operation is now considered the current operation and the process reiterates to determine if the current operation has any predecessor operations and continues as above. The process continues until a current operation does not have any successor operations.
PCT/US2003/015167 2002-05-15 2003-05-14 Method for ordering processor operations for modulo-scheduling WO2003098434A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003239454A AU2003239454A1 (en) 2002-05-15 2003-05-14 Method for ordering processor operations for modulo-scheduling

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14685702A 2002-05-15 2002-05-15
US10/146,857 2002-05-15

Publications (2)

Publication Number Publication Date
WO2003098434A2 WO2003098434A2 (en) 2003-11-27
WO2003098434A3 true WO2003098434A3 (en) 2004-09-30

Family

ID=29548296

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/015167 WO2003098434A2 (en) 2002-05-15 2003-05-14 Method for ordering processor operations for modulo-scheduling

Country Status (2)

Country Link
AU (1) AU2003239454A1 (en)
WO (1) WO2003098434A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5339428A (en) * 1991-09-04 1994-08-16 Digital Equipment Corporation Compiler allocating a register to a data item used between a use and store of another data item previously allocated to the register
US5555417A (en) * 1989-11-13 1996-09-10 Hewlett-Packard Company Method and apparatus for compiling computer programs with interprocedural register allocation
US5887174A (en) * 1996-06-18 1999-03-23 International Business Machines Corporation System, method, and program product for instruction scheduling in the presence of hardware lookahead accomplished by the rescheduling of idle slots
US20020013937A1 (en) * 1999-02-17 2002-01-31 Ostanevich Alexander Y. Register economy heuristic for a cycle driven multiple issue instruction scheduler

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5555417A (en) * 1989-11-13 1996-09-10 Hewlett-Packard Company Method and apparatus for compiling computer programs with interprocedural register allocation
US5339428A (en) * 1991-09-04 1994-08-16 Digital Equipment Corporation Compiler allocating a register to a data item used between a use and store of another data item previously allocated to the register
US5887174A (en) * 1996-06-18 1999-03-23 International Business Machines Corporation System, method, and program product for instruction scheduling in the presence of hardware lookahead accomplished by the rescheduling of idle slots
US20020013937A1 (en) * 1999-02-17 2002-01-31 Ostanevich Alexander Y. Register economy heuristic for a cycle driven multiple issue instruction scheduler

Also Published As

Publication number Publication date
AU2003239454A8 (en) 2003-12-02
AU2003239454A1 (en) 2003-12-02
WO2003098434A2 (en) 2003-11-27

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