WO2003090281A2

WO2003090281A2 - Single crystal silicon membranes for microelectromechanical applications

Info

Publication number: WO2003090281A2
Application number: PCT/US2003/011720
Authority: WO
Inventors: Kevin S. Jones; Mark E. Law
Original assignee: University Of Florida
Priority date: 2002-04-15
Filing date: 2003-04-15
Publication date: 2003-10-30
Also published as: WO2003090281A3; AU2003221959A1

Abstract

A method for forming a MEMS devices and related systems includes the steps of providing a single crystal substrate (320), etching a plurality of periodically placed holes (303) in the substrate, and annealing the substrate in a reducing ambient at a temperature its melting point. The holes coalesce into at least one cavity layer (318) and form at least one single crystal membrane layer (323) . The membrane layer provides a dislocation density of no more 106 disclocations/cm2. At least one MEMS structure including at least one movable portion is formed on the membrane layer. Microelectronic devices can also be formed on the single crystal substrate. The method can also be used to form MEMS devices having stacked membrane layers (323, 324).

Description

SINGLE CRYSTAL SILICON MEMBRANES FOR MICROELECTROMECHANICAL APPLICATIONS

FIELD OF THE INVENTION

The invention relates to a method of forming single crystal membrane- based microelectromechanical (MEMS) structures including MEMS sensors and improved devices derivable therefrom.

BACKGROUND

Single crystal Si membranes can be formed from a single crystal bulk substrate material through the use of a suitable etching process followed a high temperature anneal, such as the method disclosed by Sato et al. [1]. The high temperature anneal is performed in a special reducing ambient. Sato includes process specifics, such as trench etch pit depths, area of etched pits, annealing times, temperatures and ambients. The high temperature anneal is performed at a temperature which approaches, but does not exceed, the melting point of silicon (1414 °C), such as 1100 °C. Multiple membrane layers can be formed from deeper etch pits as compared to the etch pit depths used for forming single membrane layers. Sato et al. is hereby incorporated by reference into this application in its entirety.

Referring to FIG. 1(a), structure 105 shows a plurality of holes 103 having width 106 and hole-hole spacing 107 that are formed following etching of the surface of a silicon wafer. Upon the initial stages of a high temperature anneal in a reducing environment, the silicon on the surface diffuses and traps a plurality of cavities 113 disposed below the surface as shown in FIG. 1(b). If the array of etched holes is properly distributed, then these cavities 113 can coalesce into a continuous sheet as shown in FIG. 1(c) as structure 115, forming a single crystal silicon membrane 118 and a cavity region 119. As used herein, the phrase "properly distributed" refers to a close packed, substantially equally spaced, array of holes, analogous to the arrangement of pool balls in a pool rack. For example, the feature size of the etched holes 106 can be equal to the hole- to-hole spacing 107 shown in FIG. 1(a).

Following annealing in a non-reducing (e.g. hydrogen) ambient, the holes rearrange into the structure 115 which is shown in FIG. 1 (c). Structure 115 comprises single crystal Si membrane layer 118 disposed above cavity 119, where the single crystal Si membrane layer 118 is generally free of extended crystalline defects. The defect density of the resulting single crystal Si membrane layer 118 is nearly equal to that of the single crystal Si water 120, the defect density of the single crystal Si membrane layer 118 generally being about 10⁵ to 10⁶ disclocations/cm². The single crystal Si membrane layer 118 can be a thin (sub-micron) membrane layer, such 0.6 to 0.9 μm thick, and can provide an area of up to several hundred microns on a side, or more. Cavity layer 119 can have a comparable thickness to the thickness of single crystal membrane layer 118.

The Sato process was disclosed as being useful for forming silicon on insulator (SOI) substrates, upon which improved transistors could be formed. In this structure, the cavity region functions as the electrical insulator, as opposed to a silicon dioxide insulating layer in most prior SOI substrates. SUMMARY The invention uses single crystal membranes, such as Si membranes, formed from an etching and annealing process for use in forming improved microelectromechanical system (MEMS) devices and related systems. A MEMS- based system includes a single crystal substrate including at least one single crystal membrane layer, the membrane layer providing a dislocation density of no more than 10⁶ disclocations/cm². The system includes at least one MEMS device having at least one movable portion comprising at least a portion of the membrane layer. At least one microelectronic device can also be electrically connected to the MEMS device and disposed in or on the single crystal substrate. The single crystal substrate can be Si or Ge.

The MEMS device can include acoustic transducers, pressure transducers or optical sensors. The microelectronic device can include an amplifier, signal processing circuitry, control circuitry or logic circuitry. The membrane can include a suicide region when a Si substrate is provided.

A method for forming a MEMS device includes the steps of providing a single crystal substrate, etching a plurality of periodically placed holes in the single crystal substrate and annealing the single crystal substrate in a reducing ambient at a temperature below a melting point of the substrate to coalesce said holes into at least one cavity layer and forming at least one membrane layer. The membrane layer provides a dislocation density of no more than 10⁶ disclocations/cm². At least one microelectromechanical (MEMS) device having at least one movable portion is formed using the membrane layer. The method can include the step of forming at least one microelectronic device in or on the single crystal substrate. At least two single crystal membrane layers can be provided, the membrane layers at least partially stacked on one another. The method can also include the step of implanting a metal ion capable of forming a suicide with silicon into a portion of the membrane and annealing, wherein a suicide layer is formed in the implanted portion.

BRIEF DESCRIPTION OF THE DRAWINGS

A fuller understanding of the present invention and the features and benefits thereof will be accomplished upon review of the following detailed description together with the accompanying drawings, in which:

FIGs. 1(a) -(c) illustrate etching and annealing steps and the resulting structures involved in the formation of single crystal silicon membranes.

FIG. 2 illustrates a simplified cross-sectional view of a MEMS-based condenser-type microphone together with a microelectronic circuit fabricated on a common single crystal silicon die, according to an embodiment of the invention.

FIGs. 3(a) -(c) illustrate etching and annealing steps involved in the formation of multiple stacked single crystal membrane layers.

DETAILED DESCRIPTION OF THE INVENTION

The invention uses single crystal membranes, such as Si membranes, formed from an etching and annealing process for use in forming microelectromechanical system (MEMS) devices and related systems. Membranes suitable for use in forming MEMS devices can be formed from single crystal substrate materials other than Si, such as Ge or other materials that are capable of coalescing multiple cavities into a single cavity upon a suitable annealing cycle. A suitable annealing cycle generally involves heating the substrate to a temperature nearing the melting point of the substrate in a non-oxidizing ambient, but not reaching the melting point of the substrate material. In the case of silicon which has a melting point of 1414 °C, a suitable annealing temperature range is generally between 1000 °C and 1250 °C.

One area of science that offers significant size advantages, while overcoming the limitations of the large number and the large size of conventional parts is MEMS. MEMS, or the closely related field of microoptoelectromechanical systems (MOEMS), hereafter generally collectively referred to as "MEMS" refers to systems that integrate mechanical structures (moving parts) with microelectronics, and optical components in the case of MOEMS, into a package that is physically very small. MEMS devices are generally custom designed for a given purpose which requires the mechanical action of the device to be controlled by a computer. MEMS systems are generally fabricated using integrated circuit fabrication techniques or similar techniques such as surface micromachining, bulk micromachining and reactive ion etching (RIE). For example, using MEMS, various transducers, resonators, and mirrors have been built that occupy sizes that are generally measured in terms of microns or several millimeters. The degree of complexity of a given MEMS article depends on the number of movable levels or planes that the fabrication technique provides.

The invention allows replacement of MEMS devices which generally include polycrystalline layers which can involve processing steps that are not compatible with standard IC processing steps with a single crystal membrane process that is compatible with standard IC etching and annealing processes. The invention can also be used to form new and improved MEMS devices which can provide higher sensitivity and easier integration with standard IC fabrication processes.

Some MEMS sensors have been disclosed which include membrane layers which are referred to as being "single crystal". However, as explained below both known methods produce resulting Si membrane layers which include at least 10⁷ disclocations/cm². In a first method, a SiO₂ layer is first grown on a single crystal silicon substrate. One or more contact holes are then etched through the SiO₂to reach the single crystal silicon. Polycrystalline silicon is then deposited (e.g. using low pressure chemical vapor deposition) on the wafer to fill the hole(s) and overgrow on the SiO₂ surface. The polysilicon layer is then melted and recrystallizes with an orientation that approximately follows that of the bulk Si portion through contact to the polysilicon in the hole(s). An etch hole is then etched in the silicon surface layer which permits the SiO₂ layer to be removed (undercut) to produce the desired membrane layer. Resulting defect densities in the resulting membrane layer are from about 10⁸ to 10⁹ disclocations/cm². In a second method, two wafers are provided and then bonded together. A first wafer is etched to produce one or more well regions. A second wafer is provided, the second wafer being a silicon on insulator wafer (SOI), such as silicon on SiO₂. The SOI wafer has a thin layer of Si above the SiO₂ layer. The SOI wafer is placed on the first wafer, with its thin Si layer contacting the first wafer. The first and second wafer are then bonded together at a very high temperature. The top layer Si and SiO₂ layer are then removed to form thin Si membrane layers above each well. Unfortunately, stresses at the well interface during the bonding step produces significant defect generation. Resulting membrane layer defect densities are from about 10⁷ to 10¹⁰ disclocations/cm² using this method.

In contrast, the invention provides membrane layer defect densities of less than 10⁶ disclocations/cm², preferably less than 5 x 10⁵ disclocations/cm² and even closely approaching the defect density of high quality single crystal silicon substrates which generally provide around 10⁵ disclocations/cm². Thus, the invention provides a defect density improvement from at least about 1 to almost 5 orders of magnitude as compared to known methods for forming MEMS sensors including "single crystal" membrane layers. Defects act as traps in semiconducting crystals which provide carrier generation and recombination centers, which are known to cause various types of generally low frequency noise. Thus, lower defect density membrane layers provided by the invention provides lower noise sensor devices. Accordingly, the ability to form thin single crystal membrane layers using the invention may significantly improve the sensitivity of certain MEMS devices, such as those affected by noise. For example, the audio fidelity of MEMS based microphones produced using the invention can be expected to significantly benefit from the use high quality single crystal membranes. As described in M. Papila et al, "Piezoresistive Microphone Design Pareto Optimization: Tradeoff Between Sensitivity and Noise Floor", at the 44^th AIAA/ASME/ASCE/AHS Structures, Structural Dynamics, and Materials Conference, Norfolk, Virginia, pp. 1-13 (April 7-10, 2003), for piezoresistive devices, such as piezoresistive microphones, low frequency 1/f noise usually dominates the electronic noise of the device and thus limits the attainable sensitivity of the device. Piezoresistors exhibit noise with a power spectral density (PSD) that varies inversely with frequency when an external dc bias is applied. Since the PSD is more prevalent at lower frequencies, it is also known as low frequency noise. Two physical mechanisms have been proposed to account for the low frequency noise, random trapping/detrapping of carriers at surface and bulk electronic traps and random mobility fluctuations. Since the dominant mechanism depends on the surface and electronic material properties, an empirical formulation for l/f noise given by F. N. Hooge, "l/f Noise", Physica, 83B: 14-23 (1976) is used to model the l/f noise in the piezoresistor. Hooge's relation for l/f noise PSD is given by

^ύvi/f - ^■ Nf

where απ, known as the Hooge's parameter, is an empirically obtained constant which ranges from 5x10^"6 to 2x 0^"3 and is sensitive to bulk crystalline silicon imperfections as well as to the interface quality, V is the applied voltage, and N is the total number of carriers. The rms noise voltage due to l/f noise is obtained by integrating the noise PSD over the frequency range of operation,

Thus, the noise voltage of piezoresistive microphone devices is sensitive to bulk crystalline silicon imperfections as well as to the interface quality. The claimed invention can dramatically improve both the density of bulk crystalline silicon imperfections as well as to the interface quality and thus provide sensors having significantly enhanced sensitivity.

Since the membranes can be formed by coalescing multiple cavities using a high temperature annealing process, subsequent high temperature processes used in IC manufacturing should not generally affect the membranes once formed. Moreover, some suitable membrane substrates materials, such as Si or Ge, are compatible with the IC manufacturing process and will not contaminate processing equipment, such as furnaces. Thus, MEMS devices, such as sensors, can be easily integrated into conventional IC manufacturing processes. This permits manufacture of both the membrane and any needed amplifiers, signal processing, control or logic circuitry on the same die. Signal processing components can include devices such as filters and A D converters.

In addition, the invention can provide MEMS devices exhibiting enhanced reliability. The single crystal nature of the membrane layer offers improved reliability because conventional failure mechanisms such as grain creep will not be present to any significant degree using the invention.

Numerous devices are possible using single crystal Si membranes in MEMS applications. For example, accelerometers, acoustic transducers, pressure transducers, and improved optical sensors can all be formed using the invention. As noted above, because of the compatibility with IC processing it is also possible to integrate any needed electronics onto the same chip as the transducer or sensor device.

Acoustic transducers generally include piezo resistive transducers to convert the mechanical signal to an electrical signal. This structure could be realized using ultra shallow junction formation techniques including ion implantation and either rapid thermal annealing or laser annealing. Ultra shallow piezoresistive transducers disposed on the membranes according to the invention should also enhance the performance of the device.

FIG. 2 illustrates a simplified cross-sectional view of IC microphone system 200 comprising a MEMS-based condenser-type microphone 210 and at least one microelectronic circuit such as an amplifier 220, both on a common single crystal silicon die 260, according to an embodiment of the invention. The electrical connection between microphone 210 and amplifier 220 is not shown for simplicity. Condenser-type microphone 210 includes thin diaphragm electrode 270 and rigid back plate electrode.240, electrodes 270 and 240 separated by a thin air gap 250. Diaphragm electrode 270 vibrates when sound pressure is applied. The diaphragm 270 and backplate electrode 240 constitute a condenser. Although back plate electrode 240 is shown having backvent holes 245, backvent holes 245 are not required. Isolation region 225 electrically isolates diaphragm electrode 270 from backplate electrode 240. For example, isolation region 225 can be an oxide isolation which can be formed after formation of diaphragm electrode 270 according to the invention by etching the desired region in single crystal silicon 260 and filling the etched region with silicon dioxide or another electrically insulating material. Amplifier 220 is generally formed in single crystal silicon 260 using standard electronic processing following formation of diaphragm electrode 270. In operation, a battery (not shown) is connected to both diaphragm electrode 270 and backplate electrode 240, which produces an electrical potential between them and an amount of charge based on the battery voltage and the capacitance of microphone 210. As the distance between diaphragm electrode 270 and backplate electrode 240 changes as diaphragm electrode 270 moves in response to sound waves received the capacitance the condenser changes and current flow results as the battery attempts to maintain the correct charge given the new condenser capacitance. This current is electrically amplified by amplifier 220.

Single crystal membranes can also be used for improved optical sensors since the cavity can act as a good thermal insulator. Thus, the cavity can thermally isolate an IR detector from the silicon or other underlying substrate material. Ion implantation can be used to modify the electrical conductivity and composition of membranes formed. For example, Si membranes can be implanted with silicon dopant species such as boron, arsenic or phosphorus combined with a subsequent annealing step (e.g. 950 °C) to modify the electrical conductivity of the membrane layer, such as to form a N+ or P+ doped diaphragm electrode for a condenser-type microphone.

The composition of the Si membrane can also be altered through implantation of metallic species, such as Co, followed by a suitable annealing cycle, that result in the formation of a new phase, such as the silicide CoSi₂.

The use of ion implantation to convert silicon to a silicide is well documented in the literature [2]. The conversion of silicon to a silicide such as cobalt disilicide (CoSi₂) could allow a selected portion or the entire membrane to have a very high electrical conductivity. High electrical conductivity single crystal membranes can be used to form improved MEMS resonators. Thus, the conversion of all or part of a membrane to a highly electrically conductive membrane, such, as a silicide, can provide a membrane that can be vibrated at a particular frequency or used as a resonator.

The etching and annealing membrane process disclosed herein can also be used to produce multiple membranes stacked on one another. This option is not available using the lateral etch method for forming the membrane. Multiple stacked membranes can be formed by etching deep etch pits as illustrated in FIGS. 3(a)-(c).

The number of membranes formed for a given material is a function of both the radius of the etch pits and the depth of the etch pits. Figure 7 disclosed by Sato et al. provides this data for a silicon substrate. For example, for a silicon substrate including a plurality of etch pits each having a radius of 0.1 μm and a trench depth of 6 μm, approximately six (6) membrane layers are formed following a suitable annealing cycle.

Referring to FIG. 3(a), structure 305 shows a plurality of deep holes 303 resulting from the etching of holes into the surface of a wafer 320, such as a silicon wafer. Upon the initial stages of a high temperature anneal in a reducing environment, the silicon on the wafer surface diffuses and traps cavities below the surface in two or more rows 308 and 309 as shown in FIG. 3(b) as structure 310.

If the array of etched holes 303 is properly distributed, then the resulting cavities 308 and 309 can coalesce into two or more continuous separate cavities 318 and 319 as well as two or more continuous Si membranes 323 and 324. This arrangement is shown in FIG. 3(c) as structure 315. Structure 315 provides stacked silicon membranes 323 and 324 which are both single crystal and generally free of extended crystalline defects.

It may be possible to form multiple membranes iteratively, rather than in a single etching and annealing sequence. For example, a first membrane can be formed. A thin epitaxial layer can then be deposited over the surface. A second membrane can then be formed, followed by deposition of a thin epitaxial layer, and so on. Success with this technique would generally require the membrane after epitaxial growth to have sufficient mechanical strength to survive the reactive ion etching or other etching process necessary for the next layer to form.

The conductivity or composition of any buried membrane could be selectively altered through the use of ion implantation. For example, one membrane can receive implantation while another membrane does not receive any significant ion dose. This can be realized using conventional photoresist patterning and masking, where multiple membranes are disposed on the substrate surface. In the case of stacked membranes, selection of appropriate ion implant energies can place substantially all the ion dose on one or more membranes, depending on the range statistics of the particular ion in the particular material being implanted.

In addition, discrete portions of the area of a given membrane can receive implantation while other portions do not receive implant. This can be realized using conventional photoresist patterning and masking.

Multiple membranes can be used to produce features such as buried tubes and bubbles with one or more single crystal Si membrane layers disposed on top of these features. Thus, the invention can be used to produce devices that can require or can be improved by long length buried tubes under a silicon surface. Tubes can be arranged in a three dimensional matrix through the use of deeper etch pits. Operating in a third dimension offers the ability to tremendously increase the length of tubing in a wafer.

It is to be understood that while the invention has been described in conjunction with the preferred specific embodiments thereof, that the foregoing description as well as the examples which follow are intended to illustrate and not limit the scope of the invention. Other aspects, advantages and modifications within the scope of the invention will be apparent to those skilled in the art to which the invention pertains.

REFERENCES CITED:

[1] T. Sato, N. Aoki, I. Mizushima, Y. Tsunashima, "A New substrate Process of the Formation of Empty Space Silicon (ESS) Induced by Silicon Surface Migration", IEDM Proceedings, 1999.

[2] A.E. White, K.T. Short, R.C. Dynes "Mesotaxy, Single crystal growth of Buried CoSi₂ Layers'Αppl. Phys. Lett. 50, 90, 1987.

Claims

CLAIMSWe claim:

1. A MEMS-based system, comprising: a single crystal substrate including at least one single crystal membrane layer, said membrane layer providing a dislocation density of no more than 10⁶ disclocations/cm²; at least one MEMS device having at least one movable portion comprising at least a portion of said membrane layer, and at least one microelectronic device electrically connected to said MEMS device disposed in or on said single crystal substrate.

2. The system of claim 1 , wherein said single crystal substrate comprises Si or Ge.

3. The system of claim 1 , wherein said MEMS device is at least one selected from the group consisting of acoustic transducers, pressure transducers and optical sensors.

4. The system of claim 1 , wherein said microelectronic device comprises at least one device selected from the group consisting of amplifiers, signal processing circuitry, control circuitry and logic circuitry.

5. The system of claim 1 , wherein said single crystal substrate comprises a Si substrate, wherein a portion of said membrane includes a silicide region.

6. A method for forming a MEMS device, comprising the steps of: providing a single crystal substrate; etching a plurality of periodically placed holes in said single crystal substrate; annealing said single crystal substrate in a reducing ambient at a temperature below a melting point of said single crystal substrate to coalesce said holes into at least one cavity layer and form at least one membrane layer, said membrane layer providing a dislocation density of no more than 10⁶ disclocations/cm², and forming at least one microelectromechanical (MEMS) device having at least one movable portion using at least a portion of said membrane layer.

7. The method of claim 6, further comprising the step of forming at least one microelectronic device in or on said single crystal substrate.

8. The method of claim 6, wherein said single crystal substrate comprises Si or Ge.

9. The method of claim 6, wherein said MEMS device is at least one selected from the group consisting of acoustic transducers, pressure transducers and optical sensors.

10. The method of claim 6, wherein said at least one membrane comprises at least two single crystal membrane layers, said at least two membrane layers at least partially stacked on one another.

11. The method of claim 6, wherein said single crystal substrate comprises silicon, further comprising the steps of implanting a metal ion capable of forming a silicide with silicon into a portion of said membrane and annealing, wherein a silicide layer is formed in said implanted portion.

12. A MEMS sensor, comprising: a substrate including at least one single crystal membrane layer, said membrane layer providing a dislocation density of no more than 10⁶ disclocations/cm², wherein said MEMS sensor comprises at least a portion of said membrane layer.