WO2003088252A1 - Single-ended current sense amplifier - Google Patents
Single-ended current sense amplifier Download PDFInfo
- Publication number
- WO2003088252A1 WO2003088252A1 PCT/US2003/004075 US0304075W WO03088252A1 WO 2003088252 A1 WO2003088252 A1 WO 2003088252A1 US 0304075 W US0304075 W US 0304075W WO 03088252 A1 WO03088252 A1 WO 03088252A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- electrically coupled
- terminal electrically
- voltage
- sense amplifier
- bitline
- Prior art date
Links
- 230000003321 amplification Effects 0.000 claims abstract description 16
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 16
- 238000006243 chemical reaction Methods 0.000 claims abstract description 6
- 238000001914 filtration Methods 0.000 claims description 6
- 230000004913 activation Effects 0.000 claims 3
- 238000000034 method Methods 0.000 abstract description 5
- 230000015654 memory Effects 0.000 description 18
- 238000004513 sizing Methods 0.000 description 4
- 238000004458 analytical method Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 239000000872 buffer Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/067—Single-ended amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/06—Sense amplifier related aspects
- G11C2207/063—Current sense amplifiers
Definitions
- the present invention relates to sense amplifier circuits for use in memory integrated circuits.
- sense amplifiers are used to detect and determine the data content of a selected memory cell.
- EEPROM Electrically Erasable Programmable Read Only Memories
- Flash memories the sense amplifier serves two functions. Firstly, the sense amplifier precharges the bitline to a clamped value, and secondly, it senses the current flowing into the bitline, which depends on the memory cell state. Both the reliability, in terms of endurance and retention, and the performance depend to greatly on the design of the sense amplifier.
- the majority of integrated sense amplifier structures are based on a differential amplifier being used to compare the current coming from the selected memory cell to the current of a reference cell.
- the reference cells can be implemented in different ways, and are of different types.
- the reference cells are programmed one time only during the test of the memory, thus increasing the testing time.
- the ratio Icell/Iref must be maintained high enough to take into account the process fluctuations on the memory and the reference cells, and the impact of the memory cycling on the memory cells.
- it has been shown that the speed performance and reliability of the standard differential amplifier sense amplifiers are highly reduced for supply voltage values under 2V.
- 5,013,943 to Hirose discloses a single-ended sense amplifier having a precharging circuit in order to lessen the effect of changing the bitline capacitance and the variability in the current conducted by the cell.
- U.S. Pat. No. 5,666,310 to Yu et al discloses a sense amplifier circuit that senses the current drawn by the memory array and changes the state of the output once a certain current has been reached.
- a single-ended current sense amplifier having a precharge circuit to maintain a stable voltage on a bitline, a sensing circuit coupled to the bitline for sensing an amount of current flowing into the bitline, a direct current amplification circuit coupled to the sensing circuit for amplifying the current sensed on the bitline, a current-to-voltage conversion circuit for converting the sensed current to a voltage, and a voltage amplification circuit for amplifying the voltage at the sense amplifier output.
- the sense amplifier also includes an overshoot filtering circuit to filter out positive glitches on the bitline.
- the single-ended structure provides the advantage of eliminating the need to have a reference cell and a comparator circuit as are commonly used in the differential sense amp structures . This provides a savings in testing time and in the amount of die area used by the sense amplifier circuit. Additionally, the single-ended structure provides other advantages over the standard differential structures such as providing less sensitivity to mismatching and process variations and providing improved access time at low supply voltages.
- the sense amplifier of the present invention is faster and can sense very low currents compared to other single-ended sense amplifiers of the prior art.
- Fig. 1 is a block diagram of the structure of the sense amplifier circuit of the present invention.
- Fig. 2 is an electrical schematic diagram of the sense amplifier circuit of Fig. 1.
- the sense amplifier of the present invention includes a precharge circuit 20, which functions to precharge and maintain a stable voltage on the bitline 19.
- the precharge circuit 20 receives a power supply voltage Vdd 18 at an input terminal and a sense on/off signal 16 at another input terminal to acti- vate the sense amplifier circuit.
- a sensing circuit 30 is coupled to the bitline 19 and is used to sense the current flowing into the bitline.
- An overshoot filtering circuit 70 is coupled to the sensing circuit 30 in order to filter out positive glitches on the bitline.
- the output of the sensing circuit 30 goes to a direct current amplification circuit 40 which amplifies the current that was sensed by the sensing circuit.
- the amplified current is converted into a voltage by the current-to-voltage conversion circuit 50 and then the resulting voltage is amplified by the output amplification stage 60 and is provided to the sense amplifier output 80.
- the precharge circuit consists of transistors 101, 102, 103, 202, 203 and resistor 300.
- Transistors 101, 102 and 103 are PMOS type transistors while transistors 202 and 203 are NMOS type transistors.
- Transistor 101 has a gate input connected to the sense amplifier on/off signal input terminal 16, a source terminal coupled to the power supply voltage Vdd 18, and a drain terminal connected to the source terminal of PMOS transistor 102.
- Transistor 102 has a drain terminal coupled to the first end of resistor 300, and a gate terminal coupled to the gate of transistor 202.
- Transistor 202 has a drain terminal connected to the second end of resistor 300 and a source terminal connected to ground potential 99.
- Transistor 103 has a gate terminal connected to the gate terminal of transistor 202, a source terminal connected to the drain terminal of transistor 101, and a drain terminal connected to the drain of transistor 203.
- Transistor 203 has a source terminal connected to the gate of transistor 202 and a gate terminal connected between the drain terminal of transistor 202 and the second end of resistor 300.
- the precharge circuit functions to precharge and maintain a stable voltage on the bitline 19.
- the bitline 19 is connected to the source terminal of transistor 203, as shown in Fig. 2.
- the branch consisting of transistors 101, 103 and 203 must drive enough current to set the bitline 19 to its clamped voltage in a limited amount of time.
- the clamped precharge voltage is determined by the sizing of transistors 102 and 202 and the size of the resistor 300.
- the bias low line 25 goes low, turning off transistor 203, and thus turning off the precharge branch.
- the sensing circuit consists of NMOS transistor 210, and PMOS transistors 105 and 106.
- Transistor 210 has a gate terminal connected to the drain terminal of transistor 201, a drain terminal connected to the drain terminal and gate terminal of transistor 105 and to the gate terminal of transistor 106, and a source terminal connected to the bitline.
- Transistors 105 and 106 have gate terminals connected to the drain terminal of 105, and source terminals connected to the power supply voltage Vdd.
- the drain terminal of transistor 106 is connected to the drain terminal of NMOS transistor 206.
- Transistor 206 has a gate terminal 28 connected to a sense mode enable signal, and a source terminal connected to a ground potential.
- Transistor 210 serves to isolate the bitline voltage from the gate level of transistor 105, which allows the potential on the bitline to be imposed by the precharge circuit.
- Transistor 106 mirrors the cell current multiplied by a factor of N.
- the cell current is directly amplified and is supplied to the drain of the low drive 206 transistor, resulting in current-to-voltage conversion and a first voltage VI at node 58.
- Transistor 206 has a low W/L value and the current trip point of the sense amplifier can be adjusted by varying the multiplication factor N and the size of the transistor 206.
- the converted voltage VI is amplified by the voltage amplification circuit consisting of PMOS transistors 107 and 108, and NMOS transistors 207, 208 and 209.
- Transistor 107 has a source terminal connected to the power supply voltage Vdd 18 and a drain terminal connected to the drain terminal of transistor 207.
- Transis- tor 207 has a gate terminal connected to node 58 to receive the voltage VI, and a source terminal connected to a ground potential.
- Transistors 107 and 207 amplify the voltage VI to produce an amplified voltage V2 at a node 68.
- Transistors 108, 208, and 209 act as a bias current generator.
- Transistor 208 has a source terminal connected to the power supply voltage Vdd 18, and a gate terminal connected to its drain terminal and also to the gate terminal of transistor 107. Transistor 208 has a drain terminal connected to the drain terminal of transistor 108, and a gate terminal 67 connected to a sense mode enable signal. Transistor 209 has a drain terminal connected to the source of transistor 208, a gate terminal 69 connected to a power supply voltage Vdd and a source terminal connected to a ground potential .
- the bias current generator generates a bias current which is supplied through transistor 207 to the node 68.
- the voltage V2 goes through a pair of inverters 82, 83, serving as output buffers, and the output of the sense amplifier is produced at terminal 80.
- NMOS Transistors 201 and 211 are used to turn the sense amplifier off in stand by mode, or in the mode where there is no DC current.
- Transistor 201 has a drain terminal connected to the gate terminal of transistor 210 and to the source terminal of transistor 102 and to the first end of resistor 300.
- Transistor 201 also has a source terminal connected to ground potential, and a gate terminal 88 connected to sense on/off signal input terminal.
- Transistor 211 has a drain terminal connected to node 68, a source terminal connected to ground potential, and a gate terminal 88 connected to the sense on/off signal .
- the sense amplifier also includes an overshoot filtering circuit consisting of PMOS transistor 104 and NMOS transistors 204 and 205.
- Transistors 104 and 204 are connected as an inverter with the source of transistor 104 being connected to a power supply Vdd, the drain of 204 being connected to the drain of transis- tor 204, the source of transistor 204 being connected to a ground potential, and the gates of transistors 104 and 204 being connected together and being supplied with a bias high signal at the gate terminal 75.
- the output of the 104, 204 inverter is connected to the gate of transistor 205.
- Transistor 205 has a drain terminal connected to the bitline 19 and a source terminal connected to the ground potential.
- the overshoot filtering circuit serves to filter positive glitches on the bitline.
- the bias high signal goes low which produces a high signal at the output of inverter 104, 204.
- This high signal turns on transistor 205 which discharges the glitch.
- this solution has the advantage to drive current in the transistor 205 only if there is an overshoot on the bitline 19.
- the sense on/off signal 16 When the sense on/off signal 16 is off, the sense on/off signal is set high while the sense mode enable signal 28 is set low.
- the high sense mode enable signal turns on transistor 211, placing a low potential on node 68, and setting the output 80 of the sense amplifier to a low state. In this situation, there is no DC current in the structure.
- the sense on/off signal When the sense on/off signal is on, meaning that DC current is flowing, the sense on/off signal goes low and the sense mode enable signal goes high.
- the low signal turns on transistor 101 and turns off transistor 201. This allows current to flow through transistors 103, 203 and 210 and thus start the precharge circuit. As explained above, the precharge circuit will set the bitline 19.
- transistor 206 In order to read an ON cell, or a "0", transistor 206 must drive a large current equal to the current generated from the drain of transistor 106 in order for the voltage VI at its drain to rise. The variation of voltage VI is then amplified by the voltage amplification circuit (transistors 107 and 207) and the output voltage V2 at node 68 quickly goes low, providing a low signal, or "0", on the sense amplifier output 80.
- the transistor 206 In order to read a OFF cell, or a "1", the transistor 206 has no current to drive so the voltage VI at node 58 goes low. This turns off transistor 207 and the voltage V2 at node 68 increases strongly, producing a high output at the sense amplifier output 80.
- the sizing of the sense amplifier will be driven by two objectives, the first objective is to meet the targeted current trip point limit. This is obtained through a DC analysis.
- the second objective is to achieve the performance target in terms of access time and power.
- a first order modeling of the structure is needed. This first order modeling is described herein.
- the first step in this process is to use DC modeling to calculate the current trip point.
- the sense amplifier switches from 1 to 0 when node 58 reaches the output stage trip point.
- V TN threshold voltage
- VI current trip point limit
- the voltage VI at node 58 is charged through the unbalance current nl 0rl - I 206 , and the voltage V2 at node 68 is discharged through the unbalance current I 07 -I bias . So the read On cell delay can be written as:
- T rdON t prech arg e + ⁇ part ) j ⁇ V ° D _ l j
- t precharge is the precharge delay that can be adjusted by sizing the transistors 103 and 203
- C G207 is the gate capacitance of transistor 207
- C INV1 the input capacitance of inverter 82
- Cparl is the total parasitic capacitance on node 58, including the drain capacitance of transistors 206 and 106 as well as the routing
- Cpar2 is the total parasitic capacitance on node 68 including the drain capacitance of transistors 207 and 107, as well as ' the routing.
- I 206 and I 207 are the current flowing through transistors 206 and 207 respectively.
- the VI node 58 When reading an OFF memory, the VI node 58 is discharged through the current I 206 , while the V2 node 68 is charged through the current I bias . More precisely, when VI switches from V DD to V TN the output voltage V2 starts rising due to the unbalance current I bias - I N7 . This is neglected for the first order modeling.
- the read OFF cell delay can be written as :
- the above described sense amplifier provides many advantages including a high robustness to process variations, improved access time at low power supply voltages, and a full and easy implementation using low voltage CMOS devices .
Abstract
Description
Claims
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2004-7016212A KR20040106341A (en) | 2002-04-11 | 2003-02-11 | Single-ended current sense amplifier |
AU2003217374A AU2003217374A1 (en) | 2002-04-11 | 2003-02-11 | Single-ended current sense amplifier |
DE60315967T DE60315967T2 (en) | 2002-04-11 | 2003-02-11 | ASYMMETRIC ELECTRICITY AMPLIFIER |
EP03713418A EP1493158B1 (en) | 2002-04-11 | 2003-02-11 | Single-ended current sense amplifier |
JP2003585096A JP2005522814A (en) | 2002-04-11 | 2003-02-11 | Single-ended current sense amplifier |
CA002481336A CA2481336A1 (en) | 2002-04-11 | 2003-02-11 | Single-ended current sense amplifier |
NO20044701A NO20044701L (en) | 2002-04-11 | 2004-10-29 | Single-ended (single-ended) current-sensing amplifier |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/121,377 US6608787B1 (en) | 2002-04-11 | 2002-04-11 | Single-ended current sense amplifier |
US10/121,377 | 2002-04-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2003088252A1 true WO2003088252A1 (en) | 2003-10-23 |
Family
ID=27733581
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2003/004075 WO2003088252A1 (en) | 2002-04-11 | 2003-02-11 | Single-ended current sense amplifier |
Country Status (11)
Country | Link |
---|---|
US (1) | US6608787B1 (en) |
EP (1) | EP1493158B1 (en) |
JP (1) | JP2005522814A (en) |
KR (1) | KR20040106341A (en) |
CN (1) | CN1659658A (en) |
AU (1) | AU2003217374A1 (en) |
CA (1) | CA2481336A1 (en) |
DE (1) | DE60315967T2 (en) |
NO (1) | NO20044701L (en) |
TW (1) | TWI229872B (en) |
WO (1) | WO2003088252A1 (en) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7251178B2 (en) * | 2004-09-07 | 2007-07-31 | Infineon Technologies Ag | Current sense amplifier |
US7433253B2 (en) * | 2002-12-20 | 2008-10-07 | Qimonda Ag | Integrated circuit, method of operating an integrated circuit, method of manufacturing an integrated circuit, memory module, stackable memory module |
WO2005096796A2 (en) * | 2004-04-01 | 2005-10-20 | Atmel Corporation | Method and apparatus for a dual power supply to embedded non-volatile memory |
FR2885726B1 (en) * | 2005-05-11 | 2007-07-06 | Atmel Corp | DETECTION AMPLIFIER CIRCUIT FOR PARALLEL DETECTION OF FOUR CURRENT LEVELS |
US7203096B2 (en) * | 2005-06-30 | 2007-04-10 | Infineon Technologies Flash Gmbh & Co. Kg | Method and apparatus for sensing a state of a memory cell |
US7352640B2 (en) * | 2006-08-09 | 2008-04-01 | Atmel Corporation | High-speed, self-synchronized current sense amplifier |
US7561485B2 (en) * | 2007-01-12 | 2009-07-14 | Atmel Corporation | Sense architecture |
US7636264B2 (en) * | 2007-02-09 | 2009-12-22 | Atmel Corporation | Single-ended sense amplifier for very low voltage applications |
US7642815B2 (en) * | 2007-09-14 | 2010-01-05 | Atmel Corporation | Sense amplifier |
US7813201B2 (en) * | 2008-07-08 | 2010-10-12 | Atmel Corporation | Differential sense amplifier |
US8270242B2 (en) * | 2009-06-25 | 2012-09-18 | Atmel Corporation | Sense amplifier apparatus and methods |
US8169845B2 (en) * | 2009-06-25 | 2012-05-01 | Atmel Corporation | Apparatus and methods for sense amplifiers |
US8254195B2 (en) * | 2010-06-01 | 2012-08-28 | Qualcomm Incorporated | High-speed sensing for resistive memories |
US8189402B2 (en) * | 2010-06-16 | 2012-05-29 | Ememory Technology Inc. | Sensing circuit for memory cell supplied with low power |
US8605528B2 (en) | 2011-11-03 | 2013-12-10 | International Business Machines Corporation | Sense amplifier having an isolated pre-charge architecture, a memory circuit incorporating such a sense amplifier and associated methods |
US8934286B2 (en) | 2013-01-23 | 2015-01-13 | International Business Machines Corporation | Complementary metal-oxide-semiconductor (CMOS) dynamic random access memory (DRAM) cell with sense amplifier |
EP3022737B1 (en) * | 2013-07-16 | 2019-01-16 | Hella Corporate Center USA, Inc. | Current sense circuit with offset calibration |
US9589604B1 (en) * | 2015-09-17 | 2017-03-07 | International Business Machines Corporation | Single ended bitline current sense amplifier for SRAM applications |
US9484073B1 (en) | 2015-12-15 | 2016-11-01 | International Business Machines Corporation | Current-mode sense amplifier |
US11137822B2 (en) * | 2018-02-26 | 2021-10-05 | Chaoyang Semiconductor Jiangyin Technology Co., Ltd. | Method and apparatus for improving integrity of processor voltage supply with overshoot mitigation and support for DVFS |
CN110718250B (en) * | 2018-07-11 | 2021-10-01 | 西安格易安创集成电路有限公司 | Pre-charging circuit and method |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5872739A (en) * | 1997-04-17 | 1999-02-16 | Radiant Technologies | Sense amplifier for low read-voltage memory cells |
US6122212A (en) * | 1998-05-01 | 2000-09-19 | Winbond Electronics Corporation | Sense amplifier with feedbox mechanism |
US6194919B1 (en) * | 1997-12-30 | 2001-02-27 | Hyundai Electronics Industries Co., Ltd. | Main amplifier |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4918341A (en) | 1988-09-23 | 1990-04-17 | Actel Corporaton | High speed static single-ended sense amplifier |
US5013943A (en) | 1989-08-11 | 1991-05-07 | Simtek Corporation | Single ended sense amplifier with improved data recall for variable bit line current |
US5264743A (en) * | 1989-12-08 | 1993-11-23 | Hitachi, Ltd. | Semiconductor memory operating with low supply voltage |
JPH0478097A (en) * | 1990-07-13 | 1992-03-12 | Sony Corp | Memory device |
EP0700049A1 (en) * | 1994-08-31 | 1996-03-06 | STMicroelectronics S.r.l. | Reading circuit for memory cells |
US5666310A (en) | 1996-01-30 | 1997-09-09 | Cypress Semiconductor | High-speed sense amplifier having variable current level trip point |
KR100218306B1 (en) * | 1996-06-27 | 1999-09-01 | 구본준 | Voltage-current converter |
JP3116921B2 (en) * | 1998-09-22 | 2000-12-11 | 日本電気株式会社 | Semiconductor storage device |
JP2000306381A (en) * | 1999-04-21 | 2000-11-02 | Fujitsu Ltd | Semiconductor memory |
JP2000348488A (en) * | 1999-06-08 | 2000-12-15 | Mitsubishi Electric Corp | Semiconductor memory device |
US6297670B1 (en) * | 2000-03-30 | 2001-10-02 | Century Semiconductor, Inc. | Single-ended sense amplifier with adjustable noise margin and power down control |
-
2002
- 2002-04-11 US US10/121,377 patent/US6608787B1/en not_active Expired - Lifetime
-
2003
- 2003-02-11 CA CA002481336A patent/CA2481336A1/en not_active Abandoned
- 2003-02-11 EP EP03713418A patent/EP1493158B1/en not_active Expired - Fee Related
- 2003-02-11 AU AU2003217374A patent/AU2003217374A1/en not_active Abandoned
- 2003-02-11 DE DE60315967T patent/DE60315967T2/en not_active Expired - Lifetime
- 2003-02-11 WO PCT/US2003/004075 patent/WO2003088252A1/en active IP Right Grant
- 2003-02-11 CN CN038136015A patent/CN1659658A/en active Pending
- 2003-02-11 KR KR10-2004-7016212A patent/KR20040106341A/en not_active Application Discontinuation
- 2003-02-11 JP JP2003585096A patent/JP2005522814A/en not_active Withdrawn
- 2003-03-17 TW TW092105768A patent/TWI229872B/en not_active IP Right Cessation
-
2004
- 2004-10-29 NO NO20044701A patent/NO20044701L/en not_active Application Discontinuation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5872739A (en) * | 1997-04-17 | 1999-02-16 | Radiant Technologies | Sense amplifier for low read-voltage memory cells |
US6194919B1 (en) * | 1997-12-30 | 2001-02-27 | Hyundai Electronics Industries Co., Ltd. | Main amplifier |
US6122212A (en) * | 1998-05-01 | 2000-09-19 | Winbond Electronics Corporation | Sense amplifier with feedbox mechanism |
Non-Patent Citations (1)
Title |
---|
See also references of EP1493158A4 * |
Also Published As
Publication number | Publication date |
---|---|
KR20040106341A (en) | 2004-12-17 |
CN1659658A (en) | 2005-08-24 |
US6608787B1 (en) | 2003-08-19 |
EP1493158B1 (en) | 2007-08-29 |
EP1493158A4 (en) | 2006-01-25 |
TWI229872B (en) | 2005-03-21 |
CA2481336A1 (en) | 2003-10-23 |
JP2005522814A (en) | 2005-07-28 |
DE60315967D1 (en) | 2007-10-11 |
DE60315967T2 (en) | 2008-05-29 |
AU2003217374A1 (en) | 2003-10-27 |
NO20044701L (en) | 2004-10-29 |
EP1493158A1 (en) | 2005-01-05 |
TW200305887A (en) | 2003-11-01 |
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