WO2003085737A2 - Method and apparatus for stacking multiple die in a flip chip semiconductor package - Google Patents

Method and apparatus for stacking multiple die in a flip chip semiconductor package Download PDF

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Publication number
WO2003085737A2
WO2003085737A2 PCT/US2003/008716 US0308716W WO03085737A2 WO 2003085737 A2 WO2003085737 A2 WO 2003085737A2 US 0308716 W US0308716 W US 0308716W WO 03085737 A2 WO03085737 A2 WO 03085737A2
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WO
WIPO (PCT)
Prior art keywords
die
substrate
grid array
mounting
chipset
Prior art date
Application number
PCT/US2003/008716
Other languages
French (fr)
Other versions
WO2003085737A3 (en
Inventor
Joseph Barrett
Original Assignee
Intel Corporation (A Delaware Corporation)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation (A Delaware Corporation) filed Critical Intel Corporation (A Delaware Corporation)
Priority to AU2003218322A priority Critical patent/AU2003218322A1/en
Publication of WO2003085737A2 publication Critical patent/WO2003085737A2/en
Publication of WO2003085737A3 publication Critical patent/WO2003085737A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

A semiconductor package is disclosed where the package includes a first die mounted to first surface of a second die. The first surface of the second die is then mounted to a substrate. The substrate includes a hole of appropriate size to receive the first die and to allow the second die to be mounted to the substrate using conventional interconnection and assembly techniques.

Description

METHOD AND APPARATUS FOR STACKING MULTIPLE DIE IN A
FLIP CHIP SEMICONDUCTOR PACKAGE
Field Of The Invention
The present invention pertains to the field of semiconductor devices. More particularly, this invention pertains to the field of semiconductor device packaging.
Background of the Invention
One common type of semiconductor device packaging is known as "flip chip"
packaging. Prior flip chip packaging consists of a single die mounted to a package
substrate. An example of such a prior flip chip package is shown in Figure 1. The
package of Figure 1 includes a die 110 mounted to a substrate 130. The die 110 is electrically connected to the substrate 130 by way of conductive balls or bumps on the
bottom side of die 110. The under fill epoxy 120 is used to provide strain relief and to
reinforce the mechanical connection between the die 110 and the substrate 130. The
package of Figure 1 also includes solder balls 140 which will provide electrical connections to a circuit board when the package of Figure 1 is mounted to the circuit
board.
With prior flip chip packages, if a product requires more than one die within the
package, as may be desirable in order to provide additional features or configurability, the
additional die are bonded to the substrate along side the original die. An example of this is shown in Figure 2. The package of Figure 2 includes a die 210 and an additional die 215.
The die 210 and the die 215 are each mounted to the substrate 230. Under fill epoxy 220
is used to strengthen the mechanical bond between the die 210 and the substrate 230 and
also between the die 215 and the substrate 230. Solder balls 240 will provide electrical connections to a circuit board when the package of Figure 2 is mounted to the circuit board. Including multiple die on a substrate in side-by-side fashion as depicted in Figure 2
typically results in a larger, more complex substrate and therefore increased package cost.
Brief Description of the Drawings The invention will be understood more fully from the detailed description given
below and from the accompanying drawings of embodiments of the invention which,
however, should not be taken to limit the invention to the specific embodiments described,
but are for explanation and understanding only.
Figure 1 is a block diagram of a prior flip chip package.
Figure 2 is a block diagram of a prior flip chip package with more than one die.
Figure 3 is a block diagram of one embodiment of a package with one die mounted
to a surface of another die which is then mounted to a substrate.
Figure 4 is a block diagram of one embodiment of a package with more than one die mounted to a surface of an additional die which is then mounted to a substrate.
Figure 5 is a block diagram of one embodiment of a system including a chipset
component having more than one die.
Detailed Description
Figure 3 is a block diagram of one embodiment of a package with a die 350
mounted to a surface of another die 310 which is then mounted to a substrate 330. This
differs from prior flip chip packages such as that shown in Figure 2 in that one die is mounted to another die rather than mounting each die adjacent to each other on the substrate. The configuration of Figure 3 results in a reduction of package size and cost when more than one die is needed.
For the example embodiment of Figure 3, the die 350 is mounted to the die 310 by way of a ball grid array. The die 310 is mounted to the substrate 330 also by way of a ball grid array. Although the use of ball grid arrays are discussed in connection with Figure 3, other embodiments are possible using pin grid arrays, land grid arrays, or bump grid arrays for the connections between the die 350 and the die 310 and also for the connections between the die 310 and the substrate 330.
The substrate 330 features a hole of appropriate size to receive the die 350 and to allow the die 310 to be mounted to the substrate using conventional flip chip interconnection and assembly techniques. Although the hole in the substrate 330 is shown to extend from the top surface of the substrate 330 all the way to the bottom surface of the substrate 330, other embodiments are possible using holes that do not extend all the way to the bottom surface. Under fill epoxy 320 may be used under the die 310 and surrounding the die 350 in order to provide strain relief and to ensure satisfactory reliability of the assembled package.
In assembling the package of Figure 3, the die 350 would first be mounted to the die 310, then the die 310 would be mounted to the substrate 330. The under fill epoxy 320 may then be applied.
The substrate 330 maybe implemented using organic materials or maybe implemented using other substrate technologies, such as ceramic. Figure 4 is a block diagram of one embodiment of a package with a die 450 and an additional die 460 mounted to a surface of another die 410 which is then mounted to a substrate 430.
For the example embodiment of Figure 4, the die 450 and the die 460 are mounted to the die 410 by way of a ball grid array. The die 410 is mounted to the substrate 430 also by way of a ball grid array. Although the use ball grid arrays are discussed in connection with Figure 4, other embodiments are possible using pin grid arrays, land grid arrays, or bump grid arrays for the connections between the die 450 and the die 410, between the die 460 and the die 410, and further for the connections between the die 410 and the substrate 430.
The substrate 430 features a hole of appropriate size to receive the die 450 and the die 460 and to allow the die 410 to be mounted to the substrate 430 using conventional flip chip interconnection and assembly techniques. Although the hole in the substrate 430 is shown to extend from the top surface of the substrate 430 all the way to the bottom surface of the substrate 430, other embodiments are possible using holes that do not extend all the way to the bottom surface.
As with the example embodiment discussed above in connection with Figure 3, under fill epoxy 420 may be used under the die 410 and surrounding the die 450 and the die 460 in order to provide strain relief and to ensure satisfactory reliability of the assembled package.
In assembling the package of Figure 4, the die 450 and the die 460 would first be mounted to the die 410, then the die 410 would be mounted to the substrate 430. The under fill epoxy 420 may then be applied. As with the example embodiment of Figure 3, the substrate 430 maybe implemented using organic materials or may be implemented using other substrate technologies, such as ceramic.
Figure 5 is a block diagram of one embodiment of a system including a chipset component enclosed in a package 590 having more than one die. For this example embodiment, the package 590 includes a first die implementing a graphics accelerator 520 and a second die implementing a system logic device 530.
The package 590 is coupled to a processor 510, a system memory 540, and an input/output hub 560. The input/output hub is further coupled to a peripheral device bus 580 and a storage device 570.
The package 590 maybe implemented in accordance with the example embodiment described above in connection with Figure 3. The graphics accelerator 520 corresponds to the die 350 of Figure 3 and the system logic device 530 corresponds to the die 310 of Figure 3. Although the example embodiment of Figure 5 includes a graphics accelerator and a system logic device sharing a package in accordance with the example embodiment described in connection with Figure 3, other embodiments are possible with any of a wide range of devices being combined. For example, a die including a cache memory may be coupled with a die including a system logic (chipset) device having a cache controller. Another example may include a die including a graphics memory coupled with a die including a graphics controller.
In addition to the techniques described above, other embodiments are possible where one die is wire-bonded to another die. Further, although the above example embodiments are discussed in connection with system logic devices within a computer
system, other embodiments are possible for other devices used in cell phones, pagers, and
anywhere else that semiconductor devices are used.
In the foregoing specification the invention has been described with reference to
specific exemplary embodiments thereof. It will, however, be evident that various
modifications and changes may be made thereto without departing from the broader spirit
and scope of the invention as set forth in the appended claims. The specification and
drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.
Reference in the specification to "an embodiment," "one embodiment," "some
embodiments," or "other embodiments" means that a particular feature, structure, or
characteristic described in connection with the embodiments is included in at least some
embodiments, but not necessarily all embodiments, of the invention. The various
appearances of "an embodiment," "one embodiment," or "some embodiments" are not
necessarily all referring to the same embodiments.

Claims

CLAIMSWhat is claimed is:
1. An apparatus, comprising: a substrate including a first surface and a second surface, the substrate further including a hole extending at least partially from the first surface to the second surface; a first die including a first surface and a second surface, the first surface of the first die mounted to the first surface of the substrate; and a second die mounted to the first surface of the first die.
2. The apparatus of claim 1, wherein the second die is mounted to the first die using a ball grid array.
3. The apparatus of claim 1, wherein the first die is mounted to the substrate using a ball grid array.
4. The apparatus of claim 1, wherein the second die is mounted to the first die using a land grid array.
5. The apparatus of claim 1, wherein the first die is mounted to the substrate using a land grid array.
6. The apparatus of claim 1, wherein the second die is mounted to the first die using a pin grid array.
7. The apparatus of claim 1, wherein the first die is mounted to the substrate using
a pin grid array.
8. The apparatus of claim 1, wherein the second die is mounted to the first die
using a bump grid array.
9. The apparatus of claim 1, wherein the first die is mounted to the substrate using
a bump grid array.
10. The apparatus of claim 1, wherein the first die includes a chipset device, the
chipset device including a cache controller.
11. The apparatus of claim 10, wherein the second die includes a cache memory.
12. The apparatus of claim 1, wherein the first die includes a chipset device, the
chipset device including an interface to a graphics device.
13. The apparatus of claim 12, wherein the second die includes a graphics device.
14. The apparatus of claim 1, wherein the first die includes a chipset device, the
chipset device including a graphics controller.
15. The apparatus of claim 14, wherein the second die includes a graphics
memory.
16. A method, comprising: mounting a second die to a first surface of a first die; and mounting the first surface of the first die to a substrate, the substrate including a hole to accommodate the second die.
17. The method of claim 16, wherein mounting the second die to the first surface of the first die includes mounting the second die to the first surface of the first die using a ball grid array.
18. The method of claim 16, wherein mounting the second die to the first surface of the first die includes mounting the second die to the first surface of the first die using a land grid array.
19. The method of claim 16, wherein mounting the second die to the first surface of the first die includes mounting the second die to the first surface of the first die using a pin grid array.
20. The method of claim 16, wherein mounting the first surface of the first die to the substrate includes mounting the first surface of the first die to the substrate using a ball grid array.
21. The method of claim 16, wherein mounting the first surface of the first die to the subsfrate includes mounting the first surface of the first die to the substrate using a land grid array.
22. The method of claim 16, wherein mounting the first surface of the first die to the subsfrate includes mounting the first surface of the first die to the substrate using a pin
grid array.
23. The method of claim 16, wherein mounting the first surface of the first die to the subsfrate includes mounting the first surface of the first die to the substrate using a bump grid array.
24. The method of claim 16, wherein mounting the first surface of the first die to the substrate includes mounting the first surface of the first die to the substrate using a bump grid array.
25. A system, comprising: a processor; and a chipset component coupled to the processor, the component including a first device implemented on a first die and a second device implemented on a second die, the chipset component including a substrate having a first surface and a second surface, the subsfrate further including a hole extending at least partially from the first surface to
the second surface, the first die including a first surface and a
second surface, the first surface of the first die mounted to the first
surface of the substrate, and the second die mounted to the first
surface of the first die.
26. The system of claim 25, wherein the second die is mounted to the first die
using a ball grid array.
27. The system of claim 25, wherein the first die is mounted to the substrate using
a ball grid array.
28. The system of claim 25, wherein the second die is mounted to the first die
using a land grid array.
29. The system of claim 25, wherein the first die is mounted to the subsfrate using
a land grid array.
30. The system of claim 25, wherein the first die includes a system logic device,
the system logic device including a cache controller.
31. The system of claim 30, wherein the second die includes a cache memory.
32. The system of claim 25, wherein the first die includes a system logic device, the system logic device including an interface to a grapliics device.
33. The system of claim 32, wherein the second die includes a graphics device.
PCT/US2003/008716 2002-03-29 2003-03-21 Method and apparatus for stacking multiple die in a flip chip semiconductor package WO2003085737A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003218322A AU2003218322A1 (en) 2002-03-29 2003-03-21 Method and apparatus for stacking multiple die in a flip chip semiconductor package

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/112,631 US20030183934A1 (en) 2002-03-29 2002-03-29 Method and apparatus for stacking multiple die in a flip chip semiconductor package
US10/112,631 2002-03-29

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Publication Number Publication Date
WO2003085737A2 true WO2003085737A2 (en) 2003-10-16
WO2003085737A3 WO2003085737A3 (en) 2003-11-27

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WO2003085737A3 (en) 2003-11-27

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