WO2003077119A1 - Hardware implementation of the secure hash standard - Google Patents
Hardware implementation of the secure hash standard Download PDFInfo
- Publication number
- WO2003077119A1 WO2003077119A1 PCT/US2003/007000 US0307000W WO03077119A1 WO 2003077119 A1 WO2003077119 A1 WO 2003077119A1 US 0307000 W US0307000 W US 0307000W WO 03077119 A1 WO03077119 A1 WO 03077119A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data path
- integrated circuit
- address
- memory
- controller
- Prior art date
Links
- 238000000034 method Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 12
- 230000003044 adaptive effect Effects 0.000 description 6
- 101100457843 Schizosaccharomyces pombe (strain 972 / ATCC 24843) tit1 gene Proteins 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 230000001186 cumulative effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
- G06F9/3879—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30029—Logical and Boolean instructions, e.g. XOR, NOT
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
- G06F9/3893—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
- G06F9/3895—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0643—Hash functions, e.g. MD5, SHA, HMAC or f9 MAC
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Mathematical Physics (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Storage Device Security (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2003217991A AU2003217991A1 (en) | 2002-03-05 | 2003-03-05 | Hardware implementation of the secure hash standard |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/093,156 US7489779B2 (en) | 2001-03-22 | 2002-03-05 | Hardware implementation of the secure hash standard |
US10/093,156 | 2002-03-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2003077119A1 true WO2003077119A1 (en) | 2003-09-18 |
Family
ID=27804197
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2003/007000 WO2003077119A1 (en) | 2002-03-05 | 2003-03-05 | Hardware implementation of the secure hash standard |
Country Status (3)
Country | Link |
---|---|
US (2) | US7489779B2 (en) |
AU (1) | AU2003217991A1 (en) |
WO (1) | WO2003077119A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1814026A2 (en) * | 2005-12-29 | 2007-08-01 | Intel Corporation | Method and apparatus to attain direct communication between accelerator and instruction sequencer |
Families Citing this family (17)
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DE10254320A1 (en) * | 2002-11-21 | 2004-06-03 | Philips Intellectual Property & Standards Gmbh | Circuit arrangement with non-volatile memory module and method for encrypting / decrypting data of the non-volatile memory module |
TWI238636B (en) * | 2003-06-19 | 2005-08-21 | Yen-Fu Liu | Operation device and method of fast secure hash algorithm |
US7972221B2 (en) * | 2004-03-10 | 2011-07-05 | Acushnet Company | Method of spherical object orientation and orienter for the same |
US9652637B2 (en) | 2005-05-23 | 2017-05-16 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Method and system for allowing no code download in a code download scheme |
US9904809B2 (en) | 2006-02-27 | 2018-02-27 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Method and system for multi-level security initialization and configuration |
US9177176B2 (en) * | 2006-02-27 | 2015-11-03 | Broadcom Corporation | Method and system for secure system-on-a-chip architecture for multimedia data processing |
US7779099B2 (en) * | 2006-03-16 | 2010-08-17 | Us Beverage Net Inc. | Distributed intelligent systems and methods therefor |
US9489318B2 (en) | 2006-06-19 | 2016-11-08 | Broadcom Corporation | Method and system for accessing protected memory |
KR100901697B1 (en) * | 2007-07-09 | 2009-06-08 | 한국전자통신연구원 | Apparatus for low power ???-1 hash operation and Apparatus for low power ???? cryptographic using this |
US8755515B1 (en) | 2008-09-29 | 2014-06-17 | Wai Wu | Parallel signal processing system and method |
US9680637B2 (en) * | 2009-05-01 | 2017-06-13 | Harris Corporation | Secure hashing device using multiple different SHA variants and related methods |
JP6238774B2 (en) | 2013-02-21 | 2017-11-29 | キヤノン株式会社 | Hash value generator |
JP6113091B2 (en) * | 2013-03-07 | 2017-04-12 | キヤノン株式会社 | Hash value generator |
US9135203B2 (en) | 2013-05-01 | 2015-09-15 | Jonathan Glickman | Computer system and a computer device |
US10095631B2 (en) * | 2015-12-10 | 2018-10-09 | Arm Limited | System address map for hashing within a chip and between chips |
US10454670B2 (en) | 2016-06-10 | 2019-10-22 | Cryptography Research, Inc. | Memory optimization for nested hash operations |
JP2019164713A (en) | 2018-03-20 | 2019-09-26 | 東芝メモリ株式会社 | Storage system and data transfer method |
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Also Published As
Publication number | Publication date |
---|---|
AU2003217991A1 (en) | 2003-09-22 |
US20030135743A1 (en) | 2003-07-17 |
US20090161863A1 (en) | 2009-06-25 |
US7489779B2 (en) | 2009-02-10 |
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