WO2003075460A3 - Low power dynamic logic gate with full voltage swing operation - Google Patents

Low power dynamic logic gate with full voltage swing operation Download PDF

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Publication number
WO2003075460A3
WO2003075460A3 PCT/US2003/006429 US0306429W WO03075460A3 WO 2003075460 A3 WO2003075460 A3 WO 2003075460A3 US 0306429 W US0306429 W US 0306429W WO 03075460 A3 WO03075460 A3 WO 03075460A3
Authority
WO
WIPO (PCT)
Prior art keywords
output node
precharge
clock line
path
control circuit
Prior art date
Application number
PCT/US2003/006429
Other languages
French (fr)
Other versions
WO2003075460A2 (en
Inventor
Jianbin Wu
Lei Wang
Qiang Li
Original Assignee
Piconetics Inc
Jianbin Wu
Lei Wang
Qiang Li
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Piconetics Inc, Jianbin Wu, Lei Wang, Qiang Li filed Critical Piconetics Inc
Priority to AU2003225639A priority Critical patent/AU2003225639A1/en
Publication of WO2003075460A2 publication Critical patent/WO2003075460A2/en
Publication of WO2003075460A3 publication Critical patent/WO2003075460A3/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0019—Arrangements for reducing power consumption by energy recovery or adiabatic operation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

Dynamic low-power logic using recycled energy is disclosed. Logic circuits have a discharge path (46), a precharge path (40) and a control circuit (42, 44). The precharge path is a PMOS transistor (40) coupled between the clock line 'CLK' and the output node (16) of the circuit and configured to charge the output node to the logic high voltage of the clock line during a precharge phase. During an evaluation phase, the discharge path computes the desired logic function at the output node. A control circuit is connected between the output node and the clock line and to the gate of the precharge path transistor. The control circuit provides the proper gate drive, regardless of the voltage on the output node or the inputs to the discharge path, to guarantee that the precharge transistor fully charges the output node to the logic high voltage of the clock line, which provides recycled energy for operating the circuit.
PCT/US2003/006429 2002-03-01 2003-03-03 Low power dynamic logic gate with full voltage swing operation WO2003075460A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003225639A AU2003225639A1 (en) 2002-03-01 2003-03-03 Low power dynamic logic gate with full voltage swing operation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/087,604 US6552574B1 (en) 2002-03-01 2002-03-01 Low power dynamic logic gate with full voltage swing operation
US10/087,604 2002-03-01

Publications (2)

Publication Number Publication Date
WO2003075460A2 WO2003075460A2 (en) 2003-09-12
WO2003075460A3 true WO2003075460A3 (en) 2004-01-22

Family

ID=22206170

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/006429 WO2003075460A2 (en) 2002-03-01 2003-03-03 Low power dynamic logic gate with full voltage swing operation

Country Status (5)

Country Link
US (5) US6552574B1 (en)
CN (1) CN1650522A (en)
AU (1) AU2003225639A1 (en)
TW (1) TW595100B (en)
WO (1) WO2003075460A2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6552574B1 (en) * 2002-03-01 2003-04-22 Piconetics, Inc. Low power dynamic logic gate with full voltage swing operation
US7870346B2 (en) 2003-03-10 2011-01-11 Marvell International Ltd. Servo controller interface module for embedded disk controllers
US7457903B2 (en) * 2003-03-10 2008-11-25 Marvell International Ltd. Interrupt controller for processing fast and regular interrupts
US7039771B1 (en) 2003-03-10 2006-05-02 Marvell International Ltd. Method and system for supporting multiple external serial port devices using a serial port controller in embedded disk controllers
US7492545B1 (en) * 2003-03-10 2009-02-17 Marvell International Ltd. Method and system for automatic time base adjustment for disk drive servo controllers
US7099963B2 (en) * 2003-03-10 2006-08-29 Qlogic Corporation Method and system for monitoring embedded disk controller components
US8628564B2 (en) * 2004-05-25 2014-01-14 Covidien Lp Methods and apparatus for luminal stenting
US20070194150A1 (en) * 2005-10-19 2007-08-23 Orbit Irrigation Products, Inc. Combined valve, filter, and regulator irrigation apparatus
US20070202912A1 (en) * 2006-02-28 2007-08-30 Helix Micro, Inc. Transmission Line Power Supply for Energy Efficient Circuits
CN104575425B (en) * 2015-01-09 2017-04-12 深圳市华星光电技术有限公司 Scanning driving circuit and NAND logic operation circuit thereof
WO2016183687A1 (en) * 2015-05-20 2016-11-24 Nikolaos Papadopoulos Circuit, system and method for thin-film transistor logic gates
KR102261300B1 (en) * 2015-06-22 2021-06-09 삼성전자주식회사 Clock gating circuit operating at high speed

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4017741A (en) * 1975-11-13 1977-04-12 Rca Corporation Dynamic shift register cell
JPH07249982A (en) * 1994-03-10 1995-09-26 Fujitsu Ltd Dynamic logic circuit
US5473270A (en) * 1993-05-28 1995-12-05 At&T Corp. Adiabatic dynamic precharge boost circuitry
US6150848A (en) * 1997-11-10 2000-11-21 The United States Of America As Represented By The Secretary Of The Navy Two-phase dynamic logic circuits for gallium arsenide complementary HIGFET fabrication

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5459414A (en) * 1993-05-28 1995-10-17 At&T Corp. Adiabatic dynamic logic
JP3313276B2 (en) * 1995-03-15 2002-08-12 株式会社東芝 MOS gate circuit and power supply method thereof
FR2796224B1 (en) * 1999-07-08 2001-09-07 Suisse Electronique Microtech ADIABATIC LOGIC CIRCUIT
US6448816B1 (en) * 2000-07-11 2002-09-10 Piconetics, Inc. Resonant logic and the implementation of low power digital integrated circuits
US6552574B1 (en) * 2002-03-01 2003-04-22 Piconetics, Inc. Low power dynamic logic gate with full voltage swing operation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4017741A (en) * 1975-11-13 1977-04-12 Rca Corporation Dynamic shift register cell
US5473270A (en) * 1993-05-28 1995-12-05 At&T Corp. Adiabatic dynamic precharge boost circuitry
JPH07249982A (en) * 1994-03-10 1995-09-26 Fujitsu Ltd Dynamic logic circuit
US6150848A (en) * 1997-11-10 2000-11-21 The United States Of America As Represented By The Secretary Of The Navy Two-phase dynamic logic circuits for gallium arsenide complementary HIGFET fabrication

Also Published As

Publication number Publication date
AU2003225639A1 (en) 2003-09-16
AU2003225639A8 (en) 2003-09-16
US6784696B1 (en) 2004-08-31
US20060055429A1 (en) 2006-03-16
WO2003075460A2 (en) 2003-09-12
US6552574B1 (en) 2003-04-22
CN1650522A (en) 2005-08-03
US20040257116A1 (en) 2004-12-23
US6693462B1 (en) 2004-02-17
TW595100B (en) 2004-06-21
TW200305310A (en) 2003-10-16

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