WO2003071432A3 - Bussysteme und rekonfigurationsverfahren - Google Patents

Bussysteme und rekonfigurationsverfahren Download PDF

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Publication number
WO2003071432A3
WO2003071432A3 PCT/DE2003/000489 DE0300489W WO03071432A3 WO 2003071432 A3 WO2003071432 A3 WO 2003071432A3 DE 0300489 W DE0300489 W DE 0300489W WO 03071432 A3 WO03071432 A3 WO 03071432A3
Authority
WO
WIPO (PCT)
Prior art keywords
reconfiguration
bus systems
optimisation
configuration
methods
Prior art date
Application number
PCT/DE2003/000489
Other languages
English (en)
French (fr)
Other versions
WO2003071432A2 (de
Inventor
Martin Vorbach
Volker Baumgarte
Gerd Ehlers
Original Assignee
Pact Xpp Technologies Ag
Martin Vorbach
Volker Baumgarte
Gerd Ehlers
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10240000A external-priority patent/DE10240000A1/de
Priority to AU2003214003A priority Critical patent/AU2003214003A1/en
Priority to DE10390689T priority patent/DE10390689D2/de
Priority to EP03709624A priority patent/EP1514193B1/de
Priority to DE50310198T priority patent/DE50310198D1/de
Priority to US10/504,684 priority patent/US8127061B2/en
Application filed by Pact Xpp Technologies Ag, Martin Vorbach, Volker Baumgarte, Gerd Ehlers filed Critical Pact Xpp Technologies Ag
Priority to US10/508,559 priority patent/US20060075211A1/en
Priority to PCT/DE2003/000942 priority patent/WO2003081454A2/de
Priority to AU2003223892A priority patent/AU2003223892A1/en
Priority to EP03720231A priority patent/EP1518186A2/de
Priority to EP03776856.1A priority patent/EP1537501B1/de
Priority to AU2003286131A priority patent/AU2003286131A1/en
Priority to PCT/EP2003/008081 priority patent/WO2004021176A2/de
Priority to JP2005506110A priority patent/JP2005535055A/ja
Priority to PCT/EP2003/008080 priority patent/WO2004015568A2/en
Priority to US10/523,764 priority patent/US8156284B2/en
Priority to AU2003260323A priority patent/AU2003260323A1/en
Priority to EP03784053A priority patent/EP1535190B1/de
Publication of WO2003071432A2 publication Critical patent/WO2003071432A2/de
Publication of WO2003071432A3 publication Critical patent/WO2003071432A3/de
Priority to US12/570,943 priority patent/US8914590B2/en
Priority to US12/621,860 priority patent/US8281265B2/en
Priority to US12/729,090 priority patent/US20100174868A1/en
Priority to US12/729,932 priority patent/US20110161977A1/en
Priority to US12/947,167 priority patent/US20110238948A1/en
Priority to US13/324,048 priority patent/US20120151113A1/en
Priority to US14/540,782 priority patent/US20150074352A1/en
Priority to US14/923,702 priority patent/US10579584B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Abstract

Die vorliegende Erfindung befaßt sich mit Verfahren und Ausgestaltungen von Bussystemen für konfigurierbare Architekturen. Die Optimierung der Konfigurations- und Rekonfigurationseffizenz wird besonders berücksichtigt.
PCT/DE2003/000489 2002-02-18 2003-02-18 Bussysteme und rekonfigurationsverfahren WO2003071432A2 (de)

Priority Applications (25)

Application Number Priority Date Filing Date Title
AU2003214003A AU2003214003A1 (en) 2002-02-18 2003-02-18 Bus systems and method for reconfiguration
DE10390689T DE10390689D2 (de) 2002-02-18 2003-02-18 Bussysteme und Rekonfigurationsverfahren
EP03709624A EP1514193B1 (de) 2002-02-18 2003-02-18 Bussysteme und rekonfigurationsverfahren
DE50310198T DE50310198D1 (de) 2002-02-18 2003-02-18 Bussysteme und rekonfigurationsverfahren
US10/504,684 US8127061B2 (en) 2002-02-18 2003-02-18 Bus systems and reconfiguration methods
US10/508,559 US20060075211A1 (en) 2002-03-21 2003-03-21 Method and device for data processing
EP03720231A EP1518186A2 (de) 2002-03-21 2003-03-21 Verfahren und vorrichtung zur datenverarbeitung
PCT/DE2003/000942 WO2003081454A2 (de) 2002-03-21 2003-03-21 Verfahren und vorrichtung zur datenverarbeitung
AU2003223892A AU2003223892A1 (en) 2002-03-21 2003-03-21 Method and device for data processing
EP03776856.1A EP1537501B1 (de) 2002-08-07 2003-07-23 Verfahren und vorrichtung zur datenverarbeitung
AU2003286131A AU2003286131A1 (en) 2002-08-07 2003-07-23 Method and device for processing data
PCT/EP2003/008081 WO2004021176A2 (de) 2002-08-07 2003-07-23 Verfahren und vorrichtung zur datenverarbeitung
EP03784053A EP1535190B1 (de) 2002-08-07 2003-07-24 Verfahren zum gleichzeitigen Betreiben eines sequenziellen Prozessors und eines rekonfigurierbaren Arrays
JP2005506110A JP2005535055A (ja) 2002-08-07 2003-07-24 データ処理方法およびデータ処理装置
AU2003260323A AU2003260323A1 (en) 2002-08-07 2003-07-24 Data processing method and device
PCT/EP2003/008080 WO2004015568A2 (en) 2002-08-07 2003-07-24 Data processing method and device
US10/523,764 US8156284B2 (en) 2002-08-07 2003-07-24 Data processing method and device
US12/570,943 US8914590B2 (en) 2002-08-07 2009-09-30 Data processing method and device
US12/621,860 US8281265B2 (en) 2002-08-07 2009-11-19 Method and device for processing data
US12/729,090 US20100174868A1 (en) 2002-03-21 2010-03-22 Processor device having a sequential data processing unit and an arrangement of data processing elements
US12/729,932 US20110161977A1 (en) 2002-03-21 2010-03-23 Method and device for data processing
US12/947,167 US20110238948A1 (en) 2002-08-07 2010-11-16 Method and device for coupling a data processing unit and a data processing array
US13/324,048 US20120151113A1 (en) 2002-02-18 2011-12-13 Bus systems and methods for controlling data flow in a field of processing elements
US14/540,782 US20150074352A1 (en) 2002-03-21 2014-11-13 Multiprocessor Having Segmented Cache Memory
US14/923,702 US10579584B2 (en) 2002-03-21 2015-10-27 Integrated data processing core and array data processor and method for processing algorithms

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE10206857 2002-02-18
DE10206857.7 2002-02-18
DE10240000.8 2002-08-27
DE10240000A DE10240000A1 (de) 2002-08-27 2002-08-27 Busssysteme und Rekonfigurationsverfahren

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/324,048 Division US20120151113A1 (en) 2002-02-18 2011-12-13 Bus systems and methods for controlling data flow in a field of processing elements

Publications (2)

Publication Number Publication Date
WO2003071432A2 WO2003071432A2 (de) 2003-08-28
WO2003071432A3 true WO2003071432A3 (de) 2004-12-23

Family

ID=27758395

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/000489 WO2003071432A2 (de) 2002-02-18 2003-02-18 Bussysteme und rekonfigurationsverfahren

Country Status (6)

Country Link
US (2) US8127061B2 (de)
EP (2) EP1514193B1 (de)
AT (2) ATE538439T1 (de)
AU (1) AU2003214003A1 (de)
DE (2) DE10390689D2 (de)
WO (1) WO2003071432A2 (de)

Families Citing this family (4)

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JP2016178229A (ja) 2015-03-20 2016-10-06 株式会社東芝 再構成可能な回路
TWI709428B (zh) * 2018-01-10 2020-11-11 美商推奔控股有限公司 組態一匯流排之方法及遊戲主控台
US11803507B2 (en) 2018-10-29 2023-10-31 Secturion Systems, Inc. Data stream protocol field decoding by a systolic array

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US8127061B2 (en) 2012-02-28
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