WO2003065205A8 - Data transfer mechanism - Google Patents
Data transfer mechanismInfo
- Publication number
- WO2003065205A8 WO2003065205A8 PCT/US2003/001579 US0301579W WO03065205A8 WO 2003065205 A8 WO2003065205 A8 WO 2003065205A8 US 0301579 W US0301579 W US 0301579W WO 03065205 A8 WO03065205 A8 WO 03065205A8
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- bus
- data
- data transfer
- processing agent
- transfer mechanism
- Prior art date
Links
- 238000000034 method Methods 0.000 abstract 2
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
Abstract
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020037017300A KR100895536B1 (en) | 2002-01-25 | 2003-01-16 | Data transfer mechanism |
DE60334784T DE60334784D1 (en) | 2002-01-25 | 2003-01-16 | DATA TRANSFER MECHANISM |
CN03802115.3A CN101027634B (en) | 2002-01-25 | 2003-01-16 | data transfer mechanism |
CA002473548A CA2473548A1 (en) | 2002-01-25 | 2003-01-16 | Data transfer mechanism |
EP03734963A EP1493081B1 (en) | 2002-01-25 | 2003-01-16 | Data transfer mechanism |
AT03734963T ATE487179T1 (en) | 2002-01-25 | 2003-01-16 | DATA TRANSFER MECHANISM |
HK05100730.0A HK1070704A1 (en) | 2002-01-25 | 2005-01-27 | Data transfer mechanism |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/057,738 US7610451B2 (en) | 2002-01-25 | 2002-01-25 | Data transfer mechanism using unidirectional pull bus and push bus |
US10/057,738 | 2002-01-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2003065205A2 WO2003065205A2 (en) | 2003-08-07 |
WO2003065205A8 true WO2003065205A8 (en) | 2004-10-28 |
Family
ID=27609479
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2003/001579 WO2003065205A2 (en) | 2002-01-25 | 2003-01-16 | Data transfer mechanism |
Country Status (10)
Country | Link |
---|---|
US (1) | US7610451B2 (en) |
EP (1) | EP1493081B1 (en) |
KR (1) | KR100895536B1 (en) |
CN (1) | CN101027634B (en) |
AT (1) | ATE487179T1 (en) |
CA (1) | CA2473548A1 (en) |
DE (1) | DE60334784D1 (en) |
HK (1) | HK1070704A1 (en) |
TW (1) | TWI236595B (en) |
WO (1) | WO2003065205A2 (en) |
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-
2002
- 2002-01-25 US US10/057,738 patent/US7610451B2/en not_active Expired - Fee Related
-
2003
- 2003-01-16 EP EP03734963A patent/EP1493081B1/en not_active Expired - Lifetime
- 2003-01-16 AT AT03734963T patent/ATE487179T1/en not_active IP Right Cessation
- 2003-01-16 DE DE60334784T patent/DE60334784D1/en not_active Expired - Lifetime
- 2003-01-16 CN CN03802115.3A patent/CN101027634B/en not_active Expired - Fee Related
- 2003-01-16 WO PCT/US2003/001579 patent/WO2003065205A2/en not_active Application Discontinuation
- 2003-01-16 KR KR1020037017300A patent/KR100895536B1/en not_active IP Right Cessation
- 2003-01-16 CA CA002473548A patent/CA2473548A1/en not_active Abandoned
- 2003-01-23 TW TW092101470A patent/TWI236595B/en not_active IP Right Cessation
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Also Published As
Publication number | Publication date |
---|---|
TWI236595B (en) | 2005-07-21 |
ATE487179T1 (en) | 2010-11-15 |
CN101027634B (en) | 2015-09-09 |
KR100895536B1 (en) | 2009-04-30 |
DE60334784D1 (en) | 2010-12-16 |
EP1493081A2 (en) | 2005-01-05 |
TW200302417A (en) | 2003-08-01 |
EP1493081B1 (en) | 2010-11-03 |
US7610451B2 (en) | 2009-10-27 |
HK1070704A1 (en) | 2005-06-24 |
US20030145155A1 (en) | 2003-07-31 |
CN101027634A (en) | 2007-08-29 |
WO2003065205A2 (en) | 2003-08-07 |
KR20040017822A (en) | 2004-02-27 |
CA2473548A1 (en) | 2003-08-07 |
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