WO2003065203A2 - Method for recognising a correct command entry address, when command words of different lengths are used - Google Patents

Method for recognising a correct command entry address, when command words of different lengths are used Download PDF

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Publication number
WO2003065203A2
WO2003065203A2 PCT/DE2003/000218 DE0300218W WO03065203A2 WO 2003065203 A2 WO2003065203 A2 WO 2003065203A2 DE 0300218 W DE0300218 W DE 0300218W WO 03065203 A2 WO03065203 A2 WO 03065203A2
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WO
WIPO (PCT)
Prior art keywords
command
start bit
bit
different lengths
entry address
Prior art date
Application number
PCT/DE2003/000218
Other languages
German (de)
French (fr)
Other versions
WO2003065203A3 (en
Inventor
Gerd Dirscherl
Michael Smola
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2003065203A2 publication Critical patent/WO2003065203A2/en
Publication of WO2003065203A3 publication Critical patent/WO2003065203A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification

Definitions

  • the invention is therefore based on the object of providing a method for recognizing correct command entry addresses, even if different long command words are used.
  • an embodiment is symbolically shown a normal long, ie 32 bit long command word (B).
  • the lowest bit which is identified by “a” and corresponds to the first bit, is a start bit, which in this case is designed as "0".
  • the 17th bit is the start bit of the second Half of the instruction value, which is identified by "a , w .
  • A) represents a half-length instruction word. This also has a start bit at the first position, which is also identified by” a "and has the value" 1 ".
  • the second start bit (b) is checked. If it has the value "0 "the entry has been made correctly. If an illegal entry is made in the middle of the normal word, namely the 17th bit, the second start bit (a ⁇ ) is read with the value "0". When the second start bit (b ') is checked, the value "1" immediately recognizes that this is not a correct entry address and reading of the second half of the command word can be prevented.
  • long commands can easily be distinguished from half-length commands and simple means prevent the middle of a long command word from being entered in an unauthorized manner and an unauthorized command, namely the second half of the command word, being read.
  • the method described means that only 16 bits are available for 16-bit command words and only 30 for 32-bit command words.
  • start bits for two different command word lengths described above, more than two different command word lengths can be provided.
  • the number of "start bits" in which the length is coded can then be adjusted if necessary.

Abstract

The invention relates to a method for recognising a correct command entry address, according to which each command word has a predetermined start bit code, which indicates the length of said word.

Description

Beschreibung description
Verfahren zum Erkennen einer korrekten Befehls-Einsprung-Method for recognizing correct command entry
Adresse bei Verwendung unterschiedlich langer BefehlsworteAddress when using command words of different lengths
Die Erfindung betrifft ein Verfahren zum Unterscheiden einer korrekten Befehls-Einsprung-Adresse bei Verwendung unterschiedlich langer Befehlsworte gemäß Patentanspruch 1. Werden für den Befehlscode eines Prozessors unterschiedlich lange Befehlsworte verwendet, so ist es möglich, daß der Programmzähler nicht auf die Einsprungsadresse eines Befehlswortes zeigt. Werden beispielsweise Befehlsworte normaler Länge und solche mit halber Länge der normallangen Befehlsworte verwendet, so ist es möglich, daß der Adreßzähler auf die Mitte, daß heißt auf die zweite Worthälfte eines normallangen Befehlswortes den Adreßzeiger richtet. Somit kann das Befehlswort nicht korrekt ausgelesen werden. Ein solches unkorrektes Einspringen in die Mitte eines Befehlswortes wurde gemäß dem intern vorliegenden Stand der Technik bisher geduldet, da man davon ausgeht .Dabei wird eine Folge von fehlerhaften Befehlen ausgeführt bis sich der Befehlszähler wieder mit dem Befehlsstrom synchronisiert.The invention relates to a method for differentiating a correct command entry address when using command words of different lengths according to claim 1. If command words of different lengths are used for the command code of a processor, it is possible that the program counter does not point to the entry address of a command word. If, for example, command words of normal length and those with half the length of the normal-length command words are used, it is possible for the address counter to point the address pointer to the middle, that is to say to the second half of a normal-length command word. This means that the command word cannot be read out correctly. Such an incorrect entry into the middle of a command word has previously been tolerated in accordance with the internally available state of the art, since one assumes that a sequence of incorrect commands is carried out until the command counter is synchronized again with the command stream.
Der Erfindung liegt somit die Aufgabe zugrunde ein Verfahren zur Erkennung korrekter Befehls-Einsprung-Adressen vorzusehen, auch wenn unterschiedliche lange Befehlsworte verwendet sind.The invention is therefore based on the object of providing a method for recognizing correct command entry addresses, even if different long command words are used.
Diese Aufgabe wird erfindungsgemäß mit den in Patentanspruch 1 angegebenen Maßnahmen gelöst. Dadurch, daß bei Verwendung unterschiedlich langer Befehlsworte, jedes Befehlswort eine für die Länge des Befehlswortes entsprechende vorbestimmte Startbitcodierung (A) aufweist, sind unterschiedlich lange Befehlsworte leicht unterscheidbar.Diese Codierung weist zu- sätzlich den Vorteil auf, daß jeder Befehl implizit die Befehlslänge enthält. Gesonderte Befehle, um diese Information bereitzustellen erübrigen sich damit.This object is achieved with the measures specified in claim 1. The fact that when using command words of different lengths, each command word has a predetermined start bit coding (A) corresponding to the length of the command word, command words of different lengths can be easily distinguished. added the advantage that each command implicitly contains the command length. There is no need for separate commands to provide this information.
Weitere vorteilhafte Ausgestaltungen sind in den Unteransprüchen angegeben, wodurch ein Einspringen in die Mitte eines langen Befehlswortes leicht erkennbar wird.Further advantageous refinements are specified in the subclaims, as a result of which a step into the middle of a long command word can be easily recognized.
Nachfolgend wird die Erfindung unter Erläuterung eines Aus- führungsbeispiels unter Bezugnahme auf die Zeichnung näher erläutert .The invention is explained in more detail below with the explanation of an exemplary embodiment with reference to the drawing.
In der Figur ist ein Ausführungsbeispiel ein normal langes, d.h. 32 Bit langes Befehlswort (B) symbolisch dargestellt. Dabei steht an der Stelle des niedrigsten Bits, das mit „a" gekennzeichnet ist und dem ersten Bit erspricht, ein Start- bit, das in diesem Fall als "0" ausgebildet ist. Beim 17. Bit handelt es sich um das Startbit der zweiten Befehlsworthälfte, das mit „a,w gekennzeichnet ist. Mit A) ein halblanges Befehlswort dargestellt. Dieses weist an der ersten Stelle ebenfalls ein Startbit auf, das ebenfalls mit „a" gekennzeichnet ist und den Wert "1" aufweist.In the figure, an embodiment is symbolically shown a normal long, ie 32 bit long command word (B). The lowest bit, which is identified by "a" and corresponds to the first bit, is a start bit, which in this case is designed as "0". The 17th bit is the start bit of the second Half of the instruction value, which is identified by "a , w . A) represents a half-length instruction word. This also has a start bit at the first position, which is also identified by" a "and has the value" 1 ".
Zu Beginn eines jeden Befehlswortes kann somit leicht beim Einsprung auf dieser Adresse überprüft werden, welchen Wert das Startbit hat und ob es sich um ein halblanges oder normal langes Befehlswort handelt.At the beginning of each command word, it is easy to check the value of the start bit when entering this address and whether it is a half-length or normal length command word.
Wird nach dem „Einsprung" zu einem langen Befehlswort durch Überprüfung des ersten Bits (a,a') erkannt, daß es sich um ein normal langes Befehlswort handelt, wird das zweite Start- bit (b) überprüft. Weist dieses den Wert „0" auf ist der Einsprung korrekt erfolgt . Wird unerlaubter Weise in die Befehlswortmitte des normal langen Befehlswortes eingesprungen, nämlich zum 17. Bit, so wird das zweite Startbit (aλ), entsprechend mit dem Wert "0" gelesen. Bei der Überprüfung des zweiten Startbits (b')wird am Wert „1" somit sofort erkannt, daß es sich hierbei um keine korrekte Einsprungsadresse handelt und ein Lesen der zweiten Befehlsworthälfte ist unterbindbar.If after the "jump" to a long command word by checking the first bit (a, a ') it is recognized that it is a normal long command word, the second start bit (b) is checked. If it has the value "0 "the entry has been made correctly. If an illegal entry is made in the middle of the normal word, namely the 17th bit, the second start bit (a λ ) is read with the value "0". When the second start bit (b ') is checked, the value "1" immediately recognizes that this is not a correct entry address and reading of the second half of the command word can be prevented.
Auf die angegebene Weise sind lange von halblangen Befehlen leicht unterscheidbar und es ist mit einfachen Mitteln verhindert, daß in unerlaubter Weise in die Mitte eines langen Befehlswortes eingesprungen wird und ein nicht zugelassener Befehl, nämlich die zweite Befehlsworthälfte, gelesen wird. Für den Befehlscode bedeutet das beschriebene verfahren, daß bei 16 Bit Befehlsworten nur 15 Bit und bei 32 Bit Befehlsworten nur 30 zur Verfügung stehen.In the specified manner, long commands can easily be distinguished from half-length commands and simple means prevent the middle of a long command word from being entered in an unauthorized manner and an unauthorized command, namely the second half of the command word, being read. For the command code, the method described means that only 16 bits are available for 16-bit command words and only 30 for 32-bit command words.
Entsprechend der zuvor beschriebenen Codierung der „Start- bits" für zwei unterschiedliche Befehlswortlängen, können mehr als zwei unterschiedliche Befehlswortlängen vorgesehen sein. Die Anzahl der „Startbits" in denen die Länge kodiert ist ist dann ggf. anzupassen. According to the coding of the "start bits" for two different command word lengths described above, more than two different command word lengths can be provided. The number of "start bits" in which the length is coded can then be adjusted if necessary.
BezugszeichenlisteLIST OF REFERENCE NUMBERS
a erstes Startbit b zweites Startbit a drittes Starbit viertes Startbit a first start bit b second start bit a third star bit fourth start bit

Claims

Patentansprüche claims
1. Verfahren zum Erkennen einer korrekten Befehls- Einsprungadresse, bei Verwendung unterschiedlich langer Befehlsworte, bei dem jedes Befehlswort eine für die Länge des Befehlswortes entsprechende vorbestimmte Startbitcodierung (a) aufweist.1. A method for recognizing a correct command entry address when using command words of different lengths, in which each command word has a predetermined start bit coding (a) corresponding to the length of the command word.
2. Verfahren nach Anspruch 1, bei dem am Beginn eines langen Befehlswortes nach einem ersten Startbit (a) ein zweites Startbit (b) folgt .2. The method according to claim 1, wherein a second start bit (b) follows at the beginning of a long command word after a first start bit (a).
3. Verfahren nach Anspruch 2, bei dem eine zweite Hälfte des langen Befehlswortes mit einem dritten Startbit (a') beginnt, das mit dem ersten Startbit (a) übereinstimmt.3. The method of claim 2, wherein a second half of the long command word begins with a third start bit (a ') that matches the first start bit (a).
4. Verfahren nach Anspruch 3, bei dem dem dritten Startbit (aλ) ein viertes Starbit (bx) folgt, das zum zweiten Startbit einen komplementären Wert aufweist. 4. The method of claim 3, wherein the third start bit (a λ ) is followed by a fourth star bit (b x ), which has a complementary value to the second start bit.
PCT/DE2003/000218 2002-02-01 2003-01-27 Method for recognising a correct command entry address, when command words of different lengths are used WO2003065203A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10204038.9 2002-02-01
DE2002104038 DE10204038B4 (en) 2002-02-01 2002-02-01 Method for detecting a correct command entry address when using command words of different lengths

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WO2003065203A2 true WO2003065203A2 (en) 2003-08-07
WO2003065203A3 WO2003065203A3 (en) 2006-01-19

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2452151A (en) * 2007-08-20 2009-02-25 Sunplus Technology Co Ltd Using the concatenate bits of an instruction to obtain the length of the instruction in multi-mode processors.

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6049863A (en) * 1996-07-24 2000-04-11 Advanced Micro Devices, Inc. Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor
US6209079B1 (en) * 1996-09-13 2001-03-27 Mitsubishi Denki Kabushiki Kaisha Processor for executing instruction codes of two different lengths and device for inputting the instruction codes

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US588260A (en) * 1897-08-17 Adding-machine
US5881260A (en) * 1998-02-09 1999-03-09 Hewlett-Packard Company Method and apparatus for sequencing and decoding variable length instructions with an instruction boundary marker within each instruction
DE10120522A1 (en) * 2001-04-26 2002-11-07 Infineon Technologies Ag Method for recognizing a correct command entry address when using command words of different lengths

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6049863A (en) * 1996-07-24 2000-04-11 Advanced Micro Devices, Inc. Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor
US6209079B1 (en) * 1996-09-13 2001-03-27 Mitsubishi Denki Kabushiki Kaisha Processor for executing instruction codes of two different lengths and device for inputting the instruction codes

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2452151A (en) * 2007-08-20 2009-02-25 Sunplus Technology Co Ltd Using the concatenate bits of an instruction to obtain the length of the instruction in multi-mode processors.
GB2452151B (en) * 2007-08-20 2012-01-04 Sunplus Technology Co Ltd Instruction length determination device and method using concatenate bits to determine an instruction length in a multi-mode processor

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DE10204038A1 (en) 2003-08-14
DE10204038B4 (en) 2005-03-03
WO2003065203A3 (en) 2006-01-19
TW200302978A (en) 2003-08-16

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