WO2003054928A2 - Porous low-k dielectric interconnect structures - Google Patents

Porous low-k dielectric interconnect structures Download PDF

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Publication number
WO2003054928A2
WO2003054928A2 PCT/US2002/040020 US0240020W WO03054928A2 WO 2003054928 A2 WO2003054928 A2 WO 2003054928A2 US 0240020 W US0240020 W US 0240020W WO 03054928 A2 WO03054928 A2 WO 03054928A2
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WIPO (PCT)
Prior art keywords
porous dielectric
layer
etch stop
dielectric layer
porous
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PCT/US2002/040020
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French (fr)
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WO2003054928A3 (en
Inventor
Ann R. Fornof
Jeffrey C. Hedrick
Kang-Wook Lee
Kelly Malone
Christy S. Tyberg
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International Business Machines Corporation
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Priority claimed from US10/290,682 external-priority patent/US6783862B2/en
Application filed by International Business Machines Corporation filed Critical International Business Machines Corporation
Priority to JP2003555557A priority Critical patent/JP4437922B2/en
Priority to IL16243602A priority patent/IL162436A0/en
Priority to EP02797318A priority patent/EP1529310A4/en
Priority to KR1020047007316A priority patent/KR100581815B1/en
Priority to AU2002361679A priority patent/AU2002361679A1/en
Publication of WO2003054928A2 publication Critical patent/WO2003054928A2/en
Publication of WO2003054928A3 publication Critical patent/WO2003054928A3/en

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    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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Abstract

The present invention provides an electrical interconnect structure on a substrate, includes a first porous dielectric layer with surface region from which a porogen has been removed; and an etch stop layer disposed upon the first porous dielectric layer so that the etch stop layer extends to partially fill pores in the surface region of the first porous dielectric layer from which the porogen has been removed, thus improving adhesion during subsequent processing. Another structure comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one thin, tough, non-porous dielectric layer disposed between at least one of the porous dielectric layers and the etch stop layer. Methods of forming these structures are also provided.

Description

POROUS LOW-K DIELECTRIC INTERCONNECT STRUCTURES
BACKGROUND OF THE INVENTION
Field of the Invention
This invention relates to interconnect structures for high-speed microprocessors, application specific integrated circuits (ASICs), and other high speed IC's. The invention provides ultra low dielectric constant (low-k) interconnect structures having enhanced circuit speed, precise values of conductor resistance, and improved mechanical integrity. The structures of this invention have improved toughness and adhesion along with improved control over the metal line resistance compared to conventional structures. The present invention also provides many additional advantages, which shall become apparent as described below.
Background Art
This application is related to application serial number 09/795,431 , entitled Low-k Dielectric Interconnect Structure Comprised of a Multi Layer of Spin-On Porous Dielectrics, assigned to the same assignee as the present application, and filed on February 28, 2001 , the contents of which are incorporated herein by reference.
Many low-k dielectric plus Cu interconnect structures of the dual damascene type are known. For an example of the dual damascene process wherein SiLK™ may be used as a low-k dielectric material, reference is made to United States Patent No. 6, 383, 920, which is assigned to the same assignee as the present invention, and is incorporated in its entirety by reference, as if fully set forth herein. In order to achieve the necessary reduction in the RC delay in future generations of integrated circuits, porous materials must be used as the dielectric. In addition, due to the 5-20 nanometer pore sizes of porous organic materials, a buried etch stop layer is necessary to give smooth metal line bottoms. These structures must go through several processing steps, including chemical mechanical polishing of the copper (CMP), which create stresses within the dielectric stack that can lead to delamination. The delamination can occur due to poor adhesion at the etch stop to dielectric interfaces.
SUMMARY OF THE INVENTION
It is an object of this invention to provide an ultra low-k dielectric plus Cu interconnect structure of the dual damascene type with precise and uniform control over the Cu conductor resistance with increased adhesion to prevent delaminations during CMP.
It is an object of this invention to provide a porous dielectric stack with a buried RIE stop with improved adhesion that is based on a multilayer of spin coated dielectrics.
It is an object of this invention to provide a low-k dielectric plus copper interconnect structure with precise and uniform control over the copper conductor resistance that is based on a mutlilayer of spin coated dielectric layers, with improved toughness and adhesion and decreased line roughness.
It is another object of this invention to provide methods to make these inventive structures.
In accordance with the invention, an electrical interconnect structure on a substrate, comprises a first porous dielectric layer with surface region from which porogen has been removed; and an etch stop layer disposed upon the first porous dielectric layer so that the etch stop layer extends to partially fill pores in the surface region of the first porous dielectric layer from which the porogen has been removed. The structure may further comprise a second porous dielectric layer disposed upon the first porous dielectric layer. At least one of the first porous dielectric layer and the second porous dielectric layer may be comprised of porous SiLK™ , GX-3p™ , or other porous low k dielectric materials where the porosity is formed from the decomposition of a sacrificial porogen, which may be a component of the material, as provided by the manufacturer. Materials of this kind are described in Patent Cooperation Treaty International Patent Application WO 00/31183 entitled A composition containing a cross-linkable matrix precursor and a porogen, and a porous matrix prepared therefrom of Kenneth, J. Bruza et al. which is assigned to The Dow Chemical Company, the contents of which are incorporated herein in their entirety by reference. The etch stop layer may be comprised of HOSP™, HOSP BESt™, Ensemble™ Etch Stop, Ensemble™ Hard Mask, organo silsesquioxanes, hydrido silsesquioxanes, hydrido-organo silsesquioxanes, siloxanes, or other spin-on material with etch selectivity to the porous dielectric. Materials of this kind are described in United States Patent US 6,218,020 entitled Dielectric films from organohydridosiloxane resins with high organic content of Nigel P. Hacker et al. which is assigned to AlliedSignal Inc., and United States Patent US 6,177,199 entitled Dielectric films from organohydridosiloxane resins with low organic content of Nigel P. Hacker et al. which is assigned to AlliedSignal Inc., the contents of which are incorporated herein in their entirety by reference.
The structure may comprise a plurality of patterned metal conductors formed within a multi layer stack of porous dielectric layers on the substrate, the stack including at least the first porous dielectric layer and the second porous dielectric layer. At least one of the patterned metal conductors, located in the first porous dielectric layer, may be an electrical via. At least one of the patterned metal conductors, located in the second porous dielectric layer, may be a line connected to the via. The structure may include a top hard mask or polish stop layer applied to surface regions of the second dielectric from which porogen has been removed. The hard mask or polish stop layer may be comprised of HOSP™, HOSP BESt™, Ensemble™ Etch Stop, Ensemble™ Hard Mask, organo silsesquioxanes, hydrido silsesquioxanes, hydrido-organo silsesquioxanes, siloxanes, or other spin-on material with etch selectivity to the porous dielectric. Materials of this kind are described in United States Patent US 6,218,020 entitled Dielectric films from organohydridosiloxane resins with high organic content of Nigel P. Hacker et al. which is assigned to AlliedSignal Inc., and United States Patent US 6,177,199 entitled Dielectric films from organohydridosiloxane resins with low organic content of Nigel P. Hacker et al. which is assigned to AlliedSignal Inc., the contents of which are incorporated herein in their entirety by reference.
The invention is also directed to a method of forming an electrical interconnect structure on a substrate, comprising providing a first porous dielectric layer with surface region from which porogen has been removed; and forming an etch stop layer upon the first porous dielectric layer so that the etch stop layer extends to partially fill pores in the surface region of the first porous dielectric layer from which the porogen has been removed. The method may further comprise removing the porogen from the first surface region. The porogen may be removed by heating, and in particular, by baking on a hot surface. The method may further comprise forming a second porous dielectric layer upon the first porous dielectric layer. At least one of the first porous dielectric layer and the second porous dielectπc layer may be comprised of porous SiLK™ , GX-3p™ , or other porous low k dielectric materials where the porosity is formed from the decomposition of a sacrificial porogen. The method may further comprise forming a metal via in the first porous dielectric layer, and forming a metal line in the second porous dielectric layer.
The method may further comprise forming a plurality of patterned metal conductors within a multi layer stack of porous dielectric layers on the substrate, the stack including at least the first porous dielectric layer and the second porous dielectric layer. Additional dielectric layers may be added; and the structure may be completed by adding conductors. A top hard mask or polish stop layer may be applied to surface regions of the second dielectric from which porogen has been removed.
The method may further comprise curing the dielectric layers to render the dielectric layer porous. The dielectric layers in the stack are preferably cured in a single step after sequential application in a single tool. The dielectric application tool may be a spin coating tool containing high temperature hot plate baking chambers, and the curing step may be a furnace curing step conducted at a temperature of from about 300°C to about 500°C for about 15 minutes to about 3 hours.
Thus, the present invention is also directed to a metal wiring plus porous low dielectric constant (low-k) interconnect structure of the dual damascene type with a spin-on buried RIE stop, having improved adhesion. This aspect of the inventive structure is comprised of: A) a multilayer structure of all spin-on dielectric materials which are applied sequentially in a single tool, and then cured in a single furnace cure step, and B) a plurality of patterned metal conductors within the dielectric multilayer structure. The improved adhesion is obtained by partially burning out the porogen near the surface of the via level Porous SiLK prior to applying the etch stop. The structure of the invention has improved adhesion over conventional spin-on buried etch stop structures as a result of the increased surface area of contact between the porous SiLK and etch stop, due to partial burnout of porogen at the surface. The structure of this invention is unique in that it has a layer of Porous SiLK, prior to porogen burnout, with a partial burnout of sacrificial porogens near the surface. This results in the top layer of pores being partially filled with the spin-on buried etch stop, leading to increased adhesion between the dielectric and the etch stop.
In another aspect, The structures of this invention are unique in that they have an ultra-thin non-porous tough dielectric layer between the porous dielectric and the buried etch stop layer. This tough, thin non- porous dielectric layer serves several purposes: it improves toughness, adhesion and reliability of the interconnect structure. To improve adhesion, the non-porous layer is a version of the porous dielectric with a fracture toughness of greater than 0.3 MPa-m1/2 which will covalently bond with the porous dielectric to create one network, while increasing the surface area of contact with the etch stop layer by eliminating pores at the surface. Increased toughness is achieved by incorporating a tough material near the interface in the area of increased stress in the structure. This type of tough material does not have the necessary properties to support the very small pores required by the porous dielectric and therefore generally cannot be used as the matrix for the porous dielectric. Finally, by incorporating a non-porous dielectric layer between the etch stop layer and the porous dielectric layer, smoother lines can be achieved by eliminating pores at the bottom of the etch stop.
Thus, the present invention is directed to a metal wiring plus porous low dielectric constant (low-k) interconnect structure having improved toughness and adhesion, of the dual damascene type with a spin-on buried RIE stop. The inventive structure is comprised of : a) a multilayer of all spin-on dielectric materials which are applied sequentially in a single tool, and then cured in a single furnace cure step, and b) a plurality of patterned metal conductors within the dielectric multilayer. The improved toughness and adhesion is obtained by incorporating a thin, non-porous dielectric layer, which has a fracture toughness greater than 0.3 MPa-m1/2, between the porous dielectric and the etch stop, between the etch stop and the porous dielectric, or both.
In accordance with the invention, a structure, and in particular an electrical interconnect structure, comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one thin, non-porous dielectric layer disposed between at least one of the porous dielectric layers and the etch stop layer. The thin, non-porous dielectric layer may have a thickness of substantially 25 to 150 Angstroms. Preferably, the thin, non-porous dielectric layer has a composition with reactive functionalities identical to those of the porous dielectric layers and in particular a composition, which forms a covalent bond with the composition of the porous dielectric layers. The thin, non-porous dielectric layer may be comprised of a material selected from the group consisting of SiLK ™, GX-3™ , or other low k dielectric materials that exhibit fracture toughness values greater than 0.3 MPa-m \ preferably greater than 0.35 MPa-rn72, and will covalently bond to the porous dielectric layer. Materials of this kind are described in Patent Cooperation Treaty International Patent Application WO 00/40637 entitled Low Dielectric Constant Polymers Having Good Adhesion and Toughness and Articles Made With Such Polymers of Edward O. Shaffer II et al. which is assigned to The Dow Chemical Company. At least one of the porous dielectric layers is comprised of a material selected from the group consisting of porous SiLK ™, GX-3p™, or other porous low-k dielectric layers. Materials of this kind are described in Patent Cooperation Treaty International Patent Application WO 00/31183 entitled A composition containing a cross-linkable matrix precursor and a porogen, and a porous matrix prepared therefrom of Kenneth, J. Bruza et al. which is assigned to The Dow Chemical Company, the contents of which are incorporated herein in their entirety by reference. It may have a thickness of substantially 600-5000 Angstroms. In general, at least one of the porous dielectric layers has the same chemical composition as another of the porous dielectric layers. At least one of the porous dielectric layers may be of substantially the same thickness as another of the porous dielectric layers and have a thickness of substantially 600-5000 Angstroms.
The etch stop layer may be comprised of HOSP™, HOSP BESt™, Ensemble™ Etch Stop, Ensemble™ Hard Mask, organo silsesquioxanes, hydrido silsesquioxanes, hydrido-organo silsesquioxanes, siloxanes, or other spin-on material with etch selectivity to the porous dielectric. Materials of this kind are described in United States Patent US 6,218,020 entitled Dielectric films from organohydridosiloxane resins with high organic content of Nigel P. Hacker et al. which is assigned to AlliedSignal Inc., and United States Patent US 6,177,199 entitled Dielectric films from organohydridosiloxane resins with low organic content of Nigel P. Hacker et al. which is assigned to AlliedSignal Inc., the contents of which are incorporated herein in their entirety by reference. It may have a thickness of substantially 200 - 600 Angstroms.
The structure may further comprise a plurality of patterned metal conductors formed within a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers. At least one of the patterned metal conductors may be an electrical via or a line connected to the via.
The invention is also directed to a method for forming an electrical interconnect structure on a substrate, the structure having a plurality of porous dielectric layers disposed on the substrate and an etch stop layer between a first of the dielectric layers and a second of the dielectric layers. The method comprises forming at least one thin, non-porous dielectric layer between at least one of the porous dielectric layers and the etch stop layer. The method further comprising forming a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers, and forming a plurality of patterned metal conductors within the multilayer stack. At least one of the patterned metal conductors may be formed as an electrical via. At least one of the patterned metal conductors may be a line connected to the via.
The multilayer dielectric stack is applied to the substrate by spin coating. The method may further comprise baking the individual layers of the multilayer dielectric stack on a hot plate. The method may further comprise curing the multilayer dielectric stack. The curing of the multilayer dielectric stack may be accomplished using a furnace in a single step.
The method also includes applying a multilayer dielectric stack to the substrate and baking the multilayer dielectric stack, so that the applying and baking are accomplished in a single spin-coat tool. Additional dielectric layers may be added, and dual damascene conductors may be formed in the additional layers.
Other and further objects, advantages and features of the present invention will be understood by reference to the following specification in conjunction with the annexed drawings, wherein like parts have been given like numbers.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1A and Figure 1B are schematic drawings of a prior art porous dielectric with a buried etch stop before RIE and metallization.
Figures 2A through 2D are schematic drawings of the inventive structures with partial burnout of porogen near the surface of the via level before RIE and metallization.
Figure 3 is a schematic drawing of the inventive structures after RIE and metallization.
Figure 4 is a process flow chart of a method for make the structure of Figure 2.
Figure 5 is a schematic drawing of a porous dielectric with a buried etch stop in accordance with the prior art, before RIE and metallization.
Figure 6A is a schematic drawing of a structure in accordance with the invention with a thin layer below the etch stop before RIE and metallization.
Figure 6B is a schematic drawing of a structure in accordance with the invention with a thin layer above the etch stop before RIE and metallization. Figure 6C is a schematic drawing of a structure in accordance with the invention with a thin layer both above and below the etch stop before RIE and metallization.
Figure 7 is a schematic drawing of a structure in accordance with the invention, after RIE and metallization.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
A Structure In Accordance With The Invention
Referring to Figure 1A and Figure 1 B, a silicon substrate 1 has thereon a first porous low k dielectric layer 5, an etch stop layer 7, and a second porous low k dielectric layer 9. Furnace curing may produce a weak interface between porous low k dielectric layer 5, an etch stop layer 7. This is because during this type of processing of porous SiLK™ (a Dow Company proprietary organic ultra low-k interlayer dielectric resin) with a spin-on buried etch stop layer, the porogen is not burnt out of the porous SiLK™ until both the line and via levels of porous SiLK™ along with the buried etch stop have been applied. Full burnout of the porogen in the via level of porous SiLK™ would require a 40 minute hold at 430°C for all the porogen to diffuse out of the porous SiLK™ film, greatly increasing the raw process time. Therefore, the bottom layer of porous SiLK™ is hot plate baked for 1-3 minutes to partially react the porous SiLK™ film without removing the porogen. This bake cycle can lead to a weak interface between the via level porous SiLK™ and the etch stop if there is a high near surface concentration of porogen that is removed during the final cure.
Referring to Figure 2A through Figure 2D, and as described in more detail below, in accordance with the invention, improved adhesion is obtained by partially burning out the porogen near the surface of the via level Porous SiLK™ prior to applying the etch stop (Figure 2B). By increasing the time or temperature of the intermediate hot plate bake, the porogen near the surface can be partially removed. This results in a higher surface area of contact between the via level Porous SiLK™ and etch stop resulting in improved adhesion.
Referring to Figure 3, substrate 1 may contain electronic devices such as, for example, transistors and an array of conductor elements. An interconnect structure 3, in accordance with the invention is formed on substrate 1. Structure 3 is comprised of a first porous SiLK™ dielectric layer 5, having a thickness of 600 - 5000 Angstroms which may have a highly aromatic structure, that is thermally stable to approximately 425°C, with a glass transition temperature above 450°C, and a low dielectric constant of 2.2. The thickness may be selected within this broad range in accordance with the technology being implemented.
A HOSP™ (a spin-on hybrid organic-inorganic low k dielectric) etch stop layer 7 of thickness 200-600 Angstroms (more preferably 200-300 Angstroms), and having the atomic composition that gives etch selectivity of at least 10:1 to the porous dielectric, is disposed on the first porous SiLK™ layer 5. This material has good adhesion to the non-porous SiLK™ and thermal stability to a temperature of greater than 425°C, and a low dielectric constant of 3.2 or less.
A second porous SiLK™ dielectric layer 9, having a of thickness of 600 - 5000 Angstroms, and being a highly aromatic structure which is thermally stable to approximately 425°C, with a glass transition temperature above 450°C, and a low dielectric constant of 2.2, is disposed on the etch stop layer 7. A top hard mask or polish stop layer 11 may be applied on surface regions of the second porous dielectric layer 9, from which porogen has been removed in the manner set forth herein.
Patterned metal lines 13 and vias 14, formed by a dual damascene process, are formed within the dielectric multilayer structure described above.
Other low-k spin coated materials may be used for the dielectric layers 5 and 9 and for the etch stop layer 7. Examples of other materials that could be used for layers 5 and 9 are GX-3p™, or other porous low k dielectric materials where the porosity is formed as a result of the decomposition of a sacrificial porogen. Examples of other materials that could be used for layer 7 are HOSP BESt™, Ensemble™ Etch Stop, Ensemble™ Hard Mask, .organo silsesquioxanes, hydrido silsesquioxanes, hydrido-organo silsesquioxanes, siloxanes, or other spin-on material with etch selectivity to the porous dielectric.
A Method In Accordance With The Invention
A. The stack of dielectric layers is formed
The interconnect structure 3 in accordance with the invention may be applied to the substrate 1 or wafer by spin on techniques. The first layer 5 in the structure 3 is preferably a porous low k dielectric with a desired thickness of 600-5000 Angstroms. This low k dielectric is applied by a spin-on technique with a spin speed of 1000-4000 rpm. After spinning, the substrate 1 is hot plate baked to remove the solvent of the low k dielectric at 100-350°C, for 30-120 seconds. The substrate 1 is then placed on an oxygen-controlled hot plate and cured at 400°C for 5-10 minutes, or 400°C for 2 minutes, followed by 430°C for 2 minutes. These times and temperatures are sufficient to render the film of the first layer 5 insoluble, and to remove porogen at the surface of the film.
After cooling, a buried etch stop layer 7, with a desired thickness of 200-300 Angstroms, is applied by a spin-on technique with a spin speed of 1000-4000 rpm. The wafer is then placed on a hot plate and baked at 100-300°C for 30-120 seconds to remove the solvent. It is then placed on a 300 - 400°C oxygen controlled hot plate for 1-2 minutes. This time promotes sufficient crosslinking to render the film insoluble. After cooling, the top dielectric layer 9 is applied in a similar fashion. Layer 9 is the same composition as layer 5 with a slightly greater thickness. The desired thickness of the top low k dielectric layer 9 is 600-5000 Angstroms. This layer is spun at 1000-4000 rpm, and the wafer is then hot plate baked at 100-350°C, for 30-120 seconds, to remove the solvent.
B. The stack of dielectric layers is cured in a single cure step
At this point the wafer is placed in a furnace in an atmosphere of pure N2 (with very low O2 and H2O concentrations), and cured at 350- 450°C for 15 minutes to 3 hours to crosslink the stack and burn out the sacrificial porogen. The sacrificial porogen thermally degrades and then diffuses out of the dielectric stack through the free volume of the dielectric layers and etch stop layer, leaving the porous dielectric layers in the stack.
C. Additional dielectric layers are added for dual damascene patterning (distributed hard mask)
As noted above, the dual damascene process described in, for example, United States Patent No. 6, 383,920 may be used when adding additional layers. D. The dual damascene structure of Fig. 3 is completed (using standard process steps)
This is standard dual damascene BEOL (back end of line) processing which includes forming a via in the bottom dielectric, and a trench in the top dielectric of the multilayer of spun-on dielectrics; filling the trench with at least a conductive metal; planarizing the conductive metal stopping on the hard mask or polish stop layer.
Example 1 : A Porous SiLK™/HOSP™/Porous SiLK™ Structure is Produced
A. The stack of dielectric layers is formed as in Figure 1.
Figure imgf000017_0001
Figure imgf000018_0001
Table I - Process Flow Chart
Referring to Table I above, and Figure 4, at 20 a 200mm diameter silicon wafer substrate is treated with adhesion promoter by applying a solution of AP 4000 to the wafer followed by spinning at 3000 rpm for 30 seconds. At 22, the wafer is then placed on a hot plate at 185°C for 90 seconds for a first hot plate bake.
After cooling, the wafer to room temperature, at 24, the first layer of low k dielectric (porous SiLK ™) is applied (layer 5, Figure 1 ). The SiLK ™ solution is placed on the wafer and the wafer is spun at 3000 rpm for 30 seconds. After spinning, the wafer is placed on a 150°C hot plate for 2 minute to partially dry the solvent, at 26 (second hot plate bake). It is then transferred to a 400°C hot plate for 5 minutes. As an alternative, at 26, the wafer is placed on a 150°C hot plate for 2 minute to partially dry the solvent, transferred to a 400°C hot plate for 2 minutes, and then transferred to a 430°C hot plate for 2 minutes. The time and temperature schedule should be sufficient to render the film insoluble and burnout sacrificial porogen near the surface.
The wafer is then allowed to cool and was returned to the spinner. At 28, a solution of HOSP™, diluted to achieve a film thickness of 250A° at a spin speed of 3000 rpm, is applied to the wafer and spun at 3000 rpm for 30 seconds, to produce etch stop layer 7 (Figure 1 ). After spinning, at 30 (third hot plate bake), the wafer is placed on a hot plate at 150°C for 2 minute to partially dry the solvent. It is then moved to a 400°C hot plate for 2 minutes to partially crosslink the film. This time and temperature is sufficient to render the film insoluble. At 32, a second layer of Porous SiLK is applied in a manner similar to the first layer to produce layer 9 (Fig. 1 ). Porous SiLK is applied to the wafer and the wafer is spun at 3000 rpm for 30 seconds. At 34 (fourth hot plate bake), the wafer is placed on a 150°C hot plate for 2 minute to partially dry the solvent.
At 36, the wafer is placed in an oxygen controlled oven and cured at 430°C for 80 minutes to cure the SiLK and etch stop layers, promote crosslinking between the layers, and thermally degrade and burn out the porogen.
C. Additional dielectric layers are added for dual damascene patterning (distributed hard mask)
The cured wafer containing the layers described above was placed in a PE CVD reactor and a 350 Angstrom layer of Silicon Nitride was deposited at 350°C, and then a 1500 Angstrom layer of SiO2 was deposited at 350°C. This completes the formation of the dielectric multilayer of the Example 1.
D. The dual damascene structure of Fig. 3 is completed
Lithography and etching processes are then performed as described in, for example, United States Patent No. 6.383,920. The dual damascene structure is then completed using standard process methods known in the industry (the etched trench and via opening are filled with a liner and then with Cu, and the Cu is planarized by CMP).
During the final CMP process, the silicon dioxide layer deposited in step C is removed, leaving the structure shown in Figure 3. Advantageously, all of the dielectric layers (5, 7, and 9) shown in Figure 3 have been cured in a single furnace cure step after sequential application of the three layers in a single spin/apply tool.
Another Structure In Accordance With The Invention
Referring to Figure 5, a structure on which, for example, an integrated circuit may be fabricated includes a substrate 101 , a first porous dielectric layer 105, and a second porous dielectric layer 113. As is well known in the art, an etch stop layer 109 may be disposed between dielectric layers 105 and 113. Substrate 101 is generally comprised of silicon, and may include a dielectric, a metal region, an adhesion promoter, or any combination thereof. Substrate 101 may be a semiconductor wafer of a different composition, porous dielectric layers 105 and 113 may be comprised of a material sold under the trademark porous SiLK M) (a Dow Chemical Company proprietary organic ultra low-k interlayer dielectric resin). Other possible materials include GX-3p™ , or other porous low k dielectric materials.
Referring to Figure 6A, in accordance with the invention, a non- porous dielectric layer with a fracture toughness greater than 0.3 MPa-m1 2 107 is provided between porous dielectric layer 105 and etch stop layer 109. Dielectric layer 107 may have a thickness of approximately 25-150 Angstroms. Dielectric layer 107 has increased fracture toughness compared to porous SiLK™ due to a decreased network density, as described in above mentioned International Patent Application WO 00/40637. This structure has the same reactive functionalities as a porous SiLK™ layer and can crosslink with a porous SiLK™ layer. Layer 107 preferably has a highly aromatic structure, which is thermally stable to approximately 425°C with a glass transition temperature above 430°C, and a low dielectric constant of approximately 2.65. The structure of Figure 6B is similar to that of Figure 6A, but does not include layer 107. Instead, the structure of Figure 6B includes a layer 111 disposed between etch stop layer 109 and porous dielectric layer 113. Layer 111 may be, in all respects except location, similar to layer 107.
Referring to Figure 6C, the structure shown therein includes both a layer 107 and a layer 111 , having the characteristics described above.
A more specific example is described below with respect to Figure
7.
EXAMPLE 2: Substrate / Porous SiLK™ / thin SiLK™ layer/ HOSP BESt™ / thin SiLK™ layer / Porous SiLK™
Figure 7 schematically illustrates another specific embodiment of the invention. A substrate 101 may contain transistors and an array of conductor elements. An interconnect structure 103, in accordance with the invention, is disposed on the substrate 101. Structure 103 is comprised of a first porous SiLK™ dielectric layer 105, having a thickness of 600-5000 Angstroms and having a highly aromatic structure which is thermally stable to approximately 425°C, with a glass transition temperature above approximately 450°C, and a low dielectric constant of approximately 2.2.
A thin non porous SiLK TM layer 107, having a fracture toughness greater than 0.30 MPa-m1 2 and having a thickness of approximately 25- 150 Angstroms, is disposed on the first porous SiLK layer 105. As noted above, layer 107 has increased fracture toughness compared to porous SiLK due to a decreased network density. This structure has the same reactive functionalities as the porous SiLK layer 105 and can crosslink with porous SiLK layer 105. Layer 107 is a highly aromatic structure, which is thermally stable to approximately 425°C with a glass transition temperature above approximately 430°C, and a low dielectric constant of approximately 2.65.
A HOSP BESt™ (a spin-on hybrid organic-inorganic low-k dielectric) etch stop layer 109 of thickness 200 - 600 Angstroms (more preferably 200-300 Angstroms), and having an atomic composition that gives etch selectivity of at least 10:1 to the porous dielectric is disposed on the thin SiLK™ layer 107. The material of layer 109 has good adhesion to SiLK™, thermal stability to approximately 450°C, and a low dielectric constant of approximately 2.7.
A thin non-porous SiLK layer 111 , having a fracture toughness greater than 0.30 MPa-m1/2 and having a thickness of approximately 25- 150 Angstrom, is disposed on the etch stop layer 109. Layer 111 has increased fracture toughness compared to porous SiLK™ due to a decreased network density. Layer 111 has the same reactive functionalities as a porous SiLK™ layer and can crosslink with a porous SiLK™ layer. Layer 111 has a highly aromatic structure, which is thermally stable to approximately 425°C with a glass transition temperature above approximately 430°C, and a low dielectric constant of approximately 2.65.
A second porous SiLK dielectric layer 113 having a thickness of approximately 600-5000 Angstroms, and having a highly aromatic structure which is thermally stable to approximately 425°C with a glass transition temperature above approximately 450°C, and a low dielectric constant of approximately 2.2, is disposed on the thin SiLK™ layer 111.
Patterned metal lines 117 and vias 118, formed by a dual damascene process, such as that described in the above referenced United States Patent No. 6, 383, 920, are formed within the dielectric multilayer of Figure 7.
As is known by one skilled in the art, other low-k spin coated dielectric materials may be used for dielectric layers 105 and 113, for etch stop layer 109, and for the thin toughening layers 107 and 111.
General Method for Fabricating Another Structure of the Invention
Steps in the General Method
A. The stack of dielectric layers is applied
The inventive interconnect structure 103 is applied to the substrate 101 by spin on techniques. The first layer 105 in the structure is preferably a porous low k dielectric with a desired thickness of 600- 5000A°. This low k dielectric is applied by a spin-on technique with a spin speed of 1000-4000 rpm. After spinning the low k dielectric is hot plate baked to dry the solvent and render the film insoluble at 200-400°C for 1-2 minutes. This time and temperature is sufficient to render the film insoluble without eliminating the porogen. After cooling a thin layer of a dielectric having a fracture toughness greater than 0.30 MPa-m1/2107 capable of crosslinking with the bottom porous dielectric layer, and having a thickness of approximately 25-150 Angstroms is applied by spin coating. After spinning the dielectric is hot plate baked to dry the solvent and render the film insoluble at 200-400°C for 1-2 minutes. After cooling, the buried RIE etch stop layer 109, with a desired thickness of approximately 200-600 Angstroms, is applied by a spin-on technique with a spin speed of 1000-4000 rpm. The etch stop layer is hot plate baked to dry the solvent and render the film insoluble at 200-400°C for 1-2 minutes. This time promotes sufficient crosslinking to render the film insoluble. After cooling, a second thin layer of a dielectric having a fracture toughness greater than 0.30 MPa-m1/2111 capable of crosslinking with the top porous dielectric layer, and having a thickness of 25-150 Angstroms is applied by spin coating. After spinning the low k dielectric is hot plate baked to dry the solvent and render the film insoluble at 200-400°C for 1 -2 minutes. After cooling, the top dielectric layer 113 is applied in a similar fashion. Layer 113 may be of the same composition as layer 105, but with a slightly higher thickness. The desired thickness of the top low k dielectric layer 113 is approximately 600 - 5000 Angstroms. This layer is spun at 1000 - 4000 rpm, then hot plate baked at approximately 100-400°C for approximately 30-120 seconds to partially dry the solvent.
B. The stack of dielectric layers is cured in a single cure step
At this point the wafer is placed in a furnace in an atmosphere of pure N2 (with very low O2 and H2O concentrations) and cured at approximately 300-450°C for approximately 15 minutes to 3 hours to crosslink the stack and burn out the sacrificial porogen.
C. Additional dielectric layers are added for dual damascene patterning (distributed hard mask)
For this step and the next, reference is made to the above mentioned United States Patent No. 6, 383, 920.
D. The dual damascene structure of Fig. 7 is completed (using standard process steps)
A Method for Making the Preferred Embodiment (Porous SiLK™ / Thin SiLK™ layer/ HOSP BESt™ / Thin SiLK™ layer/ Porous SiLK™) A. The stack of dielectric layers is applied
The first layer of low k dielectric porous SiLK™ is applied to the substrate by spin coating (layer 105, Figure 7). After spinning, the wafer is placed on a 250°C hot plate for 2 minute to partially dry the solvent. It is then transferred to a 310°C hot plate for 2 minutes and a 400°C hot plate for 2 minutes. This time and temperature are sufficient to render the film insoluble.
A solution of SiLK™ , such as, for example, the composition specified in International Patent Application WO 00/40637 on page 17, Table II, resin I diluted to achieve a film thickness of about 100A° at a spin speed of 3000 rpm, is applied to the wafer and spun at 3000 rpm for 30 seconds, to produce layer 107 (Fig. 7). After spinning, the wafer is placed on a hot plate at 310°C for 1 minute to dry the solvent. It is then moved to a 400°C hot plate for 2 minutes to partially crosslink the film. This time and temperature are sufficient to render the film insoluble.
A solution of HOSP BESt™ diluted to achieve a film thickness of
250 Angstroms at a spin speed of 3000 rpm, is applied to the wafer and spun at 3000 rpm for 30 seconds, to produce layer 109 (Fig. 7). After spinning, the wafer is placed on a hot plate at 310°C for 2 minutes to dry and partially crosslink the film. This time and temperature is sufficient to render the film insoluble.
The solution of SiLK™ diluted to achieve a film thickness of 100 Angstroms, at a spin speed of 3000 rpm, is applied to the wafer and spun at 3000 rpm for 30 seconds to produce layer 111 (Fig. 7). After spinning, the wafer is placed on a hot plate at 310°C for 1 minute to partially dry the solvent. It is then moved to a 400°C hot plate for 2 minutes to partially crosslink the film. This time and temperature are sufficient to render the film insoluble. The wafer is then allowed to cool and is returned to the spinner.
The second layer of porous SiLK™ is applied in a manner similar to that for the first layer to produce layer 113 (Fig. 7). Porous SiLK™ is applied to the wafer and the wafer is spun at 3000 rpm for 30 seconds. The wafer is placed on a 250°C hot plate for 2 minute to partially dry the solvent.
At this point the wafer is placed in an oxygen controlled oven and cured at 430°C for 80 minutes to cure the SiLK and etch stop layers, to promote crosslinking between the layers, and to thermally degrade and burn out the porogen.
C. Additional dielectric layers are added for dual damascene patterning (distributed hard mask)
The cured wafer containing the layers described above was placed in a PE CVD reactor and a 350 Angstrom layer of silicon nitride 115 was deposited at 350°C, and then a 1500 Angstrom layer of SiO2 was deposited at 350°C. This completes the formation of the dielectric multilayer of Example 2.
D. The dual damascene structure of Fig. 7 is completed
Lithography and etching processes are then performed as described in the above referenced United States Patent No. 6, 383, 920. The dual damascene structure is then completed using standard process methods known in the industry (the etched trench and via opening are filled with a liner and then with copper, and the copper is planarized by CMP).
During the final CMP process, silicon dioxide layer deposited in step C is removed, leaving the structure shown in Fig. 7. It should be noted that all the dielectric layers (105, 107, 109, 111 and 113) shown in Fig. 7 have been cured in a single furnace cure step after sequential application of the 5 layers in a single spin/apply tool.
Thus, The structure of the invention has improved adhesion over conventional buried etch stop structures because the non-porous layer will increase the surface area of contact with the etch stop layer by eliminating pores at the surface, and form covalent bonds with the porous dielectric to create one network.
Increased toughness is achieved by incorporating a tough material near the interface in the area of increased stress in the dielectric stack. This type of tough material may not have the necessary properties to support very small pores required by the porous dielectric and therefore cannot be used as the matrix for the porous dielectric.
Incorporating a non-porous dielectric layer between the etch stop and the porous dielectric layer allows for smoother lines by eliminating pores at the bottom of the etch stop. Specifically, in a dual damascene process, the last step of the RIE process that includes the cap open step, may result in the line bottoms etching through the etch stop and landing on the top of the dielectric that is directly below the etch stop. Incorporation of the thin dense dielectric between the via level porous dielectric and the etch stop will result in decreased line roughness compared with the conventional structure that has the porous dielectric directly below the etch stop. While we have shown and described several embodiments in accordance with our invention, it is to be clearly understood that the same are susceptible to numerous changes apparent to one skilled in the art. Therefore, we do not wish to be limited to the details shown and described but intend to show all changes and modifications, which come within the scope of the appended claims.

Claims

WHAT IS CLAIMED IS:
1. An electrical interconnect structure on a substrate, comprising: a first porous dielectric layer with surface region from which porogen has been removed; and an etch stop layer disposed upon said first porous dielectric layer so that said etch stop layer extends to partially fill pores in the surface region of said first porous dielectric layer from which said porogen has been removed.
2. The electrical interconnect structure of claim 1 , further comprising a second porous dielectric layer disposed upon said etch stop layer.
3. The electrical interconnect structure of claim 2, wherein at least one of the first porous dielectric layer and the second porous dielectric layer is comprised of an organic dielectric material.
4. The electrical interconnect structure of claim 2, wherein at least one of the first porous dielectric layer and the second porous dielectric layer is comprised of a material wherein the porosity is formed as a result of decomposition of a sacrificial porogen.
5. The electrical interconnect structure of claim 2, wherein the first porous dielectric layer has a thickness in the range of substantially 600 - 5000 Angstroms.
6. The electrical interconnect structure of claim 2, wherein the second porous dielectric layer has a thickness in the range of substantially 600-5000 Angstroms.
7. The electrical interconnect structure of claim 2, wherein said etch stop layer is comprised of a spin-on material with etch selectivity to the porous dielectric layers.
8. The electrical interconnect structure of claim 2, wherein said etch stop layer is comprised of a material selected from the group consisting of organo silsesquioxanes, hydrido silsesquioxanes, hydrido- organo silsesquioxanes, and siloxanes.
9. The electrical interconnect structure of claim 2, wherein the etch stop layer has a thickness of substantially 200 - 600 Angstroms.
10. The electrical interconnect structure of claim 2, further comprising a plurality of patterned metal conductors formed within a multi layer stack of porous dielectric layers on the substrate, said stack including at least the first porous dielectric layer, the etch stop layer, and the second porous dielectric layer.
11. The electrical interconnect structure of claim 9, wherein at least one of the patterned metal conductors is an electrical via.
12. The electrical interconnect structure of claim 11 , wherein at least one of the patterned metal conductors is a line connected to said via.
13. The electrical interconnect structure of claim 2, wherein the first porous dielectric layer has a metal via formed therein.
14. The electrical interconnect structure of claim 2, wherein the second porous dielectric layer has a metal line formed therein.
15. The electrical interconnect structure of claim 2, further comprising a hardmask layer disposed upon said second porous dielectric layer so that said hardmask layer extends to partially fill pores in a surface region of said second porous dielectric layer from which said porogen has been removed.
16. The electrical interconnect structure of claim 15, wherein said hard mask layer is comprised of a material with etch selectivity to the porous dielectric.
17. The electrical interconnect structure of claim 15, wherein said hard mask layer is comprised of a material selected from the group consisting of Etch Stop, Hard Mask, organo silsesquioxanes, hydrido silsesquioxanes, hydrido-organo silsesquioxanes, and siloxanes.
18. The electrical interconnect structure of claim 1 , wherein said first and second porous dielectrics layers are comprised of organic dielectrics, and said etch stop layer is one of an inorganic low-k dielectric material and an inorganic/organic hybrid material.
19. The electrical interconnect structure of claim 2, wherein said inorganic low-k dielectric etch stop layer is porous.
20. The electrical interconnect structure of claim 1 , wherein the first porous dielectric layer is comprised of an organic dielectric material.
21. The electrical interconnect structure of claim 1 , wherein the first porous dielectric layer is comprised of a material wherein the porosity is formed as a result of decomposition of a sacrificial porogen.
22. The electrical interconnect structure of claim 1 , wherein the first porous dielectric layer has a thickness in the range of substantially 600 - 5000 Angstroms.
23. The electrical interconnect structure of claim 1 , wherein said etch stop layer is comprised of a spin-on material with etch selectivity to the porous dielectric of the dielectric layer.
24. The electrical interconnect structure of claim 1 , wherein said etch stop layer is comprised of a material selected from the group consisting of Etch Stop, Hard Mask, organo silsesquioxanes, hydrido silsesquioxanes, hydrido-organo silsesquioxanes, and siloxanes.
25. The electrical interconnect structure of claim 1 , wherein the etch stop layer has a thickness of substantially 200 - 600 Angstroms.
26. The interconnect structure of Claim 1 , wherein said substrate is a semiconductor wafers having an adhesion promoter layer formed thereon.
27. A method of forming an electrical interconnect structure on a substrate, comprising: providing a first porous dielectric layer with surface region from which porogen has been removed; and forming an etch stop layer upon said first porous dielectric layer so that said etch stop layer extends to partially fill pores in the surface region of said first porous dielectric layer from which said porogen has been removed.
28. The method of claim 27, further comprising removing the porogen from the first surface region.
29. The method of claim 28, wherein the porogen is removed by heating.
30. The method of claim 27, wherein the porogen is removed by baking in a hot plate bake chamber.
31. The method of claim 27, further comprising forming a second porous dielectric layer upon said etch stop layer.
32. The method of claim 31 , wherein at least one of the first porous dielectric layer and the second porous dielectric layer is comprised of an organic dielectric material.
33. The method of claim 31 , further comprising forming porosity in at least one of the first porous dielectric layer and the second porous dielectric layer by decomposition of a sacrificial porogen initially in said layers.
34. The method of claim 34, wherein the first porous dielectric layer has a thickness in the range of substantially 600 - 5000 Angstroms.
35. The method of claim 30, wherein the second porous dielectric layer has a thickness in the range of substantially 600 - 5000 Angstroms.
36. The method of claim 30, wherein said etch stop layer is comprised of a material with etch selectivity to the porous dielectric layers.
37. The method of claim 30, wherein said etch stop layer is selected from the group consisting of Etch Stop, Hard Mask, organo silsesquioxanes, hydrido silsesquioxanes, hydrido-organo silsesquioxanes, and siloxanes.
38. The method of claim 30, wherein the etch stop layer has a thickness of substantially 200 - 600 Angstroms.
39. The method of claim 30, further comprising forming a metal via in the first porous dielectric layer.
40. The method of claim 30, further comprising forming a metal line in the second porous dielectric layer.
41. The method of claim 30, further comprising forming a plurality of patterned metal conductors within a multi layer stack of porous dielectric layers on the substrate, said stack including at least the first porous dielectric layer, said etch stop layer, and the second porous dielectric layer.
42. The method of claim 41 , further comprising:
adding additional dielectric layers; and
completing the structure by adding conductors.
43. The method of claim 42, further comprising curing the dielectric layers to render the dielectric layer porous.
44. The method of claim 43, wherein said first porous dielectric, said etch stop, and said second porous dielectric layers in the stack are cured in a single step.
45. The method of Claim 44, wherein said curing is a furnace curing step conducted at a temperature of from about 300°C to about 450°C for about 15 minutes to about 3 hours.
46. The method of claim 43, wherein remaining porogen from the first and second porous dielectric layers is removed during said curing step.
47. The method of claim 43, wherein the remaining porogen degrades to low molecular weight compounds and diffuses out of the layer through free volume of the first and second porous dielectric layers and the buried etch stop layer during the curing step.
48. The method of claim 43, wherein the dielectric layers in the stack are cured after sequential application in a single tool.
49. The method of claim 48, wherein the tool is a spin coating tool containing high temperature hot plate baking chambers.
50. The method of claim 41 , further comprising: forming at least one of the patterned metal conductors as an electrical via.
51. The method of claim 50, further comprising forming at least one of the patterned metal conductors as a line connected to said via.
52. The method of claim 30, further comprising forming a hardmask layer upon said second porous dielectric layer so that said hardmask layer extends to partially fill pores in surface regions of said second porous dielectric layer from which said porogen has been removed.
53. The method of claim 30, wherein said hardmask layer is a chemical mechanical polishing polish stop layer.
54. The method of claim 52, further comprising forming porosity at least one of the first porous dielectric layer and the second porous dielectric layer by decomposition of a sacrificial porogen
55. The method of claim 52, wherein said hardmask layer is comprised of a spin-on material with etch selectivity to the porous dielectric layers.
56. The method of claim 51 , wherein said hardmask layer is comprised of a material selected from the group consisting of Etch Stop, Hard Mask, organo silsesquioxanes, hydrido silsesquioxanes, hydrido- organo silsesquioxanes, and siloxanes.
57. The method of claim 51 , wherein at least one of the first porous dielectric layer and the second porous dielectric layer is comprised of an organic dielectric material.
58. The method of claim 52, wherein the first porous dielectric layer, the etch stop layer, the second porous dielectric layer and the hard mask layers are cured in a single step.
59. The method of claim 58, wherein said curing is a furnace curing step conducted at a temperature of from about 300°C to about 450°C for about 15 minutes to about 3 hours.
60. The method of claim 58, wherein remaining porogen degrades to low molecular weight compounds and diffuses out of the structure through free volume of the first and second porous dielectric layers, the buried etch stop layer and the hard mask layer during the curing step.
61. The method of claim 51 , wherein the hard mask layer has a thickness of substantially 300 to substantially 1000 Angstroms.
62. The method of claim 27, further comprising forming a polish stop layer upon said second porous dielectric layer so that said polish stop layer extends to partially fill pores in surface regions of said second porous dielectric layer from which said porogen has been removed.
63. The method of claim 27, wherein the first porous dielectric layer is comprised of an organic dielectric material.
64. The method claim 27, further comprising forming porosity in the first porous dielectric layer by decomposition the porogen.
65. The method of claim 27, wherein the first porous dielectric layer has a thickness in the range of substantially 600 - 5000 Angstroms.
66. The method of claim 27, wherein said etch stop layer is comprised of a spin-on material with etch selectivity to the porous dielectric layers.
67. The method of claim 27, wherein said etch stop layer is comprised of a material selected from the group consisting of Etch Stop, Hard Mask, organo silsesquioxanes, hydrido silsesquioxanes, hydrido- organo silsesquioxanes, and siloxanes.
68. The method of claim 27, wherein the etch stop layer has a thickness of substantially 200 to substantially 600 Angstroms.
69. A structure comprising: a substrate; a plurality of porous dielectric layers disposed on said substrate; an etch stop layer disposed between a first of said dielectric layers and a second of said dielectric layers; and at least one thin, non-porous dielectric layer disposed between at least one of said porous dielectric layers and said etch stop layer.
70. The structure of claim 69, wherein a thin, non-porous dielectric layer is disposed between only one of said porous dielectric layers and said etch stop layer.
71. The structure of claim 69, wherein a thin, non-porous dielectric layer is disposed between each of two of said porous dielectric layers and said etch stop layer.
72. The structure of claim 69, wherein a thin, non-porous dielectric layer is disposed above one of said porous dielectric layers and below said etch stop layer.
73. The structure of claim 69, wherein a thin, non-porous dielectric layer is disposed below one of said porous dielectric layers and above said etch stop layer.
74. The structure of claim 69, wherein said thin, non-porous dielectric layer has a thickness of substantially 25 to 150 Angstroms.
75. The structure of claim 69, wherein said thin, non-porous dielectric layer has a composition with reactive functionalities identical to those of said porous dielectric layers.
76. The structure of claim 69, wherein said thin, non-porous dielectric layer has a composition, which forms a covalent bond with the composition of said porous dielectric layers.
77. The structure of claim 69, wherein said thin, non-porous dielectric layer is comprised of a material selected from the group consisting of low k dielectric materials that exhibit fracture toughness values greater than 0.30 MPa-m1/2 and will covalently bond to the porous dielectric layer.
78. The structure of claim 69, wherein at least one of said porous dielectric layers has a thickness of substantially 600-5000 Angstroms.
79. The structure of claim 69, wherein said at least one of said porous dielectric layers has the same chemical composition as another of said porous dielectric layers.
80. The structure of claim 69, wherein said at least one of said porous dielectric layers has substantially the same thickness as another of said porous dielectric layers.
81. The structure of claim 69, wherein said etch stop layer has a chemical composition comprising silicon, carbon, oxygen, and hydrogen.
82. The structure of claim 69, wherein said etch stop layer is selected from the group consisting of Etch Stop, Hard Mask, organo silsesquioxanes, hydrido silsesquioxanes, hydrido-organo silsesquioxanes, siloxanes, and other spin-on material with etch selectivity to the porous dielectric.
83. The structure of claim 69, wherein said etch stop layer has a thickness of substantially 200-600 Angstroms.
84. The structure of claim 69, further comprising a plurality of patterned metal conductors formed within a multilayer stack of porous dielectric layers on the substrate, said stack including said plurality of porous dielectric layers.
85. The structure of claim 84, wherein at least one of the patterned metal conductors is an electrical via.
86. The structure of claim 84, wherein at least one of the patterned metal conductors is a line connected to said via.
87. The structure of claim 84, wherein the first porous dielectric layer has a metal via formed therein
88. The structure of claim 84, wherein the second porous dielectric layer has a metal line formed therein.
89. A method for forming an electrical interconnect structure on a substrate, the structure having a plurality of porous dielectric layers disposed on said substrate and an etch stop layer between a first of said dielectric layers and a second of said dielectric layers comprising: forming at least one thin, non-porous dielectric layer between at least one of said porous dielectric layers and said etch stop layer.
90. The method of claim 89, wherein a thin, non-porous dielectric layer is formed between only one of said porous dielectric layers and said etch stop layer.
91. The method of claim 89, wherein a thin, non-porous dielectric layer is formed between each of two of said porous dielectric layers and said etch stop layer.
92. The method of claim 89, wherein a thin, non-porous dielectric layer is formed above one of said porous dielectric layers and below said etch stop layer.
93. The method of claim 88, wherein a thin, non-porous dielectric layer is formed below one of said porous dielectric layers and above said etch stop layer.
94. The method of claim 89, wherein said thin, non-porous dielectric layer is formed to a thickness of substantially 25 to 150
Angstroms.
95. The method structure of claim 89, wherein said thin, non- porous dielectric layer is formed to have a composition with reactive functionalities identical to those of said porous dielectric layers.
96. The method of claim 89, wherein said thin, non-porous dielectric layer is formed to have a composition which forms a covalent bond with the composition of said porous dielectric layers.
97. The method of claim 89, wherein said thin, non-porous dielectric layer is comprised of a material selected from the group consisting of low k dielectric materials that exhibit fracture toughness values greater than 0.3 MPa-m1/2 and covalently bond to the porous dielectric layer.
98. The structure of claim 89, wherein at least one of said porous dielectric layers is comprised of a material selected from the group consisting of porous low k dielectric materials.
99. The method of claim 89, wherein at least one of said porous dielectric layers is formed to have a thickness of substantially 600-5000 Angstroms.
100. The method of claim 89, wherein said at least one of said porous dielectric layers is formed with the same chemical composition as another of said porous dielectric layers.
101. The method of claim 89, wherein said at least one of said porous dielectric layers is formed to be of substantially the same thickness as another of said porous dielectric layers.
102. The method of claim 96, wherein said etch stop layer is selected from the group consisting of Etch Stop, Hard Mask, organo silsesquioxanes, hydrido silsesquioxanes, hydrido-organo silsesquioxanes, siloxanes, and other spin-on material with etch selectivity to the porous dielectric.
103. The method of claim 89, wherein said etch stop layer has a chemical composition comprising silicon, oxygen, carbon, and hydrogen.
104. The method of claim 89, wherein said etch stop layer is formed to have a thickness of substantially 200-600 Angstroms.
105. The method of claim 89, further comprising forming a multilayer stack of porous dielectric layers on the substrate, said stack including said plurality of porous dielectric layers, and forming a plurality of patterned metal conductors within said multilayer stack.
106. The method of claim 105, wherein at least one of the patterned metal conductors is formed as an electrical via.
107. The method of claim 105, wherein at least one of the patterned metal conductors is a line connected to said via.
108. The method of claim 105, wherein the first porous dielectric layer has a metal via formed therein.
109. The method of claim 105, wherein the second porous dielectric layer has a metal line formed therein.
110. The method of claim 109, wherein said multilayer dielectric stack is applied to said substrate by spin coating.
111. The method of claim 105, further comprising baking each layer of multilayer dielectric stack.
112. The method of claim 111 , wherein said baking is accomplished on a hot plate.
113. The method of claim 105, further comprising curing said multilayer dielectric stack in a single cure step.
114. The method of claim 105, wherein said curing of the multilayer stack is a furnace curing process that is carried out at a temperature from about 300°C to about 450°C for a time period of from about 15 minutes to about 3 hours.
115. The method of claim 114, wherein said curing step crosslinks the films and burns out sacrificial porogen from the porous dielectric layers.
116. The method of claim 89, further comprising applying a multilayer dielectric stack to said substrate and baking said multilayer dielectric stack, said applying and baking being accomplished in a single spin-coat tool.
117. The method of claim 89, further comprising adding additional dielectric layers, and forming dual damascene conductors in said additional layers.
118. The method of claim 89, wherein said substrate is a dielectric, a metal region, an adhesion promoter, a semiconductor wafer or any combination thereof.
PCT/US2002/040020 2001-12-13 2002-12-13 Porous low-k dielectric interconnect structures WO2003054928A2 (en)

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EP02797318A EP1529310A4 (en) 2001-12-13 2002-12-13 Porous low-k dielectric interconnect structures
KR1020047007316A KR100581815B1 (en) 2001-12-13 2002-12-13 Porous low-k dielectric interconnect structures
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US10/290,682 US6783862B2 (en) 2001-12-13 2002-11-08 Toughness, adhesion and smooth metal lines of porous low k dielectric interconnect structures
US10/290,616 US6933586B2 (en) 2001-12-13 2002-11-08 Porous low-k dielectric interconnects with improved adhesion produced by partial burnout of surface porogens
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