WO2003048981A2 - Improving integrated circuit performance and reliability using a patterned bump layout on a power grid - Google Patents

Improving integrated circuit performance and reliability using a patterned bump layout on a power grid Download PDF

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Publication number
WO2003048981A2
WO2003048981A2 PCT/US2002/037643 US0237643W WO03048981A2 WO 2003048981 A2 WO2003048981 A2 WO 2003048981A2 US 0237643 W US0237643 W US 0237643W WO 03048981 A2 WO03048981 A2 WO 03048981A2
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WO
WIPO (PCT)
Prior art keywords
bump
metal bar
integrated circuit
metal layer
angle
Prior art date
Application number
PCT/US2002/037643
Other languages
French (fr)
Other versions
WO2003048981A3 (en
Inventor
Sudhakar Bobba
Tyler J. Thorp
Dean Liu
Pradeep R. Trivedi
Original Assignee
Sun Microsystems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/997,437 external-priority patent/US6473883B1/en
Priority claimed from US09/997,523 external-priority patent/US6541873B1/en
Priority claimed from US09/997,844 external-priority patent/US6617699B2/en
Priority claimed from US09/997,438 external-priority patent/US6762505B2/en
Priority claimed from US09/997,452 external-priority patent/US6577002B1/en
Priority claimed from US09/997,471 external-priority patent/US6495926B1/en
Application filed by Sun Microsystems, Inc. filed Critical Sun Microsystems, Inc.
Priority to AU2002352885A priority Critical patent/AU2002352885A1/en
Priority to JP2003550104A priority patent/JP2005512315A/en
Publication of WO2003048981A2 publication Critical patent/WO2003048981A2/en
Priority to GB0410834A priority patent/GB2398903A/en
Publication of WO2003048981A3 publication Critical patent/WO2003048981A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Definitions

  • a typical computer system includes at least a microprocessor and some form of memory.
  • the microprocessor has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions necessary for the operation and use of the computer system.
  • Figure 1 shows a typical computer circuit board (10) having a microprocessor (12), memory (14), integrated circuits (16) that have various functionalities, and communication paths (18), i.e., buses and wires, that are necessary for the transfer of data among the aforementioned components on the circuit board (10).
  • Integrated circuits (16) and microprocessors (12), such as the ones shown in Figure 1 are electrically connected, i.e., "mounted,” to the circuit board (10) via chip packages.
  • a chip package houses semiconductor devices in strong, thermally stable, hermetically-sealed environments that provide a semiconductor device, e.g., an integrated circuit, with electronic connectivity to circuitry external to the semiconductor device.
  • FIG 2 shows a typical chip package assembly.
  • an integrated circuit (20) is mounted onto a chip package (22), where an active side (24) of the integrated circuit (20) is electrically interfaced to the chip package (22).
  • the integrated circuit (20) has bumps (26) on bond pads (also known in the art as “landing pads") (not shown) formed on the active side (24) of the integrated circuit (20), where the bumps (26) are used as electrical and mechanical connectors.
  • the integrated circuit (20) is inverted and bonded to the chip package (22) by means of the bumps (26).
  • Various materials, such as conductive polymers and metals are commonly used to form the bumps (26) on the integrated circuit (20).
  • the bumps (26) on the integrated circuit (20) serve as electrical pathways between components within the integrated circuit (20) and the chip package (22).
  • an arrangement of conductive pathways and metal layers form a means by which components in the integrated circuit (20) operatively connect to the bumps (26) located on an exterior region of the integrated circuit (20).
  • Figure 3 a shows a side view of the integrated circuit (20).
  • the integrated circuit (20) has several metal layers, M1-M8, surrounded by some dielectric material (28), e.g., silicon dioxide.
  • Vias (30) are essentially holes within the dielectric material (28) that have been doped with metal ions. Further, those skilled in the art will understand that although Figure 2 shows only eight metal layers and a particular amount of vias, integrated circuits may have any number of metal layers and/or vias.
  • FIG. 20 transmit and receive signals and power via the metal layers, M1-M8, and the vias (30). Signals that need to be transmitted/received to/from components external to the integrated circuit (20) are propagated through the metal layers, M1-M8, and vias (30) to the top metal layer, M8.
  • the top metal layer also referred to and known as "power grid", M8, then transmits/receives signals and power to/from the bumps (26) located on the active side (24) of the integrated circuit (20). With respect to the power and energy needed by the integrated circuit (20), power is delivered to the integrated circuit (20) from external sources through the bumps (26) and metal layers, M1-M8.
  • the top metal layer, M8, on the integrated circuit (20) acts as an interface between the integrated circuit (20) and the external sources/signals of power.
  • Figure 3b shows a top view of the integrated circuit (20) shown in
  • the top metal layer, M8, as shown in Figure 3b, has a number of parallel regions, otherwise known as "metal bars.” These metal bars alternate between bars connected to V DD and regions connected to Vss- Such a configuration helps reduce electromagnetic interference.
  • the top metal layer, M8, is configured such that it is orthogonal with the metal layer below, M7, as shown in Figure 3b. Further, bumps (26) on the top metal layer, M8, are arranged in a non-uniform fashion with some areas of the top metal layer, M8, having larger numbers of bumps (26) than other areas.
  • a method for designing an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises defining a desired angle, where the desired angle represents an angle formed between a line from a reference bump to a first bump and a line from the reference bump to a second bump, where the first and second bumps reside on the first metal bar, and where the reference bump resides on the second metal bar; and using the desired angle to position the first metal bar, the first bump, and the second bump on the integrated circuit.
  • a method for designing an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises defining a desired angle, where the desired angle represents an angle formed between a line from a reference bump to a first bump and a line from the reference bump to a second bump, where the first and second bumps reside on the first metal bar, and wherein the reference bump resides on the second metal bar; and using the desired angle to position the first metal bar and the second metal bar on the integrated circuit.
  • a computer system comprises a processor, a memory, and instructions, residing in the memory and executable on the processor, for determining a value of an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump.
  • a computer-readable medium having instructions therein executable by processing, where the instructions are for: inputting a desired metal layer property; and determining a value of an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump based on the desired metal layer property, where the reference bump resides on a first metal bar, and where the first and second bumps reside on a second metal bar.
  • an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second metal bar, where the first bump and the second bump are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 60 degrees.
  • an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second metal bar, where the first metal bar and the second metal bar are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 60 degrees.
  • a patterned bump array for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first bump, the second bump, and the reference bump are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 60 degrees.
  • a bump layout for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first metal bar and the second metal bar are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 60 degrees.
  • an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second metal bar, where the first bump and the second bump are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 90 degrees.
  • an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second metal bar, where the first metal bar and the second metal bar are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 90 degrees.
  • a patterned bump array for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first bump, the second bump, and the reference bump are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 90 degrees.
  • a bump layout for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first metal bar and the second metal bar are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 90 degrees.
  • an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second metal bar, where the first bump and the second bump are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 120 degrees.
  • an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second metal bar, where the first metal bar and the second metal bar are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 120 degrees.
  • a patterned bump array for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first bump, the second bump, and the reference bump are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 120 degrees.
  • a bump layout for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first metal bar and the second metal bar are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 120 degrees.
  • an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second metal bar, where the first bump and the second bump are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 150 degrees.
  • an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second metal bar, where the first metal bar and the second metal bar are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 150 degrees.
  • a patterned bump array for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first bump, the second bump, and the reference bump are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 150 degrees.
  • a bump layout for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first metal bar and the second metal bar are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 150 degrees.
  • an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second -metal bar, where the first bump and the second bump are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 180 degrees.
  • an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second metal bar, where the first metal bar and the second metal bar are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 180 degrees.
  • a patterned bump array for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first bump, the second bump, and the reference bump are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 180 degrees.
  • a bump layout for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first metal bar and the second metal bar are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 180 degrees.
  • Figure 1 shows a typical circuit board.
  • Figure 2 shows a typical chip package assembly.
  • Figure 3 a shows a side view of a typical integrated circuit.
  • Figure 3b shows a top view of a typical integrated circuit.
  • Figure 4 shows a section of a top metal layer of an integrated circuit in accordance with an embodiment of the present invention.
  • Figure 5a shows a section of a top metal layer of an integrated circuit in accordance with an embodiment of the present invention.
  • Figure 5b shows a top metal layer of an integrated circuit in accordance with the embodiment shown in Figure 5 a.
  • Figure 6a shows a section of a top metal layer of an integrated circuit in accordance with another embodiment of the present invention.
  • Figure 6b shows a top metal layer of an integrated circuit in accordance with the embodiment shown in Figure 6a.
  • Figure 7a shows a section of a top metal layer of an integrated circuit in accordance with another embodiment of the present invention.
  • Figure 7b shows a top metal layer of an integrated circuit in accordance with the embodiment shown in Figure 7a.
  • Figure 8a shows a section of a top metal layer of an integrated circuit in accordance with another embodiment of the present invention.
  • Figure 8b shows a section of a top metal layer of an integrated circuit in accordance with another embodiment of the present invention.
  • Figure 8c shows a top metal layer of an integrated circuit in accordance with the embodiments shown in Figures 8a and 8b.
  • Figure 9a shows a section of a top metal layer of an integrated circuit in accordance with another embodiment of the present invention.
  • Figure 9b shows a top metal layer of an integrated circuit in accordance with the embodiment shown in Figure 9a.
  • Figure 10 shows a computer system in accordance with an embodiment of the present invention.
  • Embodiments of the present invention relate to a method and apparatus for improving integrated circuit performance by using a patterned bump layout on a power grid of the integrated circuit.
  • Embodiments of the present invention further relate to a method and apparatus for improving bump placement on a top metal layer of an integrated circuit.
  • Embodiments of the present invention further relate to a method and apparatus for creating a bump array on a top metal layer of an integrated circuit.
  • Embodiments of the present invention further relate to a computer system that determines an optimal bump pattern given a set of conditions.
  • Embodiments of the present invention further relate to a computer-readable medium having instructions for determining an optimal placement of bumps on an integrated circuit.
  • Embodiments of the present invention also relate to a method for positioning a maximum number of bumps on a power grid of an integrated circuit.
  • Figure 4 shows a section (50) of a top metal layer of an exemplary integrated circuit in accordance with an embodiment of the present invention.
  • the section (50) has a first metal bar (52) connected to V DD> i-e., power, and a second metal bar (54) connected to V ss , i.e., ground.
  • the first metal bar (52) has two bumps (56a, 56b) and the second metal bar (54) has one bump (also referred to as "reference bump") (56c).
  • first metal bar (52) is connected to power and the second metal bar (54) is connected to ground
  • first metal bar (52) may be connected to ground and the second metal bar (54) may be connected to power
  • a separation between the bumps (56a, 56b) on the first metal bar (52) is defined as a vertical pitch, Vp.
  • a distance between the first bump (56a) on the first metal bar (52) and the bump (56c) on the second metal bar (54) is defined as an across pitch, A P .
  • a P also denotes the distance between the second bump (56b) on the first metal bar (52) and the bump (56c) on the second metal bar (54).
  • An angle ⁇ represents the angle between the two across pitches.
  • Varying angle ⁇ can be done by repositioning the bumps (56a, 56b) on the first metal bar (52) and or adjusting the spacing between the first and second metal bars (52, 54).
  • properties of a top metal layer may be changed as desired.
  • Properties dependent on the angle ⁇ include, but are not limited to, metal layer resistance, metal layer capacitance, metal layer inductance, metal layer electrical performance, overall bump current flow, bump population, bump electromagnetivity, signal track positioning, and integration characteristics.
  • bumps on a top metal layer may be patterned such that the arrangement of bumps results in repetitive groups of bumps having an angle ⁇ between across pitches in a group of bumps as shown in Figure 4.
  • the properties between a group of bumps as shown in Figure 4 may be replicated across part or all of a top metal layer in order to create a particular bump array.
  • Figure 5a shows a section of a top metal layer of an integrated circuit in accordance with an embodiment of the present invention.
  • angle ⁇ is set at 60 degrees.
  • angle ⁇ is equal to 60 degrees
  • a maximum packing of bumps on a top metal layer may be achieved, as shown below with reference to Figure 5b. This may be beneficial when the current flow capabilities for individual bumps are relatively low.
  • the number of bumps on a top metal layer is maximized, and thus, the overall amount of current that can flow from an integrated circuit to a chip package is accordingly maximized.
  • angle ⁇ is equal to 60 degrees, the distances between the bumps (56a, 56b, 56c) are all equal.
  • angle ⁇ is set at 60 degrees in Figure 5 a
  • similar bump and metal layer properties and structures may be realized using any angle ⁇ up to 75 degrees.
  • this embodiment will be referred to as the "60 degrees" embodiment, those skilled in the art will understand that this embodiment applies to embodiments having any angle ⁇ up to 75 degrees.
  • Figure 5b shows a top metal layer (60) of an integrated circuit in accordance with the embodiment shown in Figure 5a.
  • the three bump structure shown in Figure 5a is repeated across the top metal layer (60) of an integrated circuit.
  • Figure 6a shows a section of a top metal layer of an integrated circuit in accordance with an embodiment of the present invention.
  • angle ⁇ is set at 90 degrees. When angle ⁇ is equal to 90 degrees, the first metal bar (52) and second metal bar (54) are spaced closer together than the 60 degrees embodiment shown and discussed above with reference to Figure 5 a.
  • first and second metal bars (52, 54) Due to the first and second metal bars (52, 54) being closer together, there is higher capacitance between the first and second metal bars (52, 54) than there is in the 60 degrees embodiment. Further, also due to the first and second metal bars (52, 54) being spaced closer together, more metal bars can be positioned in a top metal layer than what would be possible in the 60 degrees embodiment. However, because the first and second bumps (56a, 56b) have to be spaced further apart when angle ⁇ is 90 degrees, fewer bumps per metal bar can be positioned on a top metal layer than the 60 degrees embodiment.
  • angle ⁇ is set at 90 degrees in Figure 6a
  • similar bump and metal layer properties and structures may be realized using any angle ⁇ from 76 degrees up to 105 degrees.
  • this embodiment will be referred to as the "90 degrees” embodiment, those skilled in the art will understand that this embodiment applies to embodiments having any angle ⁇ from 76 degrees up to 105 degrees.
  • Figure 6b shows a top metal layer (70) of an integrated circuit in accordance with the embodiment shown in Figure 6a.
  • the three bump structure shown in Figure 6a is repeated across the top metal layer (70) of an integrated circuit.
  • Figure 7a shows a section of a top metal layer of an integrated circuit in accordance with an embodiment of the present invention.
  • angle ⁇ is set at 120 degrees.
  • the first metal bar (52) and second metal bar (54) are virtually touching each other.
  • a minimum amount of spacing (82) between the first and second metal bars (52, 54) is present between the first and second metal bars (52, 54) to ensure that the first and second metal bars (52, 54) do not come into contact with each other.
  • angle ⁇ is set at 120 degrees in Figure 7a
  • similar bump and metal layer properties and structures may be realized using any angle ⁇ from 106 degrees up to 135 degrees.
  • this embodiment will be referred to as the "120 degrees” embodiment, those skilled in the art will understand that this embodiment applies to embodiments having any angle ⁇ from 106 degrees up to 135 degrees.
  • Figure 7b shows a top metal layer (80) of an integrated circuit in accordance with the embodiment shown in Figure 7a.
  • the three bump structure shown in Figure 7a is repeated across the top metal layer (80) of an integrated circuit.
  • Figure 8a shows a section of a top metal layer of an integrated circuit in accordance with an embodiment of the present invention.
  • angle ⁇ is set at 150 degrees.
  • the first and second metal bars (52, 54) are essentially "interlocked.”
  • the first and metal bars (52, 54) are configured, i.e., designed, in a "stair-case” pattern such that there is some finite amount of spacing (92) between the first and second metal bars (52, 54).
  • the bumps (56a, 56b, 56c) are partially aligned.
  • the landing pad size of the bumps (56a, 56b, 56c) may be changed because this embodiment is, to a certain extent, immune to bump placement variations.
  • first and second metal bars (52, 54) may be shortened so as to allow more spacing on the sides of the interlocked structure formed by the first and second metal bars (52, 54). This can be done without affecting the electrical properties among the first metal bar (52), the second metal bar (54), and the bumps (56a, 56b, 56c). By allowing more spacing on the sides of the interlocked structure, there is additional space to route signals and signal tracks. This embodiment may be viewed as a "150 degrees narrow" approach.
  • angle ⁇ is set at 150 degrees in Figures 8a and 8b
  • similar bump and metal layer properties and structures may be realized using any angle ⁇ from 136 degrees up to 165 degrees.
  • embodiments shown in Figures 8a and 8b will collectively be referred to as the "150 degrees" embodiment, those skilled in the art will understand that this embodiment applies to embodiments having any angle ⁇ from 136 degrees up to 165 degrees.
  • Figure 8c shows a top metal layer (90) of an integrated circuit in accordance with the embodiments shown in Figures 8a and 8b.
  • the three bump structure shown in Figures 8a and 8b is repeated across the top metal layer (90) of an integrated circuit.
  • the width of the metal bars is approximately equal to the width of the landing pads of the bumps. Landing pad size is usually part of design rules for a particular power grid. It follows that the minimal allowable spacing between two bumps is twice the size of a landing pad. Depending on the width of a particular metal bar and a width of a particular landing pad, different bump structures may be realized. Further, those skilled in the art will appreciate that for different design rules/constraints, the angles may change. Nonetheless, the principles of the present invention are consistent with embodiments in which this occurs.
  • Figure 9a shows a section of a top metal layer of an integrated circuit in accordance with an embodiment of the present invention.
  • angle ⁇ is set at 180 degrees.
  • the first and second metal bars (52, 54) are "interlocked.”
  • the first and metal bars (52, 54) are configured, i.e., designed, in a "stair-case” pattern such that there is some finite amount of spacing (102) between the first and second metal bars (52, 54).
  • the bumps (56a, 56b, 56c) are aligned.
  • angle ⁇ is set at 180 degrees in Figure 9a
  • similar bump and metal layer properties and structures may be realized using any angle ⁇ greater than or equal to 166 degrees.
  • this embodiment will be referred to as the "180 degrees” embodiment, those skilled in the art will understand that this embodiment applies to embodiments having any angle ⁇ greater than or equal to 166 degrees.
  • Figure 9b shows a top metal layer (100) of an integrated circuit in accordance with the embodiment shown in Figure 9a.
  • the three bump structure shown in Figure 9a is repeated across the top metal layer (100) of an integrated circuit.
  • first metal bar (52) and second metal bar (54) get closer together, similar angles may be achieved by increasing/decreasing spacing between bumps on a particular metal bar.
  • FIG. 10 shows an exemplary computer system (110) in accordance with an embodiment of the present invention.
  • the computer system (110) is capable of determining a value to which angle ⁇ needs to be varied according to various factors provided by a designer and/or computer program.
  • Input parameters (112) to the computer system (110) may include, among other things, a desired capacitance between metal bars, a desired resistance between metal bars, a desired inductance due to metal bars, a desired bump current flow to/from a top metal layer of an integrated circuit, a desired bump population on the top metal layer, and a desired amount of space to be available for signals and/or signal tracks on the top metal layer.
  • the input parameters (112) may include additional information corresponding to particular properties and characteristics of the metal bars and bumps that are going to be used in the design.
  • the input parameters (112) serve as input data to the computer system
  • the computer system (110) via some computer-readable medium, e.g., network path, floppy disk, input file, etc.
  • the computer system (110) then stores the input parameters (112) in memory (not shown) to subsequently determine (via microprocessor functions) a value of angle ⁇ that will most closely achieve the behavior desired by the designer. Thereafter, the computer system (110) the determined ⁇ value (114) via some user-readable medium, e.g., monitor display, network path, etc.
  • the computer system (110) may also determine and output one or more suggested top metal layer designs in accordance with the designer's specifications.
  • a computer-readable medium may be used, where the computer-readable medium has instructions for, among other things, determining a value of an angle between a line from a reference bump to a first bump and a line from a reference bump to a second bump.
  • the determination by the instructions may be dependent on various desired metal layer properties provided by a designer, a computer system, or other software program.
  • Advantages of the present invention may include one or more of the following.
  • a designer is provided with added flexibility in determining a particular bump layout for a top metal layer of an integrated circuit.
  • a bump placement that meets particular electrical needs may be generated.
  • a bump layout of a top metal layer may be patterned to achieve increased efficiency and/or performance.
  • a bump layout of a top metal layer is improved by characterizing particular placements of bumps by an angle, integrated circuit performance may be improved.

Abstract

A method for improving integrated circuit by using a patterned bump layout on a metal layer of the integrated circuit is provided. The method creates various bump structures by varying an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump. By varying the angle, a designer may generate a particular bump structure that meets the needs of a particular design. Further, a particular bump placement may be repeated across all or a portion of the metal layer in order to create a patterned bump layout.

Description

IMPROVING INTEGRATED CIRCUIT PERFORMANCE AND RELIABILITY USING A PATTERNED BUMP LAYOUT ON A POWER GRID
Background of Invention
[0001] A typical computer system includes at least a microprocessor and some form of memory. The microprocessor has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions necessary for the operation and use of the computer system. Figure 1 shows a typical computer circuit board (10) having a microprocessor (12), memory (14), integrated circuits (16) that have various functionalities, and communication paths (18), i.e., buses and wires, that are necessary for the transfer of data among the aforementioned components on the circuit board (10).
[0002] Integrated circuits (16) and microprocessors (12), such as the ones shown in Figure 1, are electrically connected, i.e., "mounted," to the circuit board (10) via chip packages. A chip package houses semiconductor devices in strong, thermally stable, hermetically-sealed environments that provide a semiconductor device, e.g., an integrated circuit, with electronic connectivity to circuitry external to the semiconductor device.
[0003] Figure 2 shows a typical chip package assembly. In Figure 2, an integrated circuit (20) is mounted onto a chip package (22), where an active side (24) of the integrated circuit (20) is electrically interfaced to the chip package (22). Specifically, the integrated circuit (20) has bumps (26) on bond pads (also known in the art as "landing pads") (not shown) formed on the active side (24) of the integrated circuit (20), where the bumps (26) are used as electrical and mechanical connectors. The integrated circuit (20) is inverted and bonded to the chip package (22) by means of the bumps (26). Various materials, such as conductive polymers and metals (referred to as "solder bumps"), are commonly used to form the bumps (26) on the integrated circuit (20).
[0004] As discussed above with reference to Figure 2, the bumps (26) on the integrated circuit (20) serve as electrical pathways between components within the integrated circuit (20) and the chip package (22). Within the integrated circuit (20) itself, an arrangement of conductive pathways and metal layers form a means by which components in the integrated circuit (20) operatively connect to the bumps (26) located on an exterior region of the integrated circuit (20). To this end, Figure 3 a shows a side view of the integrated circuit (20). The integrated circuit (20) has several metal layers, M1-M8, surrounded by some dielectric material (28), e.g., silicon dioxide. The metal layers, M1-M8, are connected to each other by conductive pathways (30) known as "vias." Vias (30) are essentially holes within the dielectric material (28) that have been doped with metal ions. Further, those skilled in the art will understand that although Figure 2 shows only eight metal layers and a particular amount of vias, integrated circuits may have any number of metal layers and/or vias.
[0005] Circuitry (not shown) embedded on a substrate of the integrated circuit
(20) transmit and receive signals and power via the metal layers, M1-M8, and the vias (30). Signals that need to be transmitted/received to/from components external to the integrated circuit (20) are propagated through the metal layers, M1-M8, and vias (30) to the top metal layer, M8. The top metal layer (also referred to and known as "power grid"), M8, then transmits/receives signals and power to/from the bumps (26) located on the active side (24) of the integrated circuit (20). With respect to the power and energy needed by the integrated circuit (20), power is delivered to the integrated circuit (20) from external sources through the bumps (26) and metal layers, M1-M8. The top metal layer, M8, on the integrated circuit (20) acts as an interface between the integrated circuit (20) and the external sources/signals of power. [0006] Figure 3b shows a top view of the integrated circuit (20) shown in
Figure 3 a. The top metal layer, M8, as shown in Figure 3b, has a number of parallel regions, otherwise known as "metal bars." These metal bars alternate between bars connected to VDD and regions connected to Vss- Such a configuration helps reduce electromagnetic interference. The top metal layer, M8, is configured such that it is orthogonal with the metal layer below, M7, as shown in Figure 3b. Further, bumps (26) on the top metal layer, M8, are arranged in a non-uniform fashion with some areas of the top metal layer, M8, having larger numbers of bumps (26) than other areas.
Summary of Invention
[0007] According to one aspect of the present invention, a method for designing an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises defining a desired angle, where the desired angle represents an angle formed between a line from a reference bump to a first bump and a line from the reference bump to a second bump, where the first and second bumps reside on the first metal bar, and where the reference bump resides on the second metal bar; and using the desired angle to position the first metal bar, the first bump, and the second bump on the integrated circuit.
[0008] According to another aspect, a method for designing an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises defining a desired angle, where the desired angle represents an angle formed between a line from a reference bump to a first bump and a line from the reference bump to a second bump, where the first and second bumps reside on the first metal bar, and wherein the reference bump resides on the second metal bar; and using the desired angle to position the first metal bar and the second metal bar on the integrated circuit.
[0009] According to another aspect, a computer system comprises a processor, a memory, and instructions, residing in the memory and executable on the processor, for determining a value of an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump.
[0010] According to another aspect, a computer-readable medium having instructions therein executable by processing, where the instructions are for: inputting a desired metal layer property; and determining a value of an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump based on the desired metal layer property, where the reference bump resides on a first metal bar, and where the first and second bumps reside on a second metal bar.
[0011] According to another aspect, an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second metal bar, where the first bump and the second bump are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 60 degrees.
[0012] According to another aspect, an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second metal bar, where the first metal bar and the second metal bar are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 60 degrees.
[0013] According to another aspect, a patterned bump array for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first bump, the second bump, and the reference bump are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 60 degrees.
[0014] According to another aspect, a bump layout for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first metal bar and the second metal bar are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 60 degrees.
[0015] According to another aspect, an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second metal bar, where the first bump and the second bump are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 90 degrees.
[0016] According to another aspect, an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second metal bar, where the first metal bar and the second metal bar are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 90 degrees.
[0017] According to another aspect, a patterned bump array for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first bump, the second bump, and the reference bump are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 90 degrees.
[0018] According to another aspect, a bump layout for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first metal bar and the second metal bar are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 90 degrees.
[0019] According to another aspect, an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second metal bar, where the first bump and the second bump are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 120 degrees.
[0020] According to another aspect, an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second metal bar, where the first metal bar and the second metal bar are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 120 degrees.
[0021] According to another aspect, a patterned bump array for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first bump, the second bump, and the reference bump are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 120 degrees.
[0022] According to another aspect, a bump layout for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first metal bar and the second metal bar are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 120 degrees.
[0023] According to another aspect, an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second metal bar, where the first bump and the second bump are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 150 degrees.
[0024] According to another aspect, an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second metal bar, where the first metal bar and the second metal bar are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 150 degrees.
[0025] According to another aspect, a patterned bump array for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first bump, the second bump, and the reference bump are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 150 degrees.
[0026] According to another aspect, a bump layout for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first metal bar and the second metal bar are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 150 degrees.
[0027] According to another aspect, an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second -metal bar, where the first bump and the second bump are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 180 degrees.
[0028] According to another aspect, an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second metal bar, where the first metal bar and the second metal bar are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 180 degrees.
[0029] According to another aspect, a patterned bump array for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first bump, the second bump, and the reference bump are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 180 degrees.
[0030] According to another aspect, a bump layout for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first metal bar and the second metal bar are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 180 degrees.
[0031] Other aspects and advantages of the invention will be apparent from the following description and the appended claims.
Brief Description of Drawings
[0032] Figure 1 shows a typical circuit board.
[0033] Figure 2 shows a typical chip package assembly.
[0034] Figure 3 a shows a side view of a typical integrated circuit.
[0035] Figure 3b shows a top view of a typical integrated circuit.
[0036] Figure 4 shows a section of a top metal layer of an integrated circuit in accordance with an embodiment of the present invention.
[0037] Figure 5a shows a section of a top metal layer of an integrated circuit in accordance with an embodiment of the present invention.
[0038] Figure 5b shows a top metal layer of an integrated circuit in accordance with the embodiment shown in Figure 5 a.
[0039] Figure 6a shows a section of a top metal layer of an integrated circuit in accordance with another embodiment of the present invention.
[0040] Figure 6b shows a top metal layer of an integrated circuit in accordance with the embodiment shown in Figure 6a. [0041] Figure 7a shows a section of a top metal layer of an integrated circuit in accordance with another embodiment of the present invention.
[0042] Figure 7b shows a top metal layer of an integrated circuit in accordance with the embodiment shown in Figure 7a.
[0043] Figure 8a shows a section of a top metal layer of an integrated circuit in accordance with another embodiment of the present invention.
[0044] Figure 8b shows a section of a top metal layer of an integrated circuit in accordance with another embodiment of the present invention.
[0045] Figure 8c shows a top metal layer of an integrated circuit in accordance with the embodiments shown in Figures 8a and 8b.
[0046] Figure 9a shows a section of a top metal layer of an integrated circuit in accordance with another embodiment of the present invention.
[0047] Figure 9b shows a top metal layer of an integrated circuit in accordance with the embodiment shown in Figure 9a.
[0048] Figure 10 shows a computer system in accordance with an embodiment of the present invention.
Detailed Description
[0049] Embodiments of the present invention relate to a method and apparatus for improving integrated circuit performance by using a patterned bump layout on a power grid of the integrated circuit. Embodiments of the present invention further relate to a method and apparatus for improving bump placement on a top metal layer of an integrated circuit. Embodiments of the present invention further relate to a method and apparatus for creating a bump array on a top metal layer of an integrated circuit. Embodiments of the present invention further relate to a computer system that determines an optimal bump pattern given a set of conditions. Embodiments of the present invention further relate to a computer-readable medium having instructions for determining an optimal placement of bumps on an integrated circuit. Embodiments of the present invention also relate to a method for positioning a maximum number of bumps on a power grid of an integrated circuit.
[0050] Figure 4 shows a section (50) of a top metal layer of an exemplary integrated circuit in accordance with an embodiment of the present invention. The section (50) has a first metal bar (52) connected to VDD> i-e., power, and a second metal bar (54) connected to Vss, i.e., ground. The first metal bar (52) has two bumps (56a, 56b) and the second metal bar (54) has one bump (also referred to as "reference bump") (56c).
[0051] Those skilled in the art will appreciate that although the first metal bar
(52) is connected to power and the second metal bar (54) is connected to ground, in other embodiments of the present invention, the first metal bar (52) may be connected to ground and the second metal bar (54) may be connected to power.
[0052] A separation between the bumps (56a, 56b) on the first metal bar (52) is defined as a vertical pitch, Vp. Moreover, a distance between the first bump (56a) on the first metal bar (52) and the bump (56c) on the second metal bar (54) is defined as an across pitch, AP. Likewise, AP also denotes the distance between the second bump (56b) on the first metal bar (52) and the bump (56c) on the second metal bar (54). An angle θ represents the angle between the two across pitches.
[0053] The presence of angle θ allows for the rearrangement of the bumps (56a,
56b) on the first metal bar (52) in order to create different bump patterns. Varying angle θ can be done by repositioning the bumps (56a, 56b) on the first metal bar (52) and or adjusting the spacing between the first and second metal bars (52, 54). By effectively varying θ, properties of a top metal layer may be changed as desired. Properties dependent on the angle θ include, but are not limited to, metal layer resistance, metal layer capacitance, metal layer inductance, metal layer electrical performance, overall bump current flow, bump population, bump electromagnetivity, signal track positioning, and integration characteristics.
[0054] Once an angle Θ is determined for a particular design, bumps on a top metal layer may be patterned such that the arrangement of bumps results in repetitive groups of bumps having an angle θ between across pitches in a group of bumps as shown in Figure 4. In other words, the properties between a group of bumps as shown in Figure 4 may be replicated across part or all of a top metal layer in order to create a particular bump array.
[0055] Figure 5a shows a section of a top metal layer of an integrated circuit in accordance with an embodiment of the present invention. In Figure 5a, angle θ is set at 60 degrees. When angle θ is equal to 60 degrees, a maximum packing of bumps on a top metal layer may be achieved, as shown below with reference to Figure 5b. This may be beneficial when the current flow capabilities for individual bumps are relatively low. In this embodiment, the number of bumps on a top metal layer is maximized, and thus, the overall amount of current that can flow from an integrated circuit to a chip package is accordingly maximized. Further, note that when angle θ is equal to 60 degrees, the distances between the bumps (56a, 56b, 56c) are all equal.
[0056] Those skilled in the art will appreciate that although angle θ is set at 60 degrees in Figure 5 a, similar bump and metal layer properties and structures may be realized using any angle θ up to 75 degrees. Further, although this embodiment will be referred to as the "60 degrees" embodiment, those skilled in the art will understand that this embodiment applies to embodiments having any angle θ up to 75 degrees.
[0057] Figure 5b shows a top metal layer (60) of an integrated circuit in accordance with the embodiment shown in Figure 5a. In Figure 5b, the three bump structure shown in Figure 5a is repeated across the top metal layer (60) of an integrated circuit. [0058] Figure 6a shows a section of a top metal layer of an integrated circuit in accordance with an embodiment of the present invention. In Figure 6a, angle θ is set at 90 degrees. When angle θ is equal to 90 degrees, the first metal bar (52) and second metal bar (54) are spaced closer together than the 60 degrees embodiment shown and discussed above with reference to Figure 5 a. Due to the first and second metal bars (52, 54) being closer together, there is higher capacitance between the first and second metal bars (52, 54) than there is in the 60 degrees embodiment. Further, also due to the first and second metal bars (52, 54) being spaced closer together, more metal bars can be positioned in a top metal layer than what would be possible in the 60 degrees embodiment. However, because the first and second bumps (56a, 56b) have to be spaced further apart when angle θ is 90 degrees, fewer bumps per metal bar can be positioned on a top metal layer than the 60 degrees embodiment.
[0059] Those skilled in the art will appreciate that although angle θ is set at 90 degrees in Figure 6a, similar bump and metal layer properties and structures may be realized using any angle θ from 76 degrees up to 105 degrees. Further, although this embodiment will be referred to as the "90 degrees" embodiment, those skilled in the art will understand that this embodiment applies to embodiments having any angle θ from 76 degrees up to 105 degrees.
[0060] Figure 6b shows a top metal layer (70) of an integrated circuit in accordance with the embodiment shown in Figure 6a. In Figure 6b, the three bump structure shown in Figure 6a is repeated across the top metal layer (70) of an integrated circuit.
[0061] Figure 7a shows a section of a top metal layer of an integrated circuit in accordance with an embodiment of the present invention. In Figure 7a, angle θ is set at 120 degrees. When angle θ is equal to 120 degrees, the first metal bar (52) and second metal bar (54) are virtually touching each other. However, because an electrical short would occur if the first and second metal bars (52, 54) actually touched each other, a minimum amount of spacing (82) between the first and second metal bars (52, 54) is present between the first and second metal bars (52, 54) to ensure that the first and second metal bars (52, 54) do not come into contact with each other.
[0062] Further, in the embodiment shown in Figure 7a, less bumps per metal bar can be positioned on a top metal layer than the 90 degrees embodiment shown and discussed above with reference to Figure 6a. However, because the first and second metal bars (52, 54) in Figure 7a are spaced closer together than the metal bars shown in Figure 6b, more metal bars can be positioned on a top metal layer than what would be possible in the 90 degrees embodiment.
[0063] Those skilled in the art will appreciate that although angle θ is set at 120 degrees in Figure 7a, similar bump and metal layer properties and structures may be realized using any angle θ from 106 degrees up to 135 degrees. Further, although this embodiment will be referred to as the "120 degrees" embodiment, those skilled in the art will understand that this embodiment applies to embodiments having any angle θ from 106 degrees up to 135 degrees.
[0064] Figure 7b shows a top metal layer (80) of an integrated circuit in accordance with the embodiment shown in Figure 7a. In Figure 7b, the three bump structure shown in Figure 7a is repeated across the top metal layer (80) of an integrated circuit.
[0065] Figure 8a shows a section of a top metal layer of an integrated circuit in accordance with an embodiment of the present invention. In Figure 8a, angle θ is set at 150 degrees. When angle θ is equal to 150 degrees, the first and second metal bars (52, 54) are essentially "interlocked." As shown in Figure 8a, to ensure that the first and second metal bars (52, 54) do not physically touch each other, the first and metal bars (52, 54) are configured, i.e., designed, in a "stair-case" pattern such that there is some finite amount of spacing (92) between the first and second metal bars (52, 54). Further, as shown in Figure 8a, the bumps (56a, 56b, 56c) are partially aligned. Also, the landing pad size of the bumps (56a, 56b, 56c) may be changed because this embodiment is, to a certain extent, immune to bump placement variations.
[0066] In the embodiment shown in Figure 8a, due to the interlocked structure of the metal bars (52, 54), the amount of capacitance present is higher than is present in the 120 degrees embodiment. Further, more metal bars can be positioned in a top metal layer using the 120 degrees embodiment than what would be possible in the 120 degrees embodiment. However, because bumps on a particular metal bar are spaced further apart in Figure 8a, fewer bumps per metal bar can be positioned on a top metal layer than the 120 degrees embodiment.
[0067] In another embodiment, the width of the first and second metal bars (52,
54) may be shortened so as to allow more spacing on the sides of the interlocked structure formed by the first and second metal bars (52, 54). This can be done without affecting the electrical properties among the first metal bar (52), the second metal bar (54), and the bumps (56a, 56b, 56c). By allowing more spacing on the sides of the interlocked structure, there is additional space to route signals and signal tracks. This embodiment may be viewed as a "150 degrees narrow" approach.
[0068] Those skilled in the art will appreciate that although angle θ is set at 150 degrees in Figures 8a and 8b, similar bump and metal layer properties and structures may be realized using any angle θ from 136 degrees up to 165 degrees. Further, although the embodiments shown in Figures 8a and 8b will collectively be referred to as the "150 degrees" embodiment, those skilled in the art will understand that this embodiment applies to embodiments having any angle θ from 136 degrees up to 165 degrees.
[0069] Figure 8c shows a top metal layer (90) of an integrated circuit in accordance with the embodiments shown in Figures 8a and 8b. In Figure 8c, the three bump structure shown in Figures 8a and 8b is repeated across the top metal layer (90) of an integrated circuit. [0070] It is important to note that in the 120 and 150 degrees embodiments, the width of the metal bars is approximately equal to the width of the landing pads of the bumps. Landing pad size is usually part of design rules for a particular power grid. It follows that the minimal allowable spacing between two bumps is twice the size of a landing pad. Depending on the width of a particular metal bar and a width of a particular landing pad, different bump structures may be realized. Further, those skilled in the art will appreciate that for different design rules/constraints, the angles may change. Nonetheless, the principles of the present invention are consistent with embodiments in which this occurs.
[0071] Figure 9a shows a section of a top metal layer of an integrated circuit in accordance with an embodiment of the present invention. In Figure 9a, angle θ is set at 180 degrees. When angle θ is equal to 180 degrees, the first and second metal bars (52, 54) are "interlocked." As shown in Figure 9a, to ensure that the first and second metal bars (52, 54) do not physically touch each other, the first and metal bars (52, 54) are configured, i.e., designed, in a "stair-case" pattern such that there is some finite amount of spacing (102) between the first and second metal bars (52, 54). Further, as shown in Figure 9a, the bumps (56a, 56b, 56c) are aligned.
[0072] In the embodiment shown in Figure 9a, due to the interlocked structure of the metal bars (52, 54), the amount of capacitance present is higher than is present in the 150 degrees embodiment. Further, more metal bars can be positioned in a top metal layer using the 180 degrees embodiment than what would be possible in the 150 degrees embodiment. However, because bumps on a particular metal bar are spaced further apart in Figure 9a, fewer bumps per metal bar can be positioned on a top metal layer than the 150 degrees embodiment.
[0073] Those skilled in the art will appreciate that although angle θ is set at 180 degrees in Figure 9a, similar bump and metal layer properties and structures may be realized using any angle θ greater than or equal to 166 degrees. Further, although this embodiment will be referred to as the "180 degrees" embodiment, those skilled in the art will understand that this embodiment applies to embodiments having any angle θ greater than or equal to 166 degrees.
[0074] Figure 9b shows a top metal layer (100) of an integrated circuit in accordance with the embodiment shown in Figure 9a. In Figure 9b, the three bump structure shown in Figure 9a is repeated across the top metal layer (100) of an integrated circuit.
[0075] Those skilled in the art will appreciate that although the various embodiments of the present invention are shown as the first metal bar (52) and second metal bar (54) get closer together, similar angles may be achieved by increasing/decreasing spacing between bumps on a particular metal bar.
[0076] Those skilled in the art will appreciate that the various embodiments described above with reference to Figures 5a, 6a, 7a, 8a, 8b, and 9a may be partially or wholly combined in a top metal layer to effectuate a particular desired behavior of an integrated circuit and/or of a chip package operatively connected to the integrated circuit.
[0077] Figure 10 shows an exemplary computer system (110) in accordance with an embodiment of the present invention. The computer system (110) is capable of determining a value to which angle θ needs to be varied according to various factors provided by a designer and/or computer program. Input parameters (112) to the computer system (110) may include, among other things, a desired capacitance between metal bars, a desired resistance between metal bars, a desired inductance due to metal bars, a desired bump current flow to/from a top metal layer of an integrated circuit, a desired bump population on the top metal layer, and a desired amount of space to be available for signals and/or signal tracks on the top metal layer. One of ordinary skill in the art will understand that the input parameters (112) may include additional information corresponding to particular properties and characteristics of the metal bars and bumps that are going to be used in the design.
[0078] The input parameters (112) serve as input data to the computer system
(110) via some computer-readable medium, e.g., network path, floppy disk, input file, etc. The computer system (110) then stores the input parameters (112) in memory (not shown) to subsequently determine (via microprocessor functions) a value of angle θ that will most closely achieve the behavior desired by the designer. Thereafter, the computer system (110) the determined θ value (114) via some user-readable medium, e.g., monitor display, network path, etc. The computer system (110) may also determine and output one or more suggested top metal layer designs in accordance with the designer's specifications.
[0079] Those skilled in the art will appreciate that in other embodiments, a computer-readable medium may be used, where the computer-readable medium has instructions for, among other things, determining a value of an angle between a line from a reference bump to a first bump and a line from a reference bump to a second bump. The determination by the instructions may be dependent on various desired metal layer properties provided by a designer, a computer system, or other software program.
[0080] Advantages of the present invention may include one or more of the following. In some embodiments, because an angle may be varied to create various bump placements, a designer is provided with added flexibility in determining a particular bump layout for a top metal layer of an integrated circuit.
[0081] In some embodiments, because a determination of a value of an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump is dependent on various desired electrical properties, a bump placement that meets particular electrical needs may be generated. [0082] In some embodiments, because an angle is used to characterize a particular placement of bumps, a bump layout of a top metal layer may be patterned to achieve increased efficiency and/or performance.
[0083] In some embodiments, because a bump layout of a top metal layer is improved by characterizing particular placements of bumps by an angle, integrated circuit performance may be improved.
[0084] While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as disclosed herein. Accordingly, the scope of the invention should be limited only by the attached claims.

Claims

What is claimed is:
[cl] A method for designing an integrated circuit having a top metal layer, the top metal layer having a first metal bar and a second metal bar, the method comprising: defining a desired angle, wherein the desired angle represents an angle formed between a line from a reference bump to a first bump and a line from the reference bump to a second bump, wherein the first and second bumps reside on the first metal bar, and wherein the reference bump resides on the second metal bar; and using the desired angle to position the first metal bar, the first bump, and the second bump on the integrated circuit.
[c2] The method of claim 1, wherein using the desired angle to position the first metal bar, the first bump, and the second bump creates a particular bump structure among the first bump, the second bump, and the reference bump, the method further comprising: repeating the bump structure across the top metal layer.
[c3] The method of claim 1, wherein using the desired angle to position the first metal bar, the first bump, and the second bump creates a particular bump structure among the first bump, the second bump, and the reference bump, the method further comprising: repeating the bump structure across a portion of the top metal layer.
[c4] The method of claim 1, wherein the first metal bar is operatively connected to a voltage source, and wherein the second metal bar is operatively connected to ground.
[c5] The method of claim 1, further comprising: determining a value of the desired angle prior to positioning the first metal bar, the first bump, and the second bump on the integrated circuit [c6] The method of claim 5, wherein determining the value of the desired angle is dependent upon at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, desired signal track availability.
[c7] A method for designing an integrated circuit having a top metal layer, the top metal layer having a first metal bar and a second metal bar, the method comprising: defining a desired angle, wherein the desired angle represents an angle formed between a line from a reference bump to a first bump and a line from the reference bump to a second bump, wherein the first and second bumps reside on the first metal bar, and wherein the reference bump resides on the second metal bar; and using the desired angle to position the first metal bar and the second metal bar on the integrated circuit.
[c8] The method of claim 7, wherein using the desired angle to position the first metal bar and the second metal bar on the integrated circuit creates a particular bump structure among the first bump, the second bump, and the reference bump, the method further comprising: repeating the bump structure across the top metal layer.
[c9] The method of claim 7, wherein using the desired angle to position the first metal bar and the second metal bar on the integrated circuit creates a particular bump structure among the first bump, the second bump, and the reference bump, the method further comprising: repeating the bump structure across a portion of the top metal layer.
[clO] The method of claim 7, wherein the first metal bar is operatively connected to a voltage source, and wherein the second metal bar is operatively connected to ground. [cll] The method of claim 7, further comprising: determining a value of the desired angle prior to positioning the first metal bar and the second metal bar on the integrated circuit
[cl2] The method of claim 11, wherein determining the value the desired angle is dependent upon at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, desired signal track availability.
[cl3] A computer system, comprising: a processor; a memory; and instructions, residing in the memory and executable on the processor, for determining a value of an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump.
[cl4] The computer system of claim 13, wherein the reference bumps resides on a first metal bar of a metal layer of an integrated circuit, and wherein the first and second bumps reside on a second metal bar of the metal layer.
[cl5] The computer system of claim 13, wherein determining the value of the angle is dependent on a desired metal layer property comprising at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the metal layer, desired signal track availability.
[cl6] The computer system of claim 15, further comprising: determining a metal layer design based on the desired metal layer property. [cl7] A computer-readable medium having instructions therein executable by processing, the instructions for: inputting a desired metal layer property; and determining a value of an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump based on the desired metal layer property, wherein the reference bump resides on a first metal bar, and wherein the first and second bumps reside on a second metal bar.
[cl8] The computer-readable medium of claim 17, wherein the value of the angle is used to create a particular bump placement among the first bump, the second bump, and the reference bump.
[cl9] The computer-readable medium of claim 18, wherein the bump placement is repeated across a metal layer of an integrated circuit.
[c20] The computer-readable medium of claim 18, wherein the bump placement is repeated across a portion of a metal layer of an integrated circuit.
[c21] An integrated circuit having a top metal layer, the top metal layer having a first metal bar and a second metal bar, the integrated circuit comprising: a first bump disposed on the first metal bar; a second bump disposed on the first metal bar; and a reference bump disposed on the second metal bar, wherein the first bump and the second bump are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 60 degrees.
[c22] The integrated circuit of claim 21, wherein the first bump, the second bump, and the reference bump form a bump structure that is repeated across the top metal layer to form a patterned bump array. [c23] The integrated circuit of claim 21, wherein the first bump, the second bump, and the reference bump for a bump structure that is repeated across a portion of the top metal layer.
[c24] The integrated circuit of claim 21, wherein the first metal bar is operatively connected to a voltage source, and wherein the second metal bar is operatively connected to ground.
[c25] The integrated circuit of claim 21, wherein the value of the angle is dependent on at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
[c26] An integrated circuit having a top metal layer, the top metal layer having a first metal bar and a second metal bar, the integrated circuit comprising: a first bump disposed on the first metal bar; a second bump disposed on the first metal bar; and a reference bump disposed on the second metal bar, wherein the first metal bar and the second metal bar are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 60 degrees.
[c27] The integrated circuit of claim 26, wherein the first bump, the second bump, and the reference bump form a bump structure that is repeated across the top metal layer to form a patterned bump array.
[c28] The integrated circuit of claim 26, wherein the first bump, the second bump, and the reference bump for a bump structure that is repeated across a portion of the top metal layer. [c29] The integrated circuit of claim 26, wherein the first metal bar is operatively connected to a voltage source, and wherein the second metal bar is operatively connected to ground.
[c30] The integrated circuit of claim 26, wherein the value of the angle is dependent on at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
[c31] A patterned bump array for a power grid of an integrated circuit, comprising: a reference bump disposed on a first metal bar; a first bump disposed on a second metal bar; and a second bump disposed on a second metal bar, wherein the first bump, the second bump, and the reference bump are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 60 degrees.
[c32] The patterned bump array of claim 31, wherein the first metal bar and second metal bar form a portion of the power grid.
[c33] The patterned bump array of claim 31, wherein the first metal bar is operatively connected to power, and wherein the second metal bar is operatively connected to ground.
[c34] The patterned bump array of claim 31, wherein the arrangement of the first bump, the second bump, and the reference bump is repeated across the power grid.
[c35] The patterned bump array of claim 31, wherein the arrangement of the first bump, the second bump, and the reference bump is repeated across a portion of the power grid. [c36] The patterned bump array of claim 31, wherein the value of the angle is dependent on at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
[c37] A bump layout for a power grid of an integrated circuit, comprising: a reference bump disposed on a first metal bar; a first bump disposed on a second metal bar; and a second bump disposed on a second metal bar, wherein the first metal bar and the second metal bar are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 60 degrees.
[c38] The bump layout of claim 37, wherein the first metal bar and second metal bar form a portion of the power grid.
[c39] The bump layout of claim 37, wherein the first metal bar is operatively connected to power, and wherein the second metal bar is operatively connected to ground.
[c40] The bump layout of claim 37, wherein the arrangement of the first metal bar and the second metal bar is repeated across the power grid.
[c41] The bump layout of claim 37, wherein the arrangement of the first metal bar and the second metal bar is repeated across a portion of the power grid.
[c42] The bump layout of claim 37, wherein the value of the angle is dependent on at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability. [c43] An integrated circuit having a top metal layer, the top metal layer having a first metal bar and a second metal bar, the integrated circuit comprising: a first bump disposed on the first metal bar; a second bump disposed on the first metal bar; and a reference bump disposed on the second metal bar, wherein the first bump and the second bump are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 90 degrees.
[c44] The integrated circuit of claim 43, wherein the first bump, the second bump, and the reference bump form a bump structure that is repeated across the top metal layer to form a patterned bump array.
[c45] The integrated circuit of claim 43, wherein the first bump, the second bump, and the reference bump for a bump structure that is repeated across a portion of the top metal layer.
[c46] The integrated circuit of claim 43, wherein the first metal bar is operatively connected to a voltage source, and wherein the second metal bar is operatively connected to ground.
[c47] The integrated circuit of claim 43, wherein the value of the angle is dependent on at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
[c48] An integrated circuit having a top metal layer, the top metal layer having a first metal bar and a second metal bar, the integrated circuit comprising: a first bump disposed on the first metal bar; a second bump disposed on the first metal bar; and a reference bump disposed on the second metal bar, wherein the first metal bar and the second metal bar are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 90 degrees.
[c49] The integrated circuit of claim 48, wherein the first bump, the second bump, and the reference bump form a bump structure that is repeated across the top metal layer to form a patterned bump array.
[c50] The integrated circuit of claim 48, wherein the first bump, the second bump, and the reference bump for a bump structure that is repeated across a portion of the top metal layer.
[c51] The integrated circuit of claim 48, wherein the first metal bar is operatively connected to a voltage source, and wherein the second metal bar is operatively connected to ground.
[c52] The integrated circuit of claim 48, wherein the value of the angle is dependent on at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
[c53] A patterned bump array for a power grid of an integrated circuit, comprising: a reference bump disposed on a first metal bar; a first bump disposed on a second metal bar; and a second bump disposed on a second metal bar, wherein the first bump, the second bump, and the reference bump are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 90 degrees.
[c54] The patterned bump array of claim 53, wherein the first metal bar and second metal bar form a portion of the power grid. [c55] The patterned bump array of claim 53, wherein the first metal bar is operatively connected to power, and wherein the second metal bar is operatively connected to ground.
[c56] The patterned bump array of claim 53, wherein the arrangement of the first bump, the second bump, and the reference bump is repeated across the power grid.
[c57] The patterned bump array of claim 53, wherein the arrangement of the first bump, the second bump, and the reference bump is repeated across a portion of the power grid.
[c58] The patterned bump array of claim 53, wherein the value of the angle is dependent on at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
[c59] A bump layout for a power grid of an integrated circuit, comprising: a reference bump disposed on a first metal bar; a first bump disposed on a second metal bar; and a second bump disposed on a second metal bar, wherein the first metal bar and the second metal bar are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 90 degrees.
[c60] The bump layout of claim 59, wherein the first metal bar and second metal bar form a portion of the power grid.
[c61] The bump layout of claim 59, wherein the first metal bar is operatively connected to power, and wherein the second metal bar is operatively connected to ground. [c62] The bump layout of claim 59, wherein the arrangement of the first metal bar and the second metal bar is repeated across the power grid.
[c63] The bump layout of claim 59, wherein the arrangement of the first metal bar and the second metal bar is repeated across a portion of the power grid.
[c64] The bump layout of claim 59, wherein the value of the angle is dependent on at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
[c65] An integrated circuit having a top metal layer, the top metal layer having a first metal bar and a second metal bar, the integrated circuit comprising: a first bump disposed on the first metal bar; a second bump disposed on the first metal bar; and a reference bump disposed on the second metal bar, wherein the first bump and the second bump are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 120 degrees.
[c66] The integrated circuit of claim 65, wherein the first bump, the second bump, and the reference bump form a bump structure that is repeated across the top metal layer to form a patterned bump array.
[c67] The integrated circuit of claim 65, wherein the first bump, the second bump, and the reference bump for a bump structure that is repeated across a portion of the top metal layer.
[c68] The integrated circuit of claim 65, wherein the first metal bar is operatively connected to a voltage source, and wherein the second metal bar is operatively connected to ground. [c69] The integrated circuit of claim 65, wherein the value of the angle is dependent on at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
[c70] An integrated circuit having a top metal layer, the top metal layer having a first metal bar and a second metal bar, the integrated circuit comprising: a first bump disposed on the first metal bar; a second bump disposed on the first metal bar; and a reference bump disposed on the second metal bar, wherein the first metal bar and the second metal bar are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 120 degrees.
[c71] The integrated circuit of claim 70, wherein the first bump, the second bump, and the reference bump form a bump structure that is repeated across the top metal layer to form a patterned bump array.
[c72] The integrated circuit of claim 70, wherein the first bump, the second bump, and the reference bump for a bump structure that is repeated across a portion of the top metal layer.
[c73] The integrated circuit of claim 70, wherein the first metal bar is operatively connected to a voltage source, and wherein the second metal bar is operatively connected to ground.
[c74] The integrated circuit of claim 70, wherein the value of the angle is dependent on at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability. [c75] A patterned bump array for a power grid of an integrated circuit, comprising: a reference bump disposed on a first metal bar; a first bump disposed on a second metal bar; and a second bump disposed on a second metal bar, wherein the first bump, the second bump, and the reference bump are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 120 degrees.
[c76] The patterned bump array of claim 75, wherein the first metal bar and second metal bar form a portion of the power grid.
[c77] The patterned bump array of claim 75, wherein the first metal bar is operatively connected to power, and wherein the second metal bar is operatively connected to ground.
[c78] The patterned bump array of claim 75, wherein the arrangement of the first bump, the second bump, and the reference bump is repeated across the power grid.
[c79] The patterned bump array of claim 75, wherein the arrangement of the first bump, the second bump, and the reference bump is repeated across a portion of the power grid.
[c80] The patterned bump array of claim 75, wherein the value of the angle is dependent on at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
[c81] A bump layout for a power grid of an integrated circuit, comprising: a reference bump disposed on a first metal bar; a first bump disposed on a second metal bar; and a second bump disposed on a second metal bar, wherein the first metal bar and the second metal bar are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 120 degrees.
[c82] The bump layout of claim 81, wherein the first metal bar and second metal bar form a portion of the power grid.
[c83] The bump layout of claim 81, wherein the first metal bar is operatively connected to power, and wherein the second metal bar is operatively connected to ground.
[c84] The bump layout of claim 81, wherein the arrangement of the first metal bar and the second metal bar is repeated across the power grid.
[c85] The bump layout of claim 81, wherein the arrangement of the first metal bar and the second metal bar is repeated across a portion of the power grid.
[c86] The bump layout of claim 81, wherein the value of the angle is dependent on at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
[c87] An integrated circuit having a top metal layer, the top metal layer having a first metal bar and a second metal bar, the integrated circuit comprising: a first bump disposed on the first metal bar; a second bump disposed on the first metal bar; and a reference bump disposed on the second metal bar, wherein the first bump and the second bump are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 150 degrees. [c88] The integrated circuit of claim 87, wherein the first bump, the second bump, and the reference bump form a bump structure that is repeated across the top metal layer to form a patterned bump array.
[c89] The integrated circuit of claim 87, wherein the first bump, the second bump, and the reference bump for a bump structure that is repeated across a portion of the top metal layer.
[c90] The integrated circuit of claim 87, wherein the first metal bar is operatively connected to a voltage source, and wherein the second metal bar is operatively connected to ground.
[c91] The integrated circuit of claim 87, wherein the value of the angle is dependent on at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
[c92] An integrated circuit having a top metal layer, the top metal layer having a first metal bar and a second metal bar, the integrated circuit comprising: a first bump disposed on the first metal bar; a second bump disposed on the first metal bar; and a reference bump disposed on the second metal bar, wherein the first metal bar and the second metal bar are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 150 degrees.
[c93] The integrated circuit of claim 92, wherein the first bump, the second bump, and the reference bump form a bump structure that is repeated across the top metal layer to form a patterned bump array. [c94] The integrated circuit of claim 92, wherein the first bump, the second bump, and the reference bump for a bump structure that is repeated across a portion of the top metal layer.
[c95] The integrated circuit of claim 92, wherein the first metal bar is operatively connected to a voltage source, and wherein the second metal bar is operatively connected to ground.
[c96] The integrated circuit of claim 92, wherein the value of the angle is dependent on at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
[c97] A patterned bump array for a power grid of an integrated circuit, comprising: a reference bump disposed on a first metal bar; a first bump disposed on a second metal bar; and a second bump disposed on a second metal bar, wherein the first bump, the second bump, and the reference bump are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 150 degrees.
[c98] The patterned bump array of claim 97, wherein the first metal bar and second metal bar form a portion of the power grid.
[c99] The patterned bump array of claim 97, wherein the first metal bar is operatively connected to power, and wherein the second metal bar is operatively connected to ground.
[clOO] The patterned bump array of claim 97, wherein the arrangement of the first bump, the second bump, and the reference bump is repeated across the power grid. [clOl] The patterned bump array of claim 97, wherein the arrangement of the first bump, the second bump, and the reference bump is repeated across a portion of the power grid.
[cl02] The patterned bump array of claim 97, wherein the value of the angle is dependent on at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
[cl03] A bump layout for a power grid of an integrated circuit, comprising: a reference bump disposed on a first metal bar; a first bump disposed on a second metal bar; and a second bump disposed on a second metal bar, wherein the first metal bar and the second metal bar are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 150 degrees.
[cl04] The bump layout of claim 103, wherein the first metal bar and second metal bar form a portion of the power grid.
[cl05] The bump layout of claim 103, wherein the first metal bar is operatively connected to power, and wherein the second metal bar is operatively connected to ground.
[cl06] The bump layout of claim 103, wherein the arrangement of the first metal bar and the second metal bar is repeated across the power grid.
[cl07] The bump layout of claim 103, wherein the arrangement of the first metal bar and the second metal bar is repeated across a portion of the power grid. [cl08] The bump layout of claim 103, wherein the value of the angle is dependent on at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
[cl09] An integrated circuit having a top metal layer, the top metal layer having a first metal bar and a second metal bar, the integrated circuit comprising: a first bump disposed on the first metal bar; a second bump disposed on the first metal bar; and a reference bump disposed on the second metal bar, wherein the first bump and the second bump are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 180 degrees.
[cllO] The integrated circuit of claim 109, wherein the first bump, the second bump, and the reference bump form a bump structure that is repeated across the top metal layer to form a patterned bump array.
[clll] The integrated circuit of claim 109, wherein the first bump, the second bump, and the reference bump for a bump structure that is repeated across a portion of the top metal layer.
[cll2] The integrated circuit of claim 109, wherein the first metal bar is operatively connected to a voltage source, and wherein the second metal bar is operatively connected to ground.
[cll3] The integrated circuit of claim 109, wherein the value of the angle is dependent on at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability. [el 14] An integrated circuit having a top metal layer, the top metal layer having a first metal bar and a second metal bar, the integrated circuit comprising: a first bump disposed on the first metal bar; a second bump disposed on the first metal bar; and a reference bump disposed on the second metal bar, wherein the first metal bar and the second metal bar are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 180 degrees.
[cll5] The integrated circuit of claim 114, wherein the first bump, the second bump, and the reference bump form a bump structure that is repeated across the top metal layer to form a patterned bump array.
[el 16] The integrated circuit of claim 114, wherein the first bump, the second bump, and the reference bump for a bump structure that is repeated across a portion of the top metal layer.
[el 17] The integrated circuit of claim 114, wherein the first metal bar is operatively connected to a voltage source, and wherein the second metal bar is operatively connected to ground.
[el 18] The integrated circuit of claim 114, wherein the value of the angle is dependent on at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
[el 19] A patterned bump array for a power grid of an integrated circuit, comprising: a reference bump disposed on a first metal bar; a first bump disposed on a second metal bar; and a second bump disposed on a second metal bar, wherein the first bump, the second bump, and the reference bump are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 180 degrees.
[cl20] The patterned bump array of claim 119, wherein the first metal bar and second metal bar form a portion of the power grid.
[cl21] The patterned bump array of claim 119, wherein the first metal bar is operatively connected to power, and wherein the second metal bar is operatively connected to ground.
[cl22] The patterned bump array of claim 119, wherein the arrangement of the first bump, the second bump, and the reference bump is repeated across the power grid.
[cl23] The patterned bump array of claim 119, wherein the arrangement of the first bump, the second bump, and the reference bump is repeated across a portion of the power grid.
[cl24] The patterned bump array of claim 119, wherein the value of the angle is dependent on at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
[cl25] A bump layout for a power grid of an integrated circuit, comprising: a reference bump disposed on a first metal bar; a first bump disposed on a second metal bar; and a second bump disposed on a second metal bar, wherein the first metal bar and the second metal bar are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 180 degrees. [cl26] The bump layout of claim 125, wherein the first metal bar and second metal bar form a portion of the power grid.
[cl27] The bump layout of claim 125, wherein the first metal bar is operatively connected to power, and wherein the second metal bar is operatively connected to ground.
[cl28] The bump layout of claim 125, wherein the arrangement of the first metal bar and the second metal bar is repeated across the power grid.
[cl29] The bump layout of claim 125, wherein the arrangement of the first metal bar and the second metal bar is repeated across a portion of the power grid.
[cl30] The bump layout of claim 125, wherein the value of the angle is dependent on at least one selected from the group consisting of: a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
PCT/US2002/037643 2001-11-29 2002-11-25 Improving integrated circuit performance and reliability using a patterned bump layout on a power grid WO2003048981A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU2002352885A AU2002352885A1 (en) 2001-11-29 2002-11-25 Improving integrated circuit performance and reliability using a patterned bump layout on a power grid
JP2003550104A JP2005512315A (en) 2001-11-29 2002-11-25 Method and apparatus for improving integrated circuit performance and reliability using a patterned bump layout on a power grid
GB0410834A GB2398903A (en) 2001-11-29 2004-05-14 Improving integrated circuit performance and reliability using a patterned bump layout on a power grid

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
US09/997,437 US6473883B1 (en) 2001-11-29 2001-11-29 Integrated circuit performance and reliability using angle measurement for a patterned bump layout on a power grid
US09/997,523 US6541873B1 (en) 2001-11-29 2001-11-29 90 degree bump placement layout for an integrated circuit power grid
US09/997,437 2001-11-29
US09/997,844 US6617699B2 (en) 2001-11-29 2001-11-29 120 degree bump placement layout for an integrated circuit power grid
US09/997,438 US6762505B2 (en) 2001-11-29 2001-11-29 150 degree bump placement layout for an integrated circuit power grid
US09/997,452 2001-11-29
US09/997,452 US6577002B1 (en) 2001-11-29 2001-11-29 180 degree bump placement layout for an integrated circuit power grid
US09/997,523 2001-11-29
US09/997,438 2001-11-29
US09/997,844 2001-11-29
US09/997,471 US6495926B1 (en) 2001-11-29 2001-11-29 60 degree bump placement layout for an integrated circuit power grid
US09/997,471 2001-11-29

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WO2003048981A3 WO2003048981A3 (en) 2004-06-24

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EP1932173A2 (en) * 2005-09-01 2008-06-18 Texas Instruments Incorporated Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices

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EP1376692A2 (en) * 2002-06-27 2004-01-02 Sun Microsystems, Inc. Power grid and bump pattern with reduced inductance and resistance
EP1376692A3 (en) * 2002-06-27 2005-02-09 Sun Microsystems, Inc. Power grid and bump pattern with reduced inductance and resistance
EP1932173A2 (en) * 2005-09-01 2008-06-18 Texas Instruments Incorporated Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices
EP1932173A4 (en) * 2005-09-01 2013-06-05 Texas Instruments Inc Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices
USRE48420E1 (en) 2005-09-01 2021-02-02 Texas Instruments Incorporated Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices

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GB2398903A (en) 2004-09-01
GB0410834D0 (en) 2004-06-16
AU2002352885A1 (en) 2003-06-17
WO2003048981A3 (en) 2004-06-24
JP2005512315A (en) 2005-04-28

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