WO2003038905A2 - Lateral soi field-effect transistor - Google Patents

Lateral soi field-effect transistor Download PDF

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Publication number
WO2003038905A2
WO2003038905A2 PCT/IB2002/004412 IB0204412W WO03038905A2 WO 2003038905 A2 WO2003038905 A2 WO 2003038905A2 IB 0204412 W IB0204412 W IB 0204412W WO 03038905 A2 WO03038905 A2 WO 03038905A2
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thickness
layer
silicon
dielectric layer
dielectric
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PCT/IB2002/004412
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French (fr)
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WO2003038905A3 (en
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Rene P. Zingg
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Koninklijke Philips Electronics N.V.
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Priority to AU2002339582A priority Critical patent/AU2002339582A1/en
Publication of WO2003038905A2 publication Critical patent/WO2003038905A2/en
Publication of WO2003038905A3 publication Critical patent/WO2003038905A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Definitions

  • the invention relates to a thin film lateral SOI (silicon on oxide) device.
  • SOI lateral power devices show degraded high-side performance due to carrier depletion from the handle wafer (pinching of the drift region). This degradation has been minimized by going to step- and stair-SOCOS device as shown in WO 00/31776, which in fact maximizes the silicon film thickness and available doping therein.
  • the step- and stair-SOCOS devices have, however, a potential trough for electrons in the drift region which has different heights in the SOI film due to variation in silicon film thickness and oxide thickness. This again results in a partial alignment of the vertical electric field with the current direction, increasing impact ionization rate and, thereby, limiting acceptable longitudinal electric fields. Among other disadvantages, this makes it necessary to have the transition step close to the source region where vertical fields are small and makes the device longer for a given voltage rating.
  • the device 2 comprises a buried oxide layer (BOx) 4 on a substrate (not shown) and a silicon layer 6 on the buried oxide layer 4, the silicon layer comprising, from left to right in Fig.l, a first thickness region 8, a second thickness region 10 having a thickness smaller than the first thickness region 8 and a third thickness region 12 having a thickness smaller than the second thickness region 10.
  • a first transition 14 is located between the first thickness region 8 and the second thickness region 10 and a second transition 16 is located between the second thickness region 10 and the third thickness region 12.
  • a second oxide layer (dielectric) is provided on top of the silicon layer 6, the second oxide layer having a gate oxide layer 18, a field oxide layer 20 having a thickness larger than the thickness of the gate oxide layer 18 and a drift oxide layer 22 having a thickness larger than the thickness of the field oxide layer 20.
  • An oxide layer transition 24 is located between the field oxide layer 20 and the drift oxide layer 22.
  • a gate 26 is located above the gate oxide layer 18 and extends as a field plate 28 above a channel region 38 the field oxide layer 20 and the drift oxide layer 22.
  • a drain 30 is laterally spaced from the third thickness region 12 of the silicon layer 6.
  • a source 32 is laterally separated from the gate 26.
  • the gate 26 comprises a polysilicon layer and is covered by a further oxide layer 34.
  • a further metal field plate 36 is provided which extends from the source region 32 across the further oxide layer 34 to almost an end of the field oxide layer 20.
  • the device comprises a substrate, a buried oxide layer on the substrate, a layer of silicon on the buried oxide layer (SOI, silicon on insulator), a layer of dielectric 18 (preferably grown oxide), a gate or field- plate 28 on top of this dielectric, a further dielectric layer 34, a metal layer 36, and a passivation layer (not shown).
  • SOI silicon on the buried oxide layer
  • dielectric 18 preferably grown oxide
  • the SOI layer is sequentially reduced in thickness towards the drain 30 and the oxide sequentially increased in thickness.
  • the metal layer 36 is also used to further remove the field plate 36 from the SOI layer and thereby reduce the vertical fields.
  • Line A in Figure 1 indicates the minimum potential for electrons and shows the change of height of this minimum in the SOI layer due to changes in semiconductor- and dielectric thickness.
  • the US-A 5,362,979 shows a SOI transistor with improved source-high performance especially for bridge type circuits.
  • the laterally extending silicon layer of the drift region has a region of thinner thickness over a portion of the length of the drift region.
  • the field plate is formed with a separation from the gate and extends over the thin portion of the drift region.
  • the gate and field plate are short-circuited by a metal interconnect.
  • the thin film lateral SOI device of the invention comprises, a substrate and a buried oxide layer (BOx) as a dielectric layer on the substrate; a silicon layer on the buried oxide layer, the silicon layer comprising a first thickness silicon region, a second thickness silicon region having a thickness smaller than the first thickness silicon region and a third thickness silicon region having a thickness smaller than the second thickness silicon region; a dielectric layer (TOx) on top of the silicon layer, comprising a gate dielectric layer on top of the first thickness silicon region, a field dielectric layer on top of the a second thickness silicon region, the field dielectric layer having thickness larger than the thickness of the a gate dielectric layer, and a drift dielectric layer on top of the third thickness silicon region the drift dielectric layer having thickness larger than the thickness of the a drift di
  • a thin film SOI device wherein the dielectric layers are oxide layers preferably produced by a LOCOS process.
  • a thin film SOI device wherein the gate terminates at the transition between the field dielectric layer and the drift dielectric region.
  • a thin film SOI device comprising a further dielectric layer covering at least the gate and the drift dielectric layer.
  • a thin film SOI device comprising a further field plate extending across the further dielectric layer (46).
  • the additional field plate supplements the field plate extension of the gate such that the field plate arrangement is adapted to control the complete drift region in the silicon layer or protect the drift region against external influences.
  • a thin film SOI device is provided wherein the further field plate extends to almost an end of the drift dielectric layer.
  • a thin film SOI device wherein the further field plate is connected to the source, whereby the further field plate is on the same potential level as the field plate extension of the gate which is advantageous in controlling the device.
  • a thin film SOI device wherein the gate consists of polysilicon, which is advantageous in integrating the step of manufacturing the gate during the manufacturing process of the device as is well known in the art.
  • a thin film SOI device wherein the further field plate consists of a metal resulting in a well defined shape of the further field plate during manufacturing of the device.
  • a thin film SOI device is provided, wherein the further field plate consists of a first metal layer and a second metal layer, the second metal layer being isolated from the first metal layer.
  • the first metal layer may be connected to the gate and the second metal layer can be connected to the source or the gate or to any separate potential which might be desired to control the drift region.
  • a thin film SOI device is provided, wherein the second metal layer is isolated from the first metal layer by a dielectric layer.
  • a thin film lateral SOI device comprises a substrate, a buried oxide layer on the substrate, a layer of silicon on the buried oxide layer (SOI, silicon on insulator), a layer of dielectric (preferably grown oxide), a gate or field-plate on top of this dielectric.
  • SOI silicon on the buried oxide layer
  • dielectric preferably grown oxide
  • One or multiple metal layers, isolated from the underground by a dielectric film with local contact holes and a passivation layer complete the device.
  • the SOI layer is sequentially reduced in thickness towards the drain, and the oxide sequentially increased in thickness.
  • the metal layer is also used to further remove field-plate from the SOI layer and thereby reduce the vertical fields.
  • SOI film thickness and dielectric under the field-plates are matched according to an equation in order to minimize displacements of the minimum potential of electrons along the device. This reduces carrier multiplication by impact ionization, thereby allowing higher lateral electric fields and permitting shorter devices for a given voltage rating. Reduction in drift region, increase in possible doping, increase in SOI film thickness, and reduction in area individually or in combination contribute to reducing the specific on- resistance, especially in high-side operation.
  • the above described device is a step and stair SOI device or a step and stair
  • SOCOS silicon-oxide-channel-oxide-silicon
  • LDMOS low-density dielectric
  • the invention is applicable to all thin film SOI devices having step transitions in the top oxide layer or level transitions caused by the ends of electrodes or field plates.
  • variations in and the thickness of the additional top oxide may be engineered to level out the potential trough for the electrons.
  • the thinning of the silicon layer on the buried oxide can be moved further to the collector reducing pinch-off effects in high side operation and therefore improve current drive of the device.
  • Figure 1 is a schematic section of a step and stair thin film lateral SOI device of the state of art
  • Figure 2 is a schematic section of a thin film lateral SOI device according to an embodiment of the invention.
  • Figure 3 is a schematic section of a thin film lateral SOI device according to another embodiment of the invention.
  • FIG. 2 An embodiment of the thin film lateral SOI device 40 of the invention is shown in Figure 2 in which the same reference numerals are used for the same parts as in Figure 1.
  • the thin film lateral SOI device of the invention also has a buried oxide layer 4 on a substrate (not shown) and a silicon layer 6 on the buried oxide layer 4.
  • the silicon layer 6 again having the first thickness region 8, the second thickness region 10 and the third thickness region 12.
  • the oxide layer on top of the silicon layer 6 comprises a gate oxide layer 18, a field oxide layer 20 and a drift oxide layer 22 which are provided on the thickness regions 8, 10, 12 respectively of the silicon layer 6.
  • the thin film lateral SOI device 40 of the invention as shown in Figure 2 consists of a gate 42 located above a channel region 38 and extending as a field plate 44 above the gate-oxide layer 18 and the field oxide layer 20.
  • the gate field plate ends at this transition 24, thereby allowing a thickness-matched further dielectric layer 46 to be inserted between field-plate 48 and SOI film 12.
  • This means that the polysilicon gate 42 is ending at the transition 24 from field oxide (FOx) of the first silicon layer thickness region 8 to the drift oxide (DOx) of the second silicon layer thickness region 10.
  • a further field plate 48 extends from the source 32 across the further oxide layer 46 to almost an end of the drift oxide layer 22 and covers the further oxide layer 46.
  • the further oxide layer 46 and the further field plate 48 are extending smoothly across the gate extension and the field oxide as there is no step in this area as in the device of the state of art. The fact that the step of the device of the state of art is missing, further improves the desired functionality of the device.
  • the further field plate 48 may be embodied by an extension of the source 32 and may consist of a metal layer.
  • the potential minimum of the electrons in the silicon layer in the device of Figure 1 is expressed by a relationship between top-oxide thickness (TOx), buried oxide thickness (BOx), and silicon-film thickness (t S o ⁇ ) as follows:
  • FIG. 1 is selected according to the following relationship between top-oxide thickness (TOx), buried oxide thickness (BOx), and silicon-film thickness (tSOI) as follows:
  • TOxl is the total thickness of all dielectric layers under the field plate to the left of the transition (24)
  • TOx2 is the thickness of all dielectric layers under the field plate to the right of the transition (24)
  • BOx is the thickness of the buried oxide layer tson is the thickness of the silicon on insulator layer to the left of the transition (24) tsoi 2 s the thickness of the silicon on insulator layer to the right of the transition (24) e si is the dielectric constant of silicon e ox is the dielectric constant of the dielectric.
  • Tuning the thickness of the buried oxide and the silicon layer according the equating (3) results in a reduction of the depth of the potential trough.
  • FIG. 3 Another embodiment of the thin film lateral SOI device 50 of the invention is shown in Figure 3 in which the same reference numerals are used for the same parts as in Figures 1 and 2.
  • the further field plate is embodied by a first metal layer 52 and a second metal layer 54, the second metal layer being isolated from the first metal layer 52, by an oxide layer 56.
  • the second metal layer 54 may be connected to the source, to the gate or to a separate potential.
  • BOx is the thickness of the buried oxide layer 4
  • TOxl is the total thickness of all dielectric layers below the field plate to the left of the transition 24
  • TOx2 is the thickness of all dielectric layers under the field plate to the right of the transition 24, i.e. the thickness of the drift dielectric layer 22 plus the thickness of the further dielectric layer 46
  • TOx3 is the thickness of all dielectric layers under the further field plate 54, i.e. the thickness of the third dielectric layer thickness region plus the thickness of the further dielectric layer 46 plus the thickness of the dielectric layer 56 tson the thickness of the first silicon layer thickness region 10 tson the thickness of the second silicon layer thickness region 12 tson is the thickness of the third silicon layer thickness region 14 to the right of the second silicon layer thickness region 12

Abstract

A thin film lateral SOI device comprises a substrate and a buried oxide layer (4) (BOx) as a dielectric layer on the substrate; a silicon layer (6) on the buried oxide layer, the silicon layer comprising a first thickness silicon region (8), a second thickness silicon region (10) having a thickness smaller than the first thickness silicon region (8) and a third thickness silicon region (12) having a thickness smaller than the second thickness silicon region (10); a dielectric layer (TOx) on top of the silicon layer (6), comprising a gate dielectric layer (18) on top of the first thickness silicon region (8), a field dielectric layer (20) on top of the a second thickness silicon region (10), the field dielectric layer (20) having a thickness larger than the thickness of the gate dielectric layer (18), and a drift dielectric layer (22) on top of the third thickness silicon region (12) the drift dielectric layer (22) having a thickness larger than the thickness of the drift dielectric layer (20); a gate (42) on top of the gate dielectric layer (18) above a channel region (38); a field plate (44) extending across the field dielectric layer (20); a drain (30) laterally spaced to the third thickness silicon region (12) of the silicon layer (6); and a source (32) laterally separated from the gate.

Description

Thin film lateral SOI device
The invention relates to a thin film lateral SOI (silicon on oxide) device.
SOI lateral power devices show degraded high-side performance due to carrier depletion from the handle wafer (pinching of the drift region). This degradation has been minimized by going to step- and stair-SOCOS device as shown in WO 00/31776, which in fact maximizes the silicon film thickness and available doping therein.
The step- and stair-SOCOS devices have, however, a potential trough for electrons in the drift region which has different heights in the SOI film due to variation in silicon film thickness and oxide thickness. This again results in a partial alignment of the vertical electric field with the current direction, increasing impact ionization rate and, thereby, limiting acceptable longitudinal electric fields. Among other disadvantages, this makes it necessary to have the transition step close to the source region where vertical fields are small and makes the device longer for a given voltage rating.
These features of the step and stair thin film SOI LDMOS device as shown in
WO 00/31776 are explained with reference to Figure 1 which shows such a device of the state of art. The device 2 comprises a buried oxide layer (BOx) 4 on a substrate (not shown) and a silicon layer 6 on the buried oxide layer 4, the silicon layer comprising, from left to right in Fig.l, a first thickness region 8, a second thickness region 10 having a thickness smaller than the first thickness region 8 and a third thickness region 12 having a thickness smaller than the second thickness region 10. A first transition 14 is located between the first thickness region 8 and the second thickness region 10 and a second transition 16 is located between the second thickness region 10 and the third thickness region 12. A second oxide layer (dielectric) is provided on top of the silicon layer 6, the second oxide layer having a gate oxide layer 18, a field oxide layer 20 having a thickness larger than the thickness of the gate oxide layer 18 and a drift oxide layer 22 having a thickness larger than the thickness of the field oxide layer 20. An oxide layer transition 24 is located between the field oxide layer 20 and the drift oxide layer 22. A gate 26 is located above the gate oxide layer 18 and extends as a field plate 28 above a channel region 38 the field oxide layer 20 and the drift oxide layer 22. A drain 30 is laterally spaced from the third thickness region 12 of the silicon layer 6. A source 32 is laterally separated from the gate 26. The gate 26 comprises a polysilicon layer and is covered by a further oxide layer 34. On top of the further oxide layer 34, a further metal field plate 36 is provided which extends from the source region 32 across the further oxide layer 34 to almost an end of the field oxide layer 20.
In such a SOI device called step and stair SOI device, the device comprises a substrate, a buried oxide layer on the substrate, a layer of silicon on the buried oxide layer (SOI, silicon on insulator), a layer of dielectric 18 (preferably grown oxide), a gate or field- plate 28 on top of this dielectric, a further dielectric layer 34, a metal layer 36, and a passivation layer (not shown). The SOI layer is sequentially reduced in thickness towards the drain 30 and the oxide sequentially increased in thickness. The metal layer 36 is also used to further remove the field plate 36 from the SOI layer and thereby reduce the vertical fields. Line A in Figure 1 indicates the minimum potential for electrons and shows the change of height of this minimum in the SOI layer due to changes in semiconductor- and dielectric thickness.
The US-A 5,362,979 shows a SOI transistor with improved source-high performance especially for bridge type circuits. The laterally extending silicon layer of the drift region has a region of thinner thickness over a portion of the length of the drift region. The field plate is formed with a separation from the gate and extends over the thin portion of the drift region. The gate and field plate are short-circuited by a metal interconnect. Also in this SOI device, there is the problem that the electrons drift in the drift region not at a constant distance from the buried oxide which results in a vertical displacement of the electrons in the drift region which, in turn, leads to a carrier multiplication by impact ionization limiting the break down voltage.
It is the object of the invention to further improve the performance of the step- and stair-SOCOS device by reducing carrier multiplication by impact ionization while increasing longitudinal electric field and thereby reducing the length of the device. To achieve this objective, the thin film lateral SOI device of the invention comprises, a substrate and a buried oxide layer (BOx) as a dielectric layer on the substrate; a silicon layer on the buried oxide layer, the silicon layer comprising a first thickness silicon region, a second thickness silicon region having a thickness smaller than the first thickness silicon region and a third thickness silicon region having a thickness smaller than the second thickness silicon region; a dielectric layer (TOx) on top of the silicon layer, comprising a gate dielectric layer on top of the first thickness silicon region, a field dielectric layer on top of the a second thickness silicon region, the field dielectric layer having thickness larger than the thickness of the a gate dielectric layer, and a drift dielectric layer on top of the third thickness silicon region the drift dielectric layer having thickness larger than the thickness of the a drift dielectric layer; a gate on top of the gate dielectric layer above a channel region; a field plate extending across the field dielectric layer; a drain laterally spaced to the third thickness silicon region of the silicon layer; a source laterally separated from the gate; a further dielectric layer covering at least the gate and the drift dielectric layer; and a further field plate extending across the further dielectric layer. Thereby, the vertical displacement of the potential well can be eliminated, or in a concrete example with given silicon and oxide thickness is reduced by a factor of about 5. The reduced scalar product between electric field and current direction allows shifting the thinning of the SOI film further to the drain, reducing pinch-off effects in high-side operation and therefore improve current drive of the device.
According to a preferred embodiment of the invention a thin film SOI device is provided, wherein the dielectric layers are oxide layers preferably produced by a LOCOS process.
According to a preferred embodiment of the invention a thin film SOI device is provided, wherein the gate terminates at the transition between the field dielectric layer and the drift dielectric region. This feature results in the advantage that any layer with which is deposited on top of the field plate and the further dielectric layer may be deposited any intend on top and the transition between the end of the field plate and the additional dielectric layer. Furthermore, the location of the end of the field plate is well defined which facilitates designing the thickness dimensions of the silicon layer and the second dielectric layer or the top oxide in a way to minimize vertical displacement of the electrons in the drift region.
According to a preferred embodiment of the invention a thin film SOI device is provided, comprising a further dielectric layer covering at least the gate and the drift dielectric layer. According to a preferred embodiment of the invention a thin film SOI device is provided, comprising a further field plate extending across the further dielectric layer (46). In this embodiment, the additional field plate supplements the field plate extension of the gate such that the field plate arrangement is adapted to control the complete drift region in the silicon layer or protect the drift region against external influences. According to a preferred embodiment of the invention a thin film SOI device is provided wherein the further field plate extends to almost an end of the drift dielectric layer.
According to a preferred embodiment of the invention a thin film SOI device is provided wherein the further field plate is connected to the source, whereby the further field plate is on the same potential level as the field plate extension of the gate which is advantageous in controlling the device.
According to a preferred embodiment of the invention a thin film SOI device is provided, wherein the gate consists of polysilicon, which is advantageous in integrating the step of manufacturing the gate during the manufacturing process of the device as is well known in the art.
According to a preferred embodiment of the invention a thin film SOI device is provided, wherein the further field plate consists of a metal resulting in a well defined shape of the further field plate during manufacturing of the device. According to a preferred embodiment of the invention a thin film SOI device is provided, wherein the further field plate consists of a first metal layer and a second metal layer, the second metal layer being isolated from the first metal layer. The first metal layer may be connected to the gate and the second metal layer can be connected to the source or the gate or to any separate potential which might be desired to control the drift region. According to a preferred embodiment of the invention a thin film SOI device is provided, wherein the second metal layer is isolated from the first metal layer by a dielectric layer.
Further preferred embodiment of the invention are characterized in the rest of the sub-claims. A thin film lateral SOI device comprises a substrate, a buried oxide layer on the substrate, a layer of silicon on the buried oxide layer (SOI, silicon on insulator), a layer of dielectric (preferably grown oxide), a gate or field-plate on top of this dielectric. One or multiple metal layers, isolated from the underground by a dielectric film with local contact holes and a passivation layer complete the device. The SOI layer is sequentially reduced in thickness towards the drain, and the oxide sequentially increased in thickness. The metal layer is also used to further remove field-plate from the SOI layer and thereby reduce the vertical fields. SOI film thickness and dielectric under the field-plates are matched according to an equation in order to minimize displacements of the minimum potential of electrons along the device. This reduces carrier multiplication by impact ionization, thereby allowing higher lateral electric fields and permitting shorter devices for a given voltage rating. Reduction in drift region, increase in possible doping, increase in SOI film thickness, and reduction in area individually or in combination contribute to reducing the specific on- resistance, especially in high-side operation. The above described device is a step and stair SOI device or a step and stair
SOCOS (silicon-oxide-channel-oxide-silicon) device forming a LDMOS. The invention is applicable to all thin film SOI devices having step transitions in the top oxide layer or level transitions caused by the ends of electrodes or field plates. By designing the field plate of the device according to the teaching of the invention, variations in and the thickness of the additional top oxide may be engineered to level out the potential trough for the electrons. In the device of the invention, the thinning of the silicon layer on the buried oxide can be moved further to the collector reducing pinch-off effects in high side operation and therefore improve current drive of the device.
These and various other advantages of an embodiment of the invention are now described with reference to the drawings in which:
Figure 1 is a schematic section of a step and stair thin film lateral SOI device of the state of art; Figure 2 is a schematic section of a thin film lateral SOI device according to an embodiment of the invention; and
Figure 3 is a schematic section of a thin film lateral SOI device according to another embodiment of the invention.
An embodiment of the thin film lateral SOI device 40 of the invention is shown in Figure 2 in which the same reference numerals are used for the same parts as in Figure 1.
The thin film lateral SOI device of the invention also has a buried oxide layer 4 on a substrate (not shown) and a silicon layer 6 on the buried oxide layer 4. The silicon layer 6 again having the first thickness region 8, the second thickness region 10 and the third thickness region 12. The oxide layer on top of the silicon layer 6 comprises a gate oxide layer 18, a field oxide layer 20 and a drift oxide layer 22 which are provided on the thickness regions 8, 10, 12 respectively of the silicon layer 6. The thin film lateral SOI device 40 of the invention as shown in Figure 2 consists of a gate 42 located above a channel region 38 and extending as a field plate 44 above the gate-oxide layer 18 and the field oxide layer 20. Depending on thickness the SOI regions 10 and 12 and the thickness of the drift oxide layer 22 the gate field plate ends at this transition 24, thereby allowing a thickness-matched further dielectric layer 46 to be inserted between field-plate 48 and SOI film 12. This means that the polysilicon gate 42 is ending at the transition 24 from field oxide (FOx) of the first silicon layer thickness region 8 to the drift oxide (DOx) of the second silicon layer thickness region 10.
At least the gate 42 and the field plate 44 and the drift oxide layer 22 are covered by the further oxide layer 46. A further field plate 48 extends from the source 32 across the further oxide layer 46 to almost an end of the drift oxide layer 22 and covers the further oxide layer 46. As the gate 42 ends at the transition 24 between the field oxide layer 20 and the drift oxide layer 22 , the further oxide layer 46 and the further field plate 48 are extending smoothly across the gate extension and the field oxide as there is no step in this area as in the device of the state of art. The fact that the step of the device of the state of art is missing, further improves the desired functionality of the device. The further field plate 48 may be embodied by an extension of the source 32 and may consist of a metal layer. Thereby, it is possible to maintain a smooth minimum electron potential plane B (Figure 2). The potential minimum of the electrons in the silicon layer in the device of Figure 1 is expressed by a relationship between top-oxide thickness (TOx), buried oxide thickness (BOx), and silicon-film thickness (tSoι) as follows:
Oxl *εa + -tSOIι *ε∞ (1)
Figure imgf000008_0001
for the first oxide layer thickness region 20, and
TOx2 * £si "*" n '■SOI,
(2)
(TOx2 +BOx) *-^- + εox
*SOI2 for the drift oxide layer 20 plus the thickness of the further oxide layer 34, wherein: BOx is the thickness of the buried oxide layer 4 TO l is the thickness of the field oxide layer 20 TOx2 is the thickness of the drift oxide layer 22 plus the thickness of the further oxide layer 46 tson is the thickness of the second thickness silicon region 10 tsoi2 is the thickness of the third thickness silicon region 12 € si is the dielectric constant of silicon e ox is the dielectric constant of the oxide. As an example, the device of the state of art shown in Figure 1, has with tsoil
= 1.0 μm, TOxl = 775 nm, BOx = 3 μm, tsoi2 = 425 nm, and TOx2=2.0 μm a change in potential minimum from 233 nm to 168 nm above buried oxide at the oxide transition, and back to 195 nm at the transition from polysilicon to field plate 28 to the metal field-plate 36. This is shown by line A in Figure 1. The potential minimum of the electrons in the silicon layer in the device of
Figure 2 is selected according to the following relationship between top-oxide thickness (TOx), buried oxide thickness (BOx), and silicon-film thickness (tSOI) as follows:
Figure imgf000009_0001
wherein: TOxl is the total thickness of all dielectric layers under the field plate to the left of the transition (24)
TOx2 is the thickness of all dielectric layers under the field plate to the right of the transition (24)
BOx is the thickness of the buried oxide layer tson is the thickness of the silicon on insulator layer to the left of the transition (24) tsoi2 s the thickness of the silicon on insulator layer to the right of the transition (24) e si is the dielectric constant of silicon e ox is the dielectric constant of the dielectric. In other words, by selecting the thickness parameters in the two regions of the drift region such that the left hand term of the equation equals the right hand term thereof, the vertical displacement of the potential well for electrons in the SOI layer (region 10) can be leveled out as shown by line B in Figure 2.
The device of the invention shown in Figure 2 results in a transition from 233 to 246 nm or one fifth of the previous value by merging the end of the field plate into the transition 24 and by choosing tsoil = 1 μm, tsoi2 = 560 nm, TOxl = 0,775 μm, TOx2 = 2.3 μm and BOx = 3 μm. Tuning the thickness of the buried oxide and the silicon layer according the equating (3) results in a reduction of the depth of the potential trough.
Another embodiment of the thin film lateral SOI device 50 of the invention is shown in Figure 3 in which the same reference numerals are used for the same parts as in Figures 1 and 2.
In the device 50, the further field plate is embodied by a first metal layer 52 and a second metal layer 54, the second metal layer being isolated from the first metal layer 52, by an oxide layer 56. The second metal layer 54 may be connected to the source, to the gate or to a separate potential. As can be seen from Fig. 3, there is a further change in the thickness of the SOI layer below the field plate 54 resulting in a SOI thickness regions 12 and 14 where the SOI region 14 has again a smaller thickness as compared to the thickness of the SOI region 12.
For the device of the invention shown in Figure 3, the following equation is valid:
Figure imgf000010_0001
wherein: BOx is the thickness of the buried oxide layer 4
TOxl is the total thickness of all dielectric layers below the field plate to the left of the transition 24
TOx2 is the thickness of all dielectric layers under the field plate to the right of the transition 24, i.e. the thickness of the drift dielectric layer 22 plus the thickness of the further dielectric layer 46
TOx3 is the thickness of all dielectric layers under the further field plate 54, i.e. the thickness of the third dielectric layer thickness region plus the thickness of the further dielectric layer 46 plus the thickness of the dielectric layer 56 tson the thickness of the first silicon layer thickness region 10 tson the thickness of the second silicon layer thickness region 12 tson is the thickness of the third silicon layer thickness region 14 to the right of the second silicon layer thickness region 12
€ si is the dielectric constant of silicon e ox is the dielectric constant of the dielectric. In the device of the invention shown in Figure 3, tson = 1 m, tsoi2 = 560 nm, TOxl = 0,775 μm, tSOi2 = 560 nm, TOx2 = 2.3 μm, tSoi3 = 425 nm and TOx3 = 3.1 μm, and BOx = 3 μm, and the electron potential is 215 nm above the buried oxide to silicon layer interface, symmetric in the center of the silicon layer. Also in this embodiment, the vertical displacement of the potential well for electrons in the SOI layer (region 12,14) can be leveled out as shown by line C in Figure 3.
New characteristics and advantages of the invention covered by this document have been set forth in the foregoing description. It will be understood, however, that this disclosure is, in many respects, only illustrative. Changes may be made in details, particularly in matters of shape, size, and arrangement of parts, without exceeding the scope of the invention. The scope of the invention is, of course, defined in the language in which the appended claims are expressed.

Claims

CLAIMS:
1. A thin film lateral SOI device comprising: a substrate and a buried oxide layer (4) (BOx) as a dielectric layer on the substrate; a silicon layer (6) on the buried oxide layer, the silicon layer comprising a first thickness silicon region (8), a second thickness silicon region (10) having a thickness smaller than the first thickness silicon region (8) and a third thickness silicon region (12) having a thickness smaller than the second thickness silicon region (10); a dielectric layer (TOx) on top of the silicon layer (6), comprising a gate dielectric layer (18) on top of the first thickness silicon region (8), a field dielectric layer (20) on top of the second thickness silicon region (10), the field dielectric layer (20) having a thickness larger than the thickness of the gate dielectric layer (18), and a drift dielectric layer (22) on top of the third thickness silicon region (12) the drift dielectric layer (22) having a thickness larger than the thickness of the drift dielectric layer (20); a gate (42) on top of the gate dielectric layer (18) above a channel region (38); a field plate (44) extending across the field dielectric layer (20); a drain (30) laterally spaced to the third thickness silicon region (12) of the silicon layer (6); and a source (32) laterally separated from the gate.
2. The thin film SOI device of claim 1 , wherein the dielectric layers are oxide layers preferably produced by a LOCOS process.
3. The thin film SOI device of claim 1 or 2, wherein the gate (42) terminates at a transition (24) between the field dielectric layer (20) and the drift dielectric layer (24).
4. The thin film SOI device of claim 1 ,2 or 3, comprising a further dielectric layer (46) covering at least the gate (42) and the drift dielectric layer (22)
5. The thin film SOI device of any of the preceding claims, comprising a further field plate (48; 52, 54) extending across the further dielectric layer (46).
6. The thin film SOI device of claim 5, wherein the further field plate (48; 52, 54) extends to almost an end of the drift dielectric layer (22).
7. The thin film SOI device of claim 5 or 6, wherein the further field plate (48; 52, 54) is connected to the source (32).
8. The thin film SOI device of claim 1 , wherein the gate (42) consists of polysilicon.
9. The thin film SOI device of claim 5, wherein the further field plate (48) consists of a metal.
10. The thin film SOI device of claim 5, wherein the further field plate consists of a first metal layer (52) and a second metal layer (54), the second metal layer (54) being isolated from the first metal layer (52).
11. The thin film SOI device of claim 10, wherein the second metal layer (91) is isolated from the first metal layer (52) by a dielectric layer (56).
12. The thin film SOI device of any of the preceding claims, wherein the thickness of SOI and dielectric are related according to the following formula:
TOxx * εsi + — tSO ε0
Figure imgf000013_0001
* _; "t* fr lsπoiιr, ό -
(TOxx + BOx) * + ε TOx + BOx * + εox
Figure imgf000013_0002
wherein: TOxl is the total thickness of all dielectric layers under the field plate to the left of the transition (24)
TOx2 is the thickness of all dielectric layers under the field plate to the right of the transition (24) BOx is the thickness of the buried oxide layer tson is the thickness of the silicon on insulator layer to the left of the transition (24) tsoκ is the thickness of the silicon on insulator layer to the right of the transition (24) e si is the dielectric constant of silicon
€ ox is the dielectric constant of the dielectric.
13. The thin film SOI device of any of the claims 1 to 11, wherein the thickness of
SOI and dielectric are related according to the following formula:
Figure imgf000014_0001
wherein: BOx is the thickness of the buried oxide layer (4)
TOxl is the total thickness of all dielectric layers below the field plate to the left of the transition (24)
TOx2 is the thickness of all dielectric layers under the field plate to the right of the transition (24), i.e. the thickness of the drift dielectric layer (22) plus the thickness of the further dielectric layer (46)
TOx3 is the thickness of all dielectric layers under the further field plate (48), i.e. the thickness of the third dielectric layer thickness region plus the thickness of the further dielectric layer (46) plus the thickness of the dielectric layer (56) tson is the thickness of the first silicon layer thickness region (10) tsoi2 is the thickness of the second silicon layer thickness region (12) tson is the thickness of the third silicon layer thickness region (14) to the right of the second silicon layer thickness region (12)
€ si is the dielectric constant of silicon e ox is the dielectric constant of the dielectric.
PCT/IB2002/004412 2001-11-01 2002-10-22 Lateral soi field-effect transistor WO2003038905A2 (en)

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