WO2003034216B1 - Automatic instruction set architecture generation - Google Patents

Automatic instruction set architecture generation

Info

Publication number
WO2003034216B1
WO2003034216B1 PCT/US2002/028898 US0228898W WO03034216B1 WO 2003034216 B1 WO2003034216 B1 WO 2003034216B1 US 0228898 W US0228898 W US 0228898W WO 03034216 B1 WO03034216 B1 WO 03034216B1
Authority
WO
WIPO (PCT)
Prior art keywords
instruction set
set architecture
instructions
existing
region
Prior art date
Application number
PCT/US2002/028898
Other languages
French (fr)
Other versions
WO2003034216A3 (en
WO2003034216A2 (en
Inventor
David William Goodwin
Dror Maydan
Ding-Kai Chen
Darin Stamenov Petkov
Steven Weng-Kiang Tjiang
Peng Tu
Christopher Rowen
Original Assignee
Tensilica Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tensilica Inc filed Critical Tensilica Inc
Priority to JP2003536879A priority Critical patent/JP4209776B2/en
Priority to KR1020047005643A priority patent/KR100705509B1/en
Priority to GB0407839A priority patent/GB2398144B/en
Publication of WO2003034216A2 publication Critical patent/WO2003034216A2/en
Publication of WO2003034216A3 publication Critical patent/WO2003034216A3/en
Publication of WO2003034216B1 publication Critical patent/WO2003034216B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/447—Target code generation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/443—Optimisation

Abstract

A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operation, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.

Claims

I PCT/US02/28898
AMENDED CLAIMS
[received by the International Bureau on 08 April 2004 (08.04.2004); original claims 1, 2, 7, 14, 20, 21, 27, 30 and 31 amended; original claim 13 cancelled; new claims 32 and 33 added; remaining claims unchanged (5 pages)]
AMENDED CLAIMS
[received by the International Bureau on 08 April 2004 (08.04.2004); original claims 1, 2, 7, 14, 20, 21, 27, 30 and 31 amended; original claim 13 cancelled; new claims 32 and 33 added; remaining claims unchanged (5 pages)]
1. A system, comprising:
means for receiving at least one software program written in a high level language^ and
means for automatically generating an instruction set architecture optimized for executing that program(s), wherein the instruction set architecture is represented as a set of configurations containing one or more extension instructions based on instructions in an existing standard or existing user defined instruction set architecture.
2. The system of claim 1, wherein:
the extension instructions operate on states and register files in the existing standard or existing user-defined instruction set architecture.
3. The system of claim 2, wherein the extension instructions contain vectorized versions of the existing instructions.
4. The system of claim 2, wherein the extension instructions contain VLIW combinations of the existing instructions.
5. The system of claim 2, wherein the extension instructions contain fused combinations of the existing instructions.
6. The system of claim 2, wherein the extension instructions contain specialized versions of the existing instructions.
7. The system of claim 2, wherein the extension instructions_contain vectorized versions of operations supported by the high level language.
8. The system of claim 2, wherein the extension instructions contain VLIW combinations of operations supported by the high level language.
9. The system of claim 2, wherein the extension instructions contain fused combinations of operations supported by the high level language.
10. The system of claim 2, wherein the extension instructions contain specialized versions of operations supported by the high level language.
11. The system of claim 2, wherein the extension instructions contain at least two of vectorized, VLIW, fused and specialized versions of the existing instructions.
12. The system of claim 2, wherein the extension instructions contain at least two of vectorized, VLIW, fused and specialized versions of operations supported by the high level language.
14. The system of claim 2, wherein:
instruction set architecture generation is guided by analysis information gathered from the at least one software program; and the analysis information is gathered for each region of code that could get a performance improvement from a generated instruction set algorithm.
15. The system of claim 14, wherein the analysis information includes an execution count of each region as determined from real or estimated profiling information.
16. The system of claim 14, wherein the analysis information includes an execution count of each region as determined from user-supplied directives.
17. The system of claim 14, where the analysis information includes a dependence graph of each region.
18. The system of claim 14, where the analysis information includes a set of operation vector lengths that can be used to improve performance of each region.
19. The system of claim 14, wherein each region is evaluated with a set of instruction set architecture configurations to determine a performance improvement that would result if instructions, operations, register files, and states represented by the configuration could be used for the region.
20. The system of claim 19, wherein:
instruction set architecture generation uses as a guideline an estimate of hardware cost of each instruction set architecture configuration that includes a cost of logic necessary to implement instructions, operations, register files, and state represented by the configuration; and the hardware cost and performance improvement of each instruction set architecture configuration for each region is used to determine a set of instruction set architecture configurations that together describe the generated instruction set architecture such that the performance improvement of the software program(s) is increased as much as possible while the hardware cost of the generated instruction set architecture does not exceed a cost budget.
21. The system of claim 19, wherein:
instruction set architecture generation uses as a guideline an estimate of hardware cost of each instruction set architecture configuration that includes a cost of logic necessary to implement instructions, operations, register files, and state represented by the configuration; and the hardware cost and performance improvement of each instruction set architecture configuration for each region is used to determine the set of instruction set architecture configurations that together describe the generated instruction set architecture such that the hardware cost of the generated instruction set architecture is as small as possible while providing a performance improvement that is greater or equal to a performance goal.
22. The system of claim 19, wherein the hardware cost and performance improvement of each instruction set architecture hardware configuration for each region is used to determine the set of instruction set architecture configurations that together describe the generated instruction set architecture such that the hardware cost of the generated instruction set architecture is smaller than a predetermined function of the performance improvement.
23. The system of claim 19, wherein a performance improvement provided by a particular instruction set architecture configuration for a particular region is determined by
an instruction scheduling algorithm operating on a modified dependence graph of the region.
24. The system of claim 23, wherein the dependence graph is modified to replicate operations with an operation width that is less than one.
25. The system of claim 23, wherein the dependence graph is modified to replace groups of operations with a single fused operation.
26. The system of claim 19, wherein the performance improvement provided by a particular instruction set architecture configuration for a particular region is determined using resource limits.
27. The system of claim 2, wherein instruction set architecture generation uses as a guideline an estimate of hardware cost of each instruction set architecture configuration that includes a cost of logic necessary to implement instructions, operations, register files, and state represented by the configuration.
28. The system of claim 27, wherein the hardware cost is estimated by adding hardware costs of components present in the instruction set architecture configuration.
29. The system of claim 27, wherein the hardware cost is reduced to represent reduced logic necessary when specialized operations replace generic operations.
30. A system, comprising:
means for receiving at least one software program written in a high level language^ and
means for automatically generating an instruction set architecture optimized for
executing said at least one program, by adding one or more new extension_instructions to instructions in an existing instruction set architecture based on the analysis of the said at least one program^
wherein the new instruction(s) contain vectorized versions of the existing instructions.
31. A system, comprising:
means for receiving at least one software program written in a high level language^ and means for automatically generating an instruction set architecture optimized for executing said at least one program, by adding one or more new register files based on the analysis of the said at least one program,;
wherein the new register file(s) are vectorized versions of an existing standard or existing user defined instruction set architecture.
32. A system, comprising:
means for receiving at least one software program written in a high level language; and
means for automatically generating an instruction set architecture optimized for executing said at least one program, by adding one or more new extension instructions to instructions in an existing instruction set architecture based on the analysis of the said at least one program,
wherein the new instruction(s) contain specialized versions of existing standard or user-defined instructions in the existing instruction set architecture.
33. A system, comprising:
means for receiving at least one software program written in a high level language; and means for automatically generating an instruction set architecture optimized for executing said at least one program, by adding one or more new extension instructions to instructions in an existing instruction set architecture based on the analysis of the said at least one program,
wherein a single new instruction contains one of a fused, specialized and vectorized combination of existing standard or user-defined instructions in the existing instruction set architecture.
PCT/US2002/028898 2001-10-16 2002-09-10 Automatic instruction set architecture generation WO2003034216A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2003536879A JP4209776B2 (en) 2001-10-16 2002-09-10 Automatic instruction set architecture generation
KR1020047005643A KR100705509B1 (en) 2001-10-16 2002-09-10 Automatic instruction set architecture generation
GB0407839A GB2398144B (en) 2001-10-16 2002-09-10 Automatic instruction set architecture generation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/981,291 2001-10-16
US09/981,291 US6941548B2 (en) 2001-10-16 2001-10-16 Automatic instruction set architecture generation

Publications (3)

Publication Number Publication Date
WO2003034216A2 WO2003034216A2 (en) 2003-04-24
WO2003034216A3 WO2003034216A3 (en) 2004-09-10
WO2003034216B1 true WO2003034216B1 (en) 2004-12-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/028898 WO2003034216A2 (en) 2001-10-16 2002-09-10 Automatic instruction set architecture generation

Country Status (7)

Country Link
US (2) US6941548B2 (en)
JP (1) JP4209776B2 (en)
KR (1) KR100705509B1 (en)
CN (1) CN100367209C (en)
GB (1) GB2398144B (en)
TW (1) TW594581B (en)
WO (1) WO2003034216A2 (en)

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Also Published As

Publication number Publication date
TW594581B (en) 2004-06-21
WO2003034216A3 (en) 2004-09-10
GB2398144B (en) 2005-10-12
US20050278713A1 (en) 2005-12-15
KR100705509B1 (en) 2007-04-13
US7971197B2 (en) 2011-06-28
US20030074654A1 (en) 2003-04-17
WO2003034216A2 (en) 2003-04-24
KR20040062567A (en) 2004-07-07
CN100367209C (en) 2008-02-06
JP2005507105A (en) 2005-03-10
GB0407839D0 (en) 2004-05-12
GB2398144A (en) 2004-08-11
JP4209776B2 (en) 2009-01-14
US6941548B2 (en) 2005-09-06
CN1608247A (en) 2005-04-20

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