WO2003012570A1

WO2003012570A1 - Power source circuit

Info

Publication number: WO2003012570A1
Application number: PCT/JP2002/006555
Authority: WO
Inventors: Hiroshi Miyagi
Original assignee: Niigata Seimitsu Co., Ltd.
Priority date: 2001-07-30
Filing date: 2002-06-28
Publication date: 2003-02-13
Also published as: TW567667B; JP2003044153A

Abstract

A power source circuit (10) capable of reducing power consumption for generating a constant voltage and a constant current, and a circuit scale, comprising FETs (20-23, 30, 40, 42), a resistor (50), and an output buffer (60), wherein FETs (20, 30, 40, 42), the resistor (50) and the output buffer (60) constitute a constant voltage source, and FETs (20-23, 30. 40, 42) and the resistor (50) constitute a constant current source. Components necessary to generate one type of constant voltage and three types of constant current are shared.

Description

Description Power supply circuit Technical field

The present invention relates to a power supply circuit that generates a constant current and a constant voltage in various circuits.

Conventionally, a constant current source and a constant voltage source have been used in various circuits. Most commonly, there is known a constant current source composed of a current source and a current mirror circuit.For example, if there are multiple stages of differential amplifiers using two FETs, each stage A constant current circuit is provided corresponding to the differential amplifier. In addition, a constant voltage source is used to generate a predetermined reference voltage or to generate a constant operating voltage to be supplied to each part in the circuit.

By the way, when a constant voltage source and a plurality of constant current sources are included in a circuit as described above, they operate separately, and the power required for operation is individually consumed. There is a problem that the whole power consumption increases. In particular, when many constant current sources are included, there is a problem that a plurality of similar configurations exist and the circuit scale becomes large. Disclosure of the invention

The present invention has been made in view of the above points, and an object of the present invention is to provide a power supply circuit capable of reducing the power consumption when generating a constant voltage and a constant current and reducing the circuit scale. Is to do.

In order to solve the above-described problem, a power supply circuit according to the present invention includes a reference voltage generation unit that generates a reference voltage, an output buffer that generates a predetermined constant voltage corresponding to the reference voltage, and a predetermined voltage that corresponds to the reference voltage. And a current driver for generating a constant current of Since the reference voltage generator that generates the reference voltage required to generate the constant voltage and the constant current can be used in common, the circuit scale can be reduced, and Power consumption can be reduced as compared with the case where the voltage generation units are individually provided.

Further, it is desirable that the above-described current driver generates a plurality of constant currents. By increasing the number of generated constant currents, it is possible to enhance the effects (reduced circuit scale and reduced power consumption) of sharing the reference voltage generator.

Further, it is preferable that the above-described current driver include a plurality of FETs that form a current mirror circuit together with the FET included in the reference voltage generator when a reference voltage is applied to the gate. This makes it possible to generate a constant current separately for each FET.

It is also desirable that the current driver generates a plurality of different constant currents by changing the gate length L and the gate width W of each of the plurality of FETs. This makes it possible to generate several types of constant current as needed. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a circuit diagram of a power supply circuit according to an embodiment,

FIG. 2 is a circuit diagram showing a modification of the power supply circuit,

FIG. 3 is a circuit diagram showing another modified example of the power supply circuit. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, a semiconductor device according to an embodiment of the present invention will be described in detail. FIG. 1 is a circuit diagram of a power supply circuit according to the present embodiment. The power supply circuit 10 shown in FIG. 1 includes FETs 20 to 23, 30, 40, and 42, a resistor 50, and an output buffer 60. The power supply circuit 10 has a function as a constant voltage source for generating a predetermined constant voltage and a function as a constant current source for generating a plurality of constant currents. Next, each of these constant voltage sources and constant current sources will be described.

Configuration and operation of constant voltage source

In the configuration of the power supply circuit 10, the FETs 20, 30, 40, and 42, the resistor 50, and the output buffer 60 form a constant voltage source. The FETs 20, 30, 40, 42 and the resistor 50 except the output buffer 60 correspond to the reference voltage generator. The p-channel FET 20 has a drain connected to the power supply line with the operating voltage Vdd. The source is grounded between the drain and the source of the n-channel type FET 40 and via the resistor 50. Further, the gate and the source of the FET 20 are connected.

The drain of the p-channel FET 30 is connected to the power supply line, and the source is grounded via the drain-source of the n-channel FET 42. The gates of these two FETs 20, 30 are connected in common. The gate of the FET 40 is connected to the drain of the FET 42, and the gate of the FET 42 is connected to the source of the T40.

Assuming that the current flowing between the drain and the source of the FET 40 is I, when the current I increases, the gate voltage of the FET 42 connected to one end of the resistor 50 increases. As a result, the resistance between the drain and the source of the FET 42 decreases, so that the gate voltage of the FET 40 connected to the drain of the FET 42 decreases, and the current flowing between the drain and the source of the FET 40 decreases. Conversely, when the current I flowing between the drain and the source of the FET 40 decreases, the gate voltage of the FET 42 connected to one end of the resistor 50 decreases. As a result, the resistance between the drain and the source of the FET 42 increases, so that the gate voltage of the FET 40 connected to the drain of the FET 42 increases, and the current flowing between the drain and the source of the FET 40 increases.

As described above, when the current I flowing through the FET 40 changes, the gate voltage of the FET 40 fluctuates so as to suppress the change, so that the current I stabilizes at a predetermined value. In this stable state, the drain potential of the FET 42 also maintains a predetermined value, so that a constant output voltage appears at the output terminal of the output buffer 60.

Configuration and operation of constant current source

In the configuration of the power supply circuit 10 described above, the FETs 20 to 23, 30, 40, and 42 and the resistor 50 constitute a constant current source. Also in this constant current source, the reference voltage generator (FETs 20, 30, 40, 42, and resistor 50) included in the above-described constant voltage source is commonly used. Also, each of the FETs 21, 22, and 23 corresponds to a current driver.

The gates of the p-channel FETs 21, 22, and 23 are commonly connected to the gate of the FET 20. This allows FET 21 and FET 20 A first current mirror circuit is configured. As described above, since a constant current flows between the drain and source of the FET 40, a constant current also flows between the drain and source of the FET 20, and the gate and the source of the FET 20 have a predetermined potential. Therefore, the gate of the FET 21 also maintains a predetermined potential, and a constant current I i flows between the drain and the source. If the gate length L and the gate width W of the FETs 20 and 21 are equal, a current I 1 equal to the current I flowing between the drain and the source of the FET 40 is generated by the FET 21. Also, by making the gate length L and the gate width W of the FET 21 different from the gate length L and the gate width W of the FET 20, a current I i different from the current I flowing between the drain and the source of the FET 40 is obtained. Generated by FET 21.

Similarly, the FET 22 and the FET 20 form a second current mirror circuit. Therefore, if the gate length L and the gate width W of the FETs 20 and 22 are equal, a current I ₂ equal to the current I flowing between the drain and the source of the FET 40 is generated by the FET 22. Also, by making the gate length L and the gate width W of the FET 22 different from the gate length L and the gate width W of the FET 20, a current I ₂ different from the current I flowing between the drain and the source of the FET 40 is generated. Generated by 22.

The third current mirror circuit is constituted by the FET 23 and the FET 20. Therefore, if the gate length L and the gate width W of the FETs 20 and 23 are equal to each other, a current I ₃ equal to the current I flowing between the drain and the source of the FET 40 is generated by the FET 23. Also, by making the gate length L and the gate width W of the FET 23 different from the gate length L and the gate width W of the FET 20, a current I ₃ different from the current I flowing between the drain and the source of the FET 40 is generated. _C generated by 23 As described above, the power supply circuit 10 of the present embodiment generates a predetermined constant voltage and three types of the same or different constant currents. In particular, the reference voltage generator (FET 20, 30, 40, 42, resistor 50) included in the constant voltage source that generates the constant voltage is commonly used in the constant current source that generates the constant current. The circuit scale can be significantly reduced as compared to a case where these constant voltage sources and constant current sources are separately provided. In addition, since the parts that consume power are shared, if a constant current source and a constant voltage source are provided separately, Power consumption can be reduced compared to the case.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, in the above-described embodiment, the configuration in which loads are connected to the respective source sides of the FETs 21, 22, and 23 constituting the constant current source has been described. However, the load is connected to the drain side. You may.

FIG. 2 is a circuit diagram showing a modification of the power supply circuit. The power supply circuit 110 shown in FIG. 2 includes FETs 20, 30, 40, 42, 71 to 73, resistors 50, 81 to 83, and an output buffer 60. The power supply circuit 110 has a configuration in which the FETs 21 to 23 are replaced with FETs 71 to 73 and resistors 81 to 83 in the power supply circuit 10 shown in FIG.

Specifically, a first current mirror circuit is configured by the FET 71 and the FET 40, and a predetermined current I 1 determined by the gate length L and the gate width W of the FET 71 is equal to the drain current of the FET 71. Flow between sources. Likewise, FE T 72 and by the FET 40 and the second current mirror circuit is constituted, FE T 72 gate one preparative length L and the drain of the predetermined current I ₂ is FET 72 determined by the gate width W of the 'source one Flows between A third current mirror circuit is constituted by the FET 73 and the FET 40, and a predetermined current I 3 determined by the gate length L and the gate width W of the FET 73 flows between the drain and the source of the FET 73.

In the above-described embodiment, the constant voltage is generated by one output buffer 60. However, when increasing the allowable current value when supplying the constant voltage, the number of output buffers 60 may be increased. .

FIG. 3 is a circuit diagram showing another modified example of the power supply circuit. The power supply circuit 10A shown in FIG. 3 includes FETs 20 to 23, 30, 40, and 42, a resistor 50, and three output buffers 60. The difference is that the number of output buffers 60 is changed from one to three in the power supply circuit 10 shown in FIG. These three output buffers 60 are all connected to the drain of the FET 42, and can carry a load current within the range of the respective allowable current values. This allows a large load current to flow.

Further, in the above embodiment, three constant current I i, and generates an I _2, 1 ₃ However, the number of generated constant currents may be two or four or more. Industrial applicability

As described above, according to the present invention, a reference voltage generation unit that generates a reference voltage required to generate a constant voltage and a constant current can be commonly used, so that the circuit size can be reduced. At the same time, power consumption can be reduced as compared with a case where the reference voltage generator is provided separately.

Claims

The scope of the claims

1. a reference voltage generator for generating a reference voltage;

An output buffer that generates a predetermined constant voltage corresponding to the reference voltage,

A current driver that generates a predetermined constant current corresponding to the reference voltage;

A power supply circuit comprising:

2. The power supply circuit according to claim 1, wherein the current driver generates a plurality of constant currents.

3. The power supply circuit according to claim 2, wherein the current drive unit has a plurality of FETs that form a current mirror circuit together with an FET included in the reference voltage generation unit when the reference voltage is applied to a gate. .

4. The power supply circuit according to claim 3, wherein a plurality of different constant currents are generated by the current driver by changing a gate length L and a gate width W of each of the plurality of FETs.