WO2002084669A1 - System and method for erase test of integrated circuit device having non-homogeneously sized sectors - Google Patents

System and method for erase test of integrated circuit device having non-homogeneously sized sectors Download PDF

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Publication number
WO2002084669A1
WO2002084669A1 PCT/US2001/045442 US0145442W WO02084669A1 WO 2002084669 A1 WO2002084669 A1 WO 2002084669A1 US 0145442 W US0145442 W US 0145442W WO 02084669 A1 WO02084669 A1 WO 02084669A1
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WIPO (PCT)
Prior art keywords
sector
sectors
time periods
test
time period
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PCT/US2001/045442
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French (fr)
Inventor
Janevoot Naksrikram
Aeksit Suraphak
Jitrayut Junnapart
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Advanced Micro Devices, Inc.
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Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO2002084669A1 publication Critical patent/WO2002084669A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Definitions

  • the present invention relates generally to testing integrated circuit devices such as flash memory devices.
  • the testing can include parametric tests, including testing for short circuits, open circuits, various leakage tests, and various signature tests. Also, the testing can include various performance or functional tests, such as speed tests and erase time tests. Of importance to the present invention is testing a device for erase time.
  • each sector in the device is programmed, and then the device is erased, sector by sector, with the time period required for erasure being recorded for each sector.
  • a test known as Auto Program Disturb Erase (APDE) is performed to cure the leakage, and then the APDE time period is also recorded.
  • a test limit is then calculated that is essentially the average (or, e.g. , 1.5 times the average) of the erase time periods and APDE time periods of all the sectors. If the time periods required for any sector exceed the test limit, the device is rejected.
  • flash memory devices have equally-sized sectors, that is, all the sectors to be tested of flash memory devices are assumed to be of uniform size. Accordingly, a single test limit has been used against which the erase/APDE times of all sectors are compared.
  • flash memory devices can have some sectors of one uniform size (typically of a larger size) and other sectors (boot sectors) of other, non-uniform sizes (typically of smaller sizes and, hence, colloquially referred to as "baby sectors"). In these devices, the smaller baby sectors should have shorter erase times than the larger uniform sectors. Nonetheless, current test procedures still use a single test limit against which all sectors are compared.
  • the present invention recognizes that when a single test limit is used, it is based on times derived from both the uniform sectors and baby sectors and, hence, might be set too low for uniform sectors, thus resulting in a large number of false rejects. Having made the above critical observations, the present invention provides the below-solutions to one or more of the observations.
  • a method for testing a semiconductor device having at least one first sector of a first sector type (e.g. , a uniform sector) and at least one second sector of a second sector type (e.g. , a boot sector) includes measuring at least one first time period, such as erase time and/or APDE time, that is related to erasing the first sector. The method also includes establishing a first test limit based at least in part on the first time period. Further, the method includes measuring at least one second time period related to erasing the second sector, and establishing a second test limit based at least in part on the second time period. The first and second test limits are used to determine whether the device passes or fails an erase test.
  • first time period such as erase time and/or APDE time
  • the device includes many first sectors and many second sectors, and the first test limit is based at least in part on an average of first time periods associated with respective first sectors. Likewise, the second test limit is based at least in part on an average of second time periods associated with respective second sectors.
  • the preferred method can include measuring at least one third time period related to erasing the first sector and measuring at least one fourth time period related to erasing the second sector.
  • the first and second time periods can be erase time periods and the third and fourth time periods can be APDE time periods. Consequently, the first test limit preferably is based on the first and third time periods (uniform sector average erase time and uniform sector average APDE time), while the second test limit is based on the second and fourth time periods (boot sector average erase time and boot sector average APDE time).
  • the preferred method can also determine whether the time period associated with the sector exceeds the test limit associated with the time period of the sector. If it does, the device is rejected. At least one parameter test can also be executed on the device.
  • Figure 1 is a schematic view of a flash memory device having uniform sectors and non-uniform sectors;
  • Figure 2 is a flow chart of the overall logic of the present invention.
  • Figure 3 is a flow chart of the erase test logic; and Figure 4 is a flow chart of the erase test evaluation logic.
  • a semiconductor device more specifically a bootable device, and still more specifically a flash memory device, is shown and generally designated 10.
  • the device includes plural sectors.
  • the sectors labeled “sector 5", “sector 6", and “sector 7" are all uniformly sized, relatively large sectors. This means they all have the same number of memory cells.
  • the sectors labeled “sector 0”, “sector 1", “sector 2”, and “sector 3" are non-uniformly sized, compared to the uniformly sized sectors, are relatively small and, hence, can be referred to as "baby sectors" .
  • the sectors 0-3 can be the same size as each other or, as shown, the sectors 1 and 2 can have the same size, sector 0 can be larger than sector 1, and sector 3 can be larger than sector 0. In any case, the boot sectors are generally smaller than the uniform sectors.
  • Figure 2 shows the overall logic by which the present invention operates.
  • certain parameter tests can be executed on the device 10. These tests include, but are not limited to, tests for open circuits and short circuits, certain electrical leakage tests including in-leakage, and certain device signature tests.
  • performance (functional) tests are conducted, including but not limited to the section erase test described further below.
  • additional parameter tests can be executed if desired/necessary.
  • the erase test logic is shown in Figure 3. Beginning at block 18, all cells in all sectors are programmed, so that the cells can be subsequently erased. Moving to block 20, a DO loop is entered for each sector. At block 22 the programming time period for each sector is recorded, as is the sector type/size.
  • Programming time period can, of course, be recorded during the process at block 18, and sector size/type can likewise be recorded. Moving to block 24, the sector is erased and its erase time period recorded.
  • APDE Auto Program Disturb Erase
  • decision diamond 30 determines whether the last sector has been tested. If not, the next sector is tested starting at block 22. At the end of the process of Figure 3, the test is evaluated at state 32 using the logic of Figure 4.
  • Figure 4 shows the erase test evaluation logic.
  • a DO loop is entered for each sector type/size.
  • each sector type might be defined by sectors having exactly the same size as other sectors in that type.
  • two sector types - uniformly sized memory sectors, and boot sectors regardless of size, might be defined.
  • a test limit for the type under test is defined.
  • the test limit is based on one or more, preferably both of: the average erase time period for sectors in the type, and the average APDE time period for sectors in the type.
  • the test limit is defined to be 1.5 times the sum of the average erase time period plus the average APDE time period.
  • the logic moves to block 38 to enter a DO loop for each sector in the type. Proceeding to decision diamond 40 it is determined whether either one or the sum of both of the sector's erase time period plus APDE time period exceed the test limit. Preferably, the sum of the segment's erase time period and APDE time period are compared to the test limit at decision diamond 40. If the sum exceeds the limit, "FAIL" is returned at block 42 and the device 10 is rejected. Otherwise, the logic moves to decision diamond 44 to determine whether the last sector in the type has been tested, and if not, the next sector is tested starting at decision diamond 40. If the last segment in the type has been tested the logic moves from decision diamond 44 to decision diamond 46 to determine whether the last sector type has been evaluated, and if not the next sector type is tested starting at block 36. Otherwise, the logic ends at state 48.
  • decision diamond 40 it is determined whether either one or the sum of both of the sector's erase time period plus APDE time period exceed the test limit. Preferably, the sum of the segment's erase time period
  • the above logic can be embodied in a computer or other digital processor that is programmed to execute method acts in accordance with the logic, and it can be stored on a computer-readable medium such as a hard disk drive, diskette, optical disk, ROM or RAM, and so on.

Abstract

A system and method for testing a flash memory device (10) having uniform sectors (4, 5, 6) and smaller, "boot" sectors (0, 1, 2) includes determining uniform and boot test limits based on average erase (24) and APDE (28) time periods of the uniform (4, 5, 6) and boot sectors (0-2) respectively. In this way, the erase test results (24) for each sector type is compared (36) against test limits that are based only on that sector type, thereby avoiding excessive false rejects.

Description

SYSTEM AND METHOD FOR ERASE TEST OF INTEGRATED CIRCUIT DEVICE HAVING NON-HOMOGENEOUSLY SIZED SECTORS
TECHNICAL FIELD
The present invention relates generally to testing integrated circuit devices such as flash memory devices.
BACKGROUND ART
Semiconductor devices, including integrated circuit devices such as boot-type devices, are tested prior to shipment to ensure quality control. In the case of boot-type devices known as flash memory devices, the testing can include parametric tests, including testing for short circuits, open circuits, various leakage tests, and various signature tests. Also, the testing can include various performance or functional tests, such as speed tests and erase time tests. Of importance to the present invention is testing a device for erase time.
Specifically, to determine whether a device can be erased adequately, each sector in the device is programmed, and then the device is erased, sector by sector, with the time period required for erasure being recorded for each sector. In the event that any leakage is detected after an erase operation, a test known as Auto Program Disturb Erase (APDE) is performed to cure the leakage, and then the APDE time period is also recorded. A test limit is then calculated that is essentially the average (or, e.g. , 1.5 times the average) of the erase time periods and APDE time periods of all the sectors. If the time periods required for any sector exceed the test limit, the device is rejected.
As recognized by the present invention, for test purposes it has been assumed that flash memory devices have equally-sized sectors, that is, all the sectors to be tested of flash memory devices are assumed to be of uniform size. Accordingly, a single test limit has been used against which the erase/APDE times of all sectors are compared. The present invention understands, however, that flash memory devices can have some sectors of one uniform size (typically of a larger size) and other sectors (boot sectors) of other, non-uniform sizes (typically of smaller sizes and, hence, colloquially referred to as "baby sectors"). In these devices, the smaller baby sectors should have shorter erase times than the larger uniform sectors. Nonetheless, current test procedures still use a single test limit against which all sectors are compared. The present invention recognizes that when a single test limit is used, it is based on times derived from both the uniform sectors and baby sectors and, hence, might be set too low for uniform sectors, thus resulting in a large number of false rejects. Having made the above critical observations, the present invention provides the below-solutions to one or more of the observations.
DISCLOSURE OF INVENTION A method for testing a semiconductor device having at least one first sector of a first sector type (e.g. , a uniform sector) and at least one second sector of a second sector type (e.g. , a boot sector) includes measuring at least one first time period, such as erase time and/or APDE time, that is related to erasing the first sector. The method also includes establishing a first test limit based at least in part on the first time period. Further, the method includes measuring at least one second time period related to erasing the second sector, and establishing a second test limit based at least in part on the second time period. The first and second test limits are used to determine whether the device passes or fails an erase test.
In a preferred embodiment, the device includes many first sectors and many second sectors, and the first test limit is based at least in part on an average of first time periods associated with respective first sectors. Likewise, the second test limit is based at least in part on an average of second time periods associated with respective second sectors.
As indicated above, more than one time period can be used, and preferably both erase time and APDE time are used. Accordingly, the preferred method can include measuring at least one third time period related to erasing the first sector and measuring at least one fourth time period related to erasing the second sector. The first and second time periods can be erase time periods and the third and fourth time periods can be APDE time periods. Consequently, the first test limit preferably is based on the first and third time periods (uniform sector average erase time and uniform sector average APDE time), while the second test limit is based on the second and fourth time periods (boot sector average erase time and boot sector average APDE time).
For each sector, the preferred method can also determine whether the time period associated with the sector exceeds the test limit associated with the time period of the sector. If it does, the device is rejected. At least one parameter test can also be executed on the device.
BRIEF DESCRIPTION OF DRAWINGS
Figure 1 is a schematic view of a flash memory device having uniform sectors and non-uniform sectors; Figure 2 is a flow chart of the overall logic of the present invention;
Figure 3 is a flow chart of the erase test logic; and Figure 4 is a flow chart of the erase test evaluation logic.
BEST MODE FOR CARRYING OUT THE INVENTION Referring initially to Figure 1 , a semiconductor device, more specifically a bootable device, and still more specifically a flash memory device, is shown and generally designated 10. As shown, the device includes plural sectors. The sectors labeled "sector 5", "sector 6", and "sector 7" are all uniformly sized, relatively large sectors. This means they all have the same number of memory cells. On the other hand, the sectors labeled "sector 0", "sector 1", "sector 2", and "sector 3" are non-uniformly sized, compared to the uniformly sized sectors, are relatively small and, hence, can be referred to as "baby sectors" . These sectors are also known as "boot sectors" . The sectors 0-3 can be the same size as each other or, as shown, the sectors 1 and 2 can have the same size, sector 0 can be larger than sector 1, and sector 3 can be larger than sector 0. In any case, the boot sectors are generally smaller than the uniform sectors.
Figure 2 shows the overall logic by which the present invention operates. Commencing at block 12, certain parameter tests can be executed on the device 10. These tests include, but are not limited to, tests for open circuits and short circuits, certain electrical leakage tests including in-leakage, and certain device signature tests. Moving to block 14, performance (functional) tests are conducted, including but not limited to the section erase test described further below. Then, at block 16 additional parameter tests can be executed if desired/necessary.
The erase test logic is shown in Figure 3. Commencing at block 18, all cells in all sectors are programmed, so that the cells can be subsequently erased. Moving to block 20, a DO loop is entered for each sector. At block 22 the programming time period for each sector is recorded, as is the sector type/size.
Programming time period can, of course, be recorded during the process at block 18, and sector size/type can likewise be recorded. Moving to block 24, the sector is erased and its erase time period recorded.
Next, at decision diamond 26 it is determined whether the sector experienced any electrical leakage during erasure, and if so, an Auto Program Disturb Erase (APDE) pulse is generated at block 28 to cure the leakage, i.e. , APDE is applied until the leakage is below a threshold. The time period to conduct the APDE test is recorded, and a routine known as "erase verify" is conducted in accordance with flash memory test principles known in the art to verify that the sector under test is erased.
From block 28 or decision diamond 26 when the test there is negative, the logic moves to decision diamond 30 to determine whether the last sector has been tested. If not, the next sector is tested starting at block 22. At the end of the process of Figure 3, the test is evaluated at state 32 using the logic of Figure 4.
Figure 4 shows the erase test evaluation logic. Commencing at block 34, a DO loop is entered for each sector type/size. For instance, each sector type might be defined by sectors having exactly the same size as other sectors in that type. Or, two sector types - uniformly sized memory sectors, and boot sectors regardless of size, might be defined. In any case, at block 36 a test limit for the type under test is defined. The test limit is based on one or more, preferably both of: the average erase time period for sectors in the type, and the average APDE time period for sectors in the type. In a particularly preferred embodiment, the test limit is defined to be 1.5 times the sum of the average erase time period plus the average APDE time period.
After defining the test limit for the sector type under test, the logic moves to block 38 to enter a DO loop for each sector in the type. Proceeding to decision diamond 40 it is determined whether either one or the sum of both of the sector's erase time period plus APDE time period exceed the test limit. Preferably, the sum of the segment's erase time period and APDE time period are compared to the test limit at decision diamond 40. If the sum exceeds the limit, "FAIL" is returned at block 42 and the device 10 is rejected. Otherwise, the logic moves to decision diamond 44 to determine whether the last sector in the type has been tested, and if not, the next sector is tested starting at decision diamond 40. If the last segment in the type has been tested the logic moves from decision diamond 44 to decision diamond 46 to determine whether the last sector type has been evaluated, and if not the next sector type is tested starting at block 36. Otherwise, the logic ends at state 48.
The above logic can be embodied in a computer or other digital processor that is programmed to execute method acts in accordance with the logic, and it can be stored on a computer-readable medium such as a hard disk drive, diskette, optical disk, ROM or RAM, and so on.
While the particular SYSTEM AND METHOD FOR ERASE TEST OF INTEGRATED CIRCUIT DEVICE HAVING NON-HOMOGENEOUSLY SIZED SECTORS as herein shown and described in detail is fully capable of attaining the above-described objects of the invention, it is to be understood that it is the presently preferred embodiment of the present invention and is thus representative of the subject matter which is broadly contemplated by the present invention, that the scope of the present invention fully encompasses other embodiments which may become obvious to those skilled in the art, and that the scope of the present invention is accordingly to be limited by nothing other than the appended claims, in which reference to an element in the singular is not intended to mean "one and only one" unless explicitly so stated, but rather "one or more". All structural and functional equivalents to the elements of the above-described preferred embodiment that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Moreover, it is not necessary for a device or method to address each and every problem sought to be solved by the present invention, for it to be encompassed by the present claims. Furthermore, no element, component, or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims. No claim element herein is to be construed under the provisions of 35 U.S.C. §112, sixth paragraph, unless the element is expressly recited using the phrase "means for".

Claims

CLAIMSWhat is claimed is:
1. A method for testing a semiconductor device having at least one first sector of a first sector type and at least one second sector of a second sector type, comprising: measuring at least one first time period related to erasing the first sector; establishing at least a first test limit based at least in part on the first time period; measuring at least one second time period related to erasing the second sector; establishing at least a second test limit based at least in part on the second time period; and using the first and second test limits, determining whether the device passes or fails an erase test.
2. The method of Claim 1, wherein the device comprises plural first sectors and plural second sectors, and the first test limit is based at least in part on an average of first time periods associated with respective first sectors and the second test limit is based at least in part on an average of second time periods associated with respective second sectors.
3. The method of Claim 1 , further comprising measuring at least one third time period related to erasing the first sector and measuring at least one fourth time period related to erasing the second sector, the first and second time periods being erase time periods and the third and fourth time periods being APDE time periods, the first test limit being based at least partially on at least one of: the first and third time periods, the second test limit being based at least partially on at least one of: the second and fourth time periods.
4. The method of Claim 3, wherein the first test limit is based at least partially on both of the first and third time periods, and the second test limit is based at least partially on both of the second and fourth time periods.
5. The method of Claim 2, further comprising measuring at least third time periods related to erasing respective first sectors and measuring at least fourth time periods related to erasing respective second sectors, the first and second time periods being erase time periods and the third and fourth time periods being APDE time periods, the first test limit being based at least partially on at least one of: the first and third time periods, the second test limit being based at least partially on at least one of: the second and fourth time periods.
6. The method of Claim 5, wherein the first test limit is based at least partially on both of the first and third time periods, and the second test limit is based at least partially on both of the second and fourth time periods.
7. The method of Claim 1 , wherein the act of using includes determining, for each sector, whether the time period associated with the sector exceeds the test limit associated with the time period of the sector.
8. The method of Claim 1 , further comprising executing at least one parameter test on the device.
9. The method of Claim 1, wherein the second sector is a boot sector.
10. A device for testing a semiconductor device having at least one first sector of a first sector type and at least one second sector of a second sector type, comprising: means for measuring at least one first time period related to erasing the first sector; means for establishing at least a first test limit based at least in part on the first time period; means for measuring at least one second time period related to erasing the second sector; means for establishing at least a second test limit based at least in part on the second time period; and means for determining, using the first and second test limits, whether the device passes or fails an erase test.
PCT/US2001/045442 2001-04-16 2001-10-30 System and method for erase test of integrated circuit device having non-homogeneously sized sectors WO2002084669A1 (en)

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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7805701B1 (en) * 2004-12-07 2010-09-28 National Semiconductor Corporation Universal two-input logic gate that is configurable and connectable in an integrated circuit by a single mask layer adjustment
US20070141731A1 (en) * 2005-12-20 2007-06-21 Hemink Gerrit J Semiconductor memory with redundant replacement for elements posing future operability concern
US7567472B2 (en) 2006-04-12 2009-07-28 Micron Technology, Inc. Memory block testing
CN100576356C (en) * 2006-12-21 2009-12-30 中芯国际集成电路制造(上海)有限公司 Reduce the method for storage unit write-in disorder
US9830998B2 (en) 2015-05-19 2017-11-28 Sandisk Technologies Llc Stress patterns to detect shorts in three dimensional non-volatile memory

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5581510A (en) * 1994-06-28 1996-12-03 Mitsubishi Denki Kabushiki Kaisha Method of testing flash memory
US5615148A (en) * 1995-03-28 1997-03-25 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
EP0844619A2 (en) * 1996-11-21 1998-05-27 Nec Corporation Nonvolatile semiconductor memory device having test circuit for testing erasing function thereof

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05283708A (en) * 1992-04-02 1993-10-29 Mitsubishi Electric Corp Nonvolatile semiconductor memory, its manufacturing method and testing method
JP3193810B2 (en) * 1993-08-31 2001-07-30 富士通株式会社 Nonvolatile semiconductor memory device and test method therefor
US5646948A (en) * 1993-09-03 1997-07-08 Advantest Corporation Apparatus for concurrently testing a plurality of semiconductor memories in parallel
JPH07201191A (en) * 1993-12-28 1995-08-04 Toshiba Corp Nonvolatile semiconductor memory device
US5675546A (en) * 1996-06-07 1997-10-07 Texas Instruments Incorporated On-chip automatic procedures for memory testing

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5581510A (en) * 1994-06-28 1996-12-03 Mitsubishi Denki Kabushiki Kaisha Method of testing flash memory
US5615148A (en) * 1995-03-28 1997-03-25 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
EP0844619A2 (en) * 1996-11-21 1998-05-27 Nec Corporation Nonvolatile semiconductor memory device having test circuit for testing erasing function thereof

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