WO2002058164A2 - Gan layer on a substrate with an amorphous layer - Google Patents

Gan layer on a substrate with an amorphous layer Download PDF

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Publication number
WO2002058164A2
WO2002058164A2 PCT/US2001/046663 US0146663W WO02058164A2 WO 2002058164 A2 WO2002058164 A2 WO 2002058164A2 US 0146663 W US0146663 W US 0146663W WO 02058164 A2 WO02058164 A2 WO 02058164A2
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Prior art keywords
layer
monocrystalline
semiconductor structure
material layer
substrate
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PCT/US2001/046663
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French (fr)
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WO2002058164A3 (en
Inventor
Jamal Ramdani
Lyndee L. Hilt
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Motorola, Inc.
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Priority to AU2002227245A priority Critical patent/AU2002227245A1/en
Publication of WO2002058164A2 publication Critical patent/WO2002058164A2/en
Publication of WO2002058164A3 publication Critical patent/WO2002058164A3/en
Priority to US11/117,349 priority patent/US7211852B2/en

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    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Definitions

  • This invention relates generally to semiconductor structures and devices and to a method for their fabrication, and more specifically to fabrication of semiconductor structures formed of GaN films on compliant substrates.
  • Semiconductor devices typically include multiple layers of conductive, insulating, and semiconductive layers. Often, the desirable properties of such layers improve with the crystallinity of the layer. For example, the electron mobility and optical properties of semiconductive layers improves as the crystallinity of the layer increases. Similarly, the free electron concentration of conductive layers and the electron charge displacement and electron energy recoverability of insulative or dielectric films improves as the crystallinity of these layers increases. For many years, attempts have been made to grow various monolithic thin films on a foreign substrate, such as silicon (Si). To achieve optimal characteristics of the various monolithic layers, however, a monocrystalline film of high crystalline quality is desired.
  • a foreign substrate such as silicon (Si).
  • a variety of semiconductor devices could advantageously be fabricated in that film at a low cost compared to the cost of fabricating such devices beginning with a bulk wafer of semiconductor material or in an epitaxial film of such material on a bulk wafer of semiconductor material.
  • a thin film of high quality monocrystalline material could be realized beginning with a bulk wafer such as a silicon wafer, an integrated device structure could be achieved that took advantage of the best properties of both the silicon and the high quality monocrystalline material. Accordingly, a need exists for a semiconductor structure that provides a high quality monocrystalline film or layer over another monocrystalline material and for a process for making such a structure. This structure and process could have extensive applications.
  • GaN has a large, direct bandgap, structural stability and high thermal stability which makes it suitable for a wide range of electrical and optical device applications such as lasers, light emitting devices in the blue and green wavelengths, high temperature devices and solar blind detectors.
  • GaN film growth is carried out on sapphire substrates or SiC substrates, both substrates of which present disadvantages. SiC substrates are of small size and are expensive.
  • GaN on sapphire is hexagonal and exhibits lower mobility than cubic GaN.
  • sapphire has a lattice constant and thermal conductivity significantly different from HI-N nitrides such as Ga ⁇ and is electrically insulating. For example, the lattice constant for Ga ⁇ differs by approximately 13-16% from that of sapphire.
  • Ga ⁇ layers Another disadvantage of typical Ga ⁇ films grown on sapphire is the high number of defect dislocations in the Ga ⁇ layers. These defects impact the electrical and optical performance of the Ga ⁇ devices. For example, in optical devices, the defects act as scattering centers requiring a higher laser threshold current density. In electrical devices, dislocations can create deep defect energy levels that increase the leakage current.
  • FIGS. 1, 2, and 3 illustrate schematically, in cross section, device structures in accordance with various embodiments of the invention
  • FLG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer
  • FIG. 5 illustrates a high resolution Transmission Electron Micrograph of a structure including a monocrystalline accommodating buffer layer
  • FIG. 6 illustrates an x-ray diffraction spectrum of a structure including a monocrystalline accommodating buffer layer
  • FIG. 7 illustrates a high resolution Transmission Electron Micrograph of a structure including an amorphous oxide layer
  • FIG. 8 illustrates an x-ray diffraction spectrum of a structure including an amorphous oxide layer
  • FIGS. 9A-9D illustrate schematically, in cross-section, the formation of a device structure in accordance with another embodiment of the invention.
  • FIGS. 10A-10D illustrate a probable molecular bonding structure of the device structures illustrated in FIGS. 9A-9D;
  • FIGS. 11-14 illustrate schematically, in cross-section, the formation of a device structure in accordance with still another embodiment of the invention;
  • FIGS. 15-17 illustrate schematically, in cross-section, the formation of yet another embodiment of a device structure in accordance with the invention.
  • FIGS. 18-20 illustrate schematically, in cross-section, the formation of another exemplary embodiment of a semiconductor structure fabricated on a semiconductor substrate according to the present invention.
  • FIG. 1 illustrates schematically, in cross section, a portion of a semiconductor structure 20 in accordance with an embodiment of the invention.
  • Semiconductor structure 20 includes a monocrystalline substrate 22, accommodating buffer layer 24 comprising a monocrystalline material, and a monocrystalline material layer 26.
  • monocrystalline shall have the meaning commonly used within the semiconductor industry.
  • the term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.
  • structure 20 also includes an amorphous intermediate layer 28 positioned between substrate 22 and accommodating buffer layer 24.
  • Structure 20 may also include a template layer 30 between the accommodating buffer layer and monocrystalline material layer 26.
  • the template layer helps to initiate the growth of the monocrystalline material layer on the accommodating buffer layer.
  • the amorphous intermediate layer helps to relieve the strain in the accommodating buffer layer and by doing so, aids in the growth of a high crystalline quality accommodating buffer layer.
  • Substrate 22 in accordance with an embodiment of the invention, is a monocrystalline semiconductor or compound semiconductor wafer, preferably of large diameter.
  • the wafer can be of, for example, a material from Group IN of the periodic table, and preferably a material from Group IVB.
  • Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like.
  • substrate 22 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry.
  • Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate.
  • amorphous intermediate layer 28 is grown on substrate 22 at the interface between substrate 22 and the growing accommodating buffer layer by the oxidation of substrate 22 during the growth of layer 24.
  • the amorphous intermediate layer serves to relieve strain that might otherwise occur in the monocrystalline accommodating buffer layer as a result of differences in the lattice constants of the substrate and the buffer layer.
  • lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by the amorphous intermediate layer, the strain may cause defects in the crystalline structure of the accommodating buffer layer.
  • monocrystalline material layer 26 which may comprise a semiconductor material, a compound semiconductor material, or another type of material such as a metal or a non- metal.
  • Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying substrate and with the overlying material layer.
  • the material could be an oxide or nitride having a lattice structure closely matched to the substrate and to the subsequently applied monocrystalline material layer.
  • Materials that are suitable for the accommodating buffer layer include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for the accommodating buffer layer.
  • metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates
  • these materials are insulators, although strontium ruthenate, for example, is a conductor.
  • these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitrides may include three or more different metallic elements.
  • Amorphous interface layer 28 is preferably an oxide formed by the oxidation of the surface of substrate 22, and more preferably is composed of a silicon oxide.
  • the thickness of layer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate 22 and accommodating buffer layer 24.
  • layer 28 has a thickness in the range of approximately 0.5-5 nm.
  • the material for monocrystalline material layer 26 can be selected, as desired, for a particular structure or application.
  • the monocrystalline material of layer 26 may comprise a compound semiconductor which can be selected, as needed for a particular semiconductor structure, from any of the Group I-QA and VA elements (TTT-V semiconductor compounds), mixed TE-V compounds, Group H(A or B) and VIA elements (UNI semiconductor compounds), and mixed II-NI compounds.
  • monocrystalline material layer 26 may also comprise other semiconductor materials, metals, or non-metal materials which are used in the formation of semiconductor structures, devices and/or integrated circuits.
  • template 30 is discussed below. Suitable template materials chemically bond to the surface of the accommodating buffer layer 24 at selected sites and provide sites for the nucleation of the epitaxial growth of monocrystalline material layer 26. When used, template layer 30 has a thickness ranging from about 1 to about 10 monolayers.
  • FIG. 2 illustrates, in cross section, a portion of a semiconductor structure 40 in accordance with a further embodiment of the invention.
  • Structure 40 is similar to the previously described semiconductor structure 20, except that an additional buffer layer 32 is positioned between accommodating buffer layer 24 and monocrystalline material layer 26.
  • the additional buffer layer is positioned between template layer 30 and the overlying layer of monocrystalline material.
  • the additional buffer layer formed of a semiconductor or compound semiconductor material when the monocrystalline material layer 26 comprises a semiconductor or compound semiconductor material, serves to provide a lattice compensation when the lattice constant of the accommodating buffer layer cannot be adequately matched to the overlying monocrystalline semiconductor or compound semiconductor material layer.
  • FIG. 3 schematically illustrates, in cross section, a portion of a semiconductor structure 34 in accordance with another exemplary embodiment of the invention. Structure
  • structure 34 is similar to structure 20, except that structure 34 includes an amorphous layer 36, rather than accommodating buffer layer 24 and amorphous interface layer 28, and an additional monocrystalline layer 38.
  • amorphous layer 36 may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above. Monocrystalline layer 38 is then formed (by epitaxial growth) overlying the monocrystalline accommodating buffer layer. The accommodating buffer layer is then exposed to an anneal process to convert the monocrystalline accommodating buffer layer to an amorphous layer. Amorphous layer 36 formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate. Thus, layer 36 may comprise one or two amorphous layers. Formation of amorphous layer 36 between substrate 22 and additional monocrystalline layer 26 (subsequent to layer 38 formation) relieves stresses between layers 22 and 38 and provides a true compliant substrate for subsequent processing-e.g., monocrystalline material layer 26 formation.
  • Additional monocrystalline layer 38 may include any of the materials described throughout this application in connection with either of monocrystalline material layer 26 or additional buffer layer 32.
  • layer 38 may include monocrystalline
  • additional monocrystalline layer 38 serves as an anneal cap during layer 36 formation and as a template for subsequent monocrystalline layer 26 formation. Accordingly, layer 38 is preferably thick enough to provide a suitable template for layer 26 growth (at least one monolayer) and thin enough to allow layer 38 to form as a substantially defect free monocrystalline material.
  • additional monocrystalline layer 38 comprises monocrystalline material (e.g., a material discussed above in connection with monocrystalline layer 26) that is thick enough to form devices within layer 38.
  • monocrystalline material e.g., a material discussed above in connection with monocrystalline layer 26
  • a semiconductor structure in accordance with the present invention does not include monocrystalline material layer 26.
  • the semiconductor structure in accordance with this embodiment only includes one monocrystalline layer disposed above amorphous oxide layer 36.
  • monocrystalline substrate 22 is a silicon substrate oriented in the (100) direction.
  • the silicon substrate can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200-300 mm.
  • accommodating buffer layer 24 is a monocrystalline layer of S ⁇ z B ⁇ .JTi 3 where z ranges from 0 to 1 and the amorphous intermediate layer is a layer of silicon oxide (SiO x ) formed at the interface between the silicon substrate and the accommodating buffer layer. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formed layer 26.
  • the accommodating buffer layer can have a thickness of about 2 to about 100 nanometers (nm) and preferably has a thickness of about 5 nm. In general, it is desired to have an accommodating buffer layer thick enough to isolate the compound semiconductor layer from the substrate to obtain the desired electrical and optical properties. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed.
  • the amorphous intermediate layer of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1 to 2 nm.
  • monocrystalline material layer 26 is a compound semiconductor layer of gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs) having a thickness of about 1 nm to about 100 micrometers ( ⁇ m) and preferably a thickness of about 0.5 ⁇ to 10 ⁇ m. The thickness generally depends on the application for which the layer is being prepared.
  • a template layer is formed by capping the oxide layer.
  • the template layer is preferably 1-10 monolayers of Ti-As, Sr-O-As, Sr-Ga-O, or Sr-Al-O. By way of a preferred example, 1-2 monolayers of Ti-As or Sr-Ga-O have been illustrated to successfully grow GaAs layers.
  • Example 2 This embodiment of the invention is an example of structure 40 illustrated in FIG. 2.
  • Substrate 22, accommodating buffer layer 24, and monocrystalline material layer 26 can be similar to those described in example 1.
  • an additional buffer layer 32 serves to alleviate any strains that might result from a mismatch of the crystal lattice of the accommodating buffer layer and the lattice of the monocrystalline material.
  • Buffer layer 32 can be a layer of germanium or a GaAs, an aluminum gallium arsenide (AlGaAs), an indium gallium phosphide (InGaP), an aluminum gallium phosphide (AlGaP), an indium gallium arsenide (InGaAs), an aluminum indium phosphide (AllnP), a gallium arsenide phosphide (GaAsP), or an indium gallium phosphide (InGaP) strain compensated superlattice.
  • buffer layer 32 includes a GaAs ⁇ P ! - x superlattice, wherein the value of x ranges from 0 to 1.
  • buffer layer 32 includes an InyGa ⁇ y P superlattice, wherein the value of y ranges from 0 to 1.
  • the lattice constant is varied from bottom to top across the superlattice to create a match between lattice constants of the underlying oxide and the overlying monocrystalline material which in this example is a compound semiconductor material.
  • the compositions of other compound semiconductor materials, such as those listed above, may also be similarly varied to manipulate the lattice constant of layer 32 in a like manner.
  • the superlattice can have a thickness of about 50-500 nm and preferably has a thickness of about 100-200 nm.
  • buffer layer 32 can be a layer of monocrystalline germanium having a thickness of 1-50 nm and preferably having a thickness of about 2-20 nm.
  • a template layer of either germanium- strontium (Ge-Sr) or germanium-titanium (Ge-Ti) having a thickness of about one monolayer can be used as a nucleating site for the subsequent growth of the monocrystalline material layer which in this example is a compound semiconductor material.
  • the formation of the oxide layer is capped with either a monolayer of strontium or a monolayer of titanium to act as a nucleating site for the subsequent deposition of the monocrystalline germanium.
  • the monolayer of strontium or titanium provides a nucleating site to which the first monolayer of germanium can bond.
  • Example 3 This example provides exemplary materials useful in structure 34, as illustrated in FIG. 3.
  • Substrate material 22, template layer 30, and monocrystalline material layer 26 may be the same as those described above in connection with example 1.
  • Amorphous layer 36 is an amorphous oxide layer which is suitably formed of a combination of amorphous intermediate layer materials (e.g., layer 28 materials as described above) and accommodating buffer layer materials (e.g., layer 24 materials as described above).
  • amorphous layer 36 may include a combination of SiO x and SrzBai-z TiO 3 (where z ranges from 0 to l),which combine or mix, at least partially, during an anneal process to form amorphous oxide layer 36.
  • amorphous layer 36 may vary from application to application and may depend on such factors as desired insulating properties of layer 36, type of monocrystalline material comprising layer 26, and the like. In accordance with one exemplary aspect of the present embodiment, layer 36 thickness is about 2 nm to about 100 nm, preferably about 2-10 nm, and more preferably about 5-6 nm.
  • Layer 38 comprises a monocrystalline material that can be grown epitaxially over a monocrystalline oxide material such as material used to form accommodating buffer layer 24.
  • layer 38 includes the same materials as those comprising layer 26.
  • layer 38 also includes GaAs.
  • layer 38 may include materials different from those used to form layer 26.
  • layer 38 is about 1 monolayer to about 100 nm thick.
  • substrate 22 is a monocrystalline substrate such as a monocrystalline silicon or gallium arsenide substrate.
  • the crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation.
  • accommodating buffer layer 24 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation.
  • the lattice constants of the accommodating buffer layer and the monocrystalline substrate must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved.
  • the terms "substantially equal” and “substantially matched” mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer.
  • HG. 4 illustrates graphically the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal.
  • Curve 42 illustrates the boundary of high crystalline quality material. The area to the right of curve 42 represents layers that have a large number of defects. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved.
  • substrate 22 is a (100) or (111) oriented monocrystalline silicon wafer and accommodating buffer layer 24 is a layer of strontium barium titanate.
  • Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material by 45° with respect to the crystal orientation of the silicon substrate wafer.
  • the inclusion in the structure of amorphous interface layer 28, a silicon oxide layer in this example, if it is of sufficient thickness, serves to reduce strain in the titanate monocrystalline layer that might result from any mismatch in the lattice constants of the host silicon wafer and the grown titanate layer.
  • a high quality, thick, monocrystalline titanate layer is achievable.
  • layer 26 is a layer of epitaxially grown monocrystalline material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation.
  • the lattice constant of layer 26 differs from the lattice constant of substrate 22.
  • the accommodating buffer layer must be of high crystalline quality.
  • the host material is a strontium or barium zirconate or a strontium or barium hafnate or barium tin oxide and the compound semiconductor layer is indium phosphide or gallium indium arsenide or aluminum indium arsenide
  • substantial matching of crystal lattice constants can be achieved by rotating the orientation of the grown crystal layer by 45° with respect to the host oxide crystal.
  • a crystalline semiconductor buffer layer between the host oxide and the grown monocrystalline material layer can be used to reduce strain in the grown monocrystalline material layer that might result from small differences in lattice constants. Better crystalline quality in the grown monocrystalline material layer can thereby be achieved.
  • the following example illustrates a process, in accordance with one embodiment of the invention, for fabricating a semiconductor structure such as the structures depicted in HGS. 1 - 3.
  • the process starts by providing a monocrystalline semiconductor substrate comprising silicon or germanium.
  • the semiconductor substrate is a silicon wafer having a (100) orientation.
  • the substrate is preferably oriented on axis or, at most, about 4° off axis.
  • At least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures.
  • the term "bare" in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material.
  • bare silicon is highly reactive and readily forms a native oxide.
  • the term "bare" is intended to encompass such a native oxide.
  • a thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process in accordance with the invention.
  • the native oxide layer In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline substrate, the native oxide layer must first be removed to expose the crystalline structure of the underlying substrate. The following process is preferably carried out by molecular beam epitaxy (MBE), although other epitaxial processes may also be used in accordance with the present invention.
  • MBE molecular beam epitaxy
  • the native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus.
  • strontium the substrate is then heated to a temperature of about 850° C to cause the strontium to react with the native silicon oxide layer.
  • the strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface.
  • the resultant surface which exhibits an ordered 2x1 structure, includes strontium, oxygen, and silicon.
  • the ordered 2x1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide.
  • the template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer.
  • the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkali earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 850°C. At this temperature a solid state reaction takes place between the strontium oxide and the native silicon oxide causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer.
  • an alkali earth metal oxide such as strontium oxide, strontium barium oxide, or barium oxide
  • the substrate is cooled to a temperature in the range of about 200-800°C and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy.
  • the MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources.
  • the ratio of strontium and titanium is approximately 1:1.
  • the partial pressure of oxygen is initially set at a minimum value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value.
  • the overpressure of oxygen causes the growth of an amorphous silicon oxide layer at the interface between the underlying substrate and the growing strontium titanate layer.
  • the growth of the silicon oxide layer results from the diffusion of oxygen through the growing strontium titanate layer to the interface where the oxygen reacts with silicon at the surface of the underlying substrate.
  • the strontium titanate grows as an ordered monocrystal with the crystalline orientation rotated by 45° with respect to the ordered 2x1 crystalline structure of the underlying substrate. Strain that otherwise might exist in the strontium titanate layer because of the small mismatch in lattice constant between the silicon substrate and the growing crystal is relieved in the amorphous silicon oxide intermediate layer.
  • the monocrystalline strontium titanate is capped by a template layer that is conducive to the subsequent growth of an epitaxial layer of a desired monocrystalline material.
  • the MBE growth of the strontium titanate monocrystalline layer can be capped by terminating the growth with 1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen, 1-2 monolayers of strontium, or with 1-2 monolayers of strontium-oxygen.
  • arsenic is deposited to form a Ti-As bond, a Ti-O-As bond or a Sr-O-As.
  • gallium arsenide monocrystalline layer is subsequently introduced to the reaction with the arsenic and gallium arsenide forms.
  • gallium can be deposited on the capping layer to form a Sr-O- Ga bond, and arsenic is subsequently introduced with the gallium to form the GaAs.
  • FIG. 5 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with one embodiment of the present invention.
  • Single crystal SrTiO 3 accommodating buffer layer 24 was grown epitaxially on silicon substrate 22. During this growth process, amorphous interfacial layer 28 is formed which relieves strain due to lattice mismatch.
  • GaAs compound semiconductor layer 26 was then grown epitaxially using template layer 30.
  • FIG. 6 illustrates an x-ray diffraction spectrum taken on a structure including GaAs monocrystalline layer 26 comprising GaAs grown on silicon substrate 22 using accommodating buffer layer 24.
  • the peaks in the spectrum indicate that both the accommodating buffer layer 24 and GaAs compound semiconductor layer 26 are single crystal and (100) orientated.
  • the structure illustrated in FIG. 2 can be formed by the process discussed above with the addition of an additional buffer layer deposition step.
  • the buffer layer is formed overlying the template layer before the deposition of the monocrystalline material layer. If the buffer layer is a monocrystalUne material comprising a compound semiconductor superlattice, such a superlattice can be deposited, by MBE for example, on the template described above. If instead the buffer layer is a monocrystalline material layer comprising a layer of germanium, the process above is modified to cap the strontium titanate monocrystalUne layer with a final layer of either strontium or titanium and then by depositing germanium to react with the strontium or titanium. The germanium buffer layer can then be deposited directly on this template.
  • Structure 34 may be formed by growing an accommodating buffer layer, forming an amorphous oxide layer over substrate 22, and growing semiconductor layer 38 over the accommodating buffer layer, as described above.
  • the accommodating buffer layer and the amorphous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amorphous, thereby forming an amorphous layer such that the combination of the amorphous oxide layer and the now amorphous accommodating buffer layer form a single amorphous oxide layer 36.
  • Layer 26 is then subsequently grown over layer 38.
  • the anneal process may be carried out subsequent to growth of layer 26.
  • layer 36 is formed by exposing substrate 22, the accommodating buffer layer, the amorphous oxide layer, and monocrystalline layer 38 to a rapid thermal anneal process with a peak temperature of about 700°C to about 1000°C and a process time of about 5 seconds to about 10 minutes.
  • suitable anneal processes may be employed to convert the accommodating buffer layer to an amorphous layer in accordance with the present invention.
  • laser annealing, electron beam annealing, or "conventional" thermal annealing processes in the proper environment
  • an overpressure of one or more constituents of layer 30 may be required to prevent degradation of layer 38 during the anneal process.
  • the anneal environment preferably includes an overpressure of arsenic to mitigate degradation of layer 38.
  • layer 38 of structure 34 may include any materials suitable for either of layers 32 or 26. Accordingly, any deposition or growth methods described in connection with either layer 32 or 26, may be employed to deposit layer 38.
  • FIG. 7 is a high resolution TEM of semiconductor material manufactured in accordance with the embodiment of the invention illustrated in FIG. 3.
  • a single crystal SrTiO 3 accommodating buffer layer was grown epitaxially on silicon substrate 22. During this growth process, an amorphous interfacial layer forms as described above.
  • additional monocrystalline layer 38 comprising a compound semiconductor layer of GaAs is formed above the accommodating buffer layer and the accommodating buffer layer is exposed to an anneal process to form amorphous oxide layer 36.
  • FIG. 8 illustrates an x-ray diffraction spectrum taken on a structure including additional monocrystalline layer 38 comprising a GaAs compound semiconductor layer and amorphous oxide layer 36 formed on silicon substrate 22.
  • the peaks in the spectrum indicate that GaAs compound semiconductor layer 38 is single crystal and (100) orientated and the lack of peaks around 40 to 50 degrees indicates that layer 36 is amorphous.
  • the process described above illustrates a process for forming a semiconductor structure including a silicon substrate, an overlying oxide layer, and a monocrystalline material layer comprising a gallium arsenide compound semiconductor layer by the process of molecular beam epitaxy.
  • the process can also be carried out by the process of chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), migration enhanced epitaxy (MEE), atomic layer epitaxy (ALE), physical vapor deposition (PVD), chemical solution deposition (CSD), pulsed laser deposition (PLD), or the like.
  • CVD chemical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • MEE migration enhanced epitaxy
  • ALE atomic layer epitaxy
  • PVD physical vapor deposition
  • CSD chemical solution deposition
  • PLD pulsed laser deposition
  • other monocrystalline accommodating buffer layers such as alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown.
  • monocrystalline material layers comprising other III-N and II-NI monocrystalline compound semiconductors, semiconductors, metals and non-metals can be deposited overlying the monocrystalline oxide accommodating buffer layer.
  • monocrystalline material layer and monocrystalline oxide accommodating buffer layer uses an appropriate template for initiating the growth of the monocrystalline material layer. For example, if the accommodating buffer layer is an alkaline earth metal zirconate, the oxide can be capped by a thin layer of zirconium.
  • zirconium can be followed by the deposition of arsenic or phosphorus to react with the zirconium as a precursor to depositing indium gallium arsenide, indium aluminum arsenide, or indium phosphide respectively.
  • the monocrystalline oxide accommodating buffer layer is an alkaline earth metal hafnate, the oxide layer can be capped by a thin layer of hafnium.
  • the deposition of hafnium is followed by the deposition of arsenic or phosphorous to react with the hafnium as a precursor to the growth of an indium gallium arsenide, indium aluminum arsenide, or indium phosphide layer, respectively.
  • strontium titanate can be capped with a layer of strontium or strontium and oxygen and barium titanate can be capped with a layer of barium or barium and oxygen.
  • Each of these depositions can be followed by the deposition of arsenic or phosphorus to react with the capping material to form a template for the deposition of a monocrystalline material layer comprising compound semiconductors such as indium gallium arsenide, indium aluminum arsenide, or indium phosphide.
  • FIGS. 9A-9D The formation of a device structure in accordance with another embodiment of the invention is illustrated schematically in cross-section in FIGS. 9A-9D.
  • this embodiment of the invention involves the process of forming a compliant substrate utilizing the epitaxial growth of single crystal oxides, such as the formation of accommodating buffer layer 24 previously described with reference to FIGS. 1 and 2 and amorphous layer 36 previously described with reference to FIG. 3, and the formation of a template layer 30.
  • the embodiment illustrated in FIGS. 9A-9D utilizes a template that includes a surfactant to facilitate layer-by-layer monocrystalline material growth.
  • an amorphous intermediate layer 58 is grown on substrate 52 at the interface between substrate 52 and a growing accommodating buffer layer 54, which is preferably a monocrystalline crystal oxide layer, by the oxidation of substrate 52 during the growth of layer 54.
  • Layer 54 is preferably a monocrystalline oxide material such as a monocrystalline layer of SrJBa z TiOs where z ranges from 0 to 1.
  • layer 54 may also comprise any of those compounds previously described with reference layer 24 in FIGS. 1-2 and any of those compounds previously described with reference to layer 36 in FIG. 3 which is formed from layers 24 and 28 referenced in FIGS. 1 and 2.
  • Layer 54 is grown with a strontium (Sr) terminated surface represented in FIG. 9A by hatched line 55 which is followed by the addition of a template layer 60 which includes a surfactant layer 61 and capping layer 63 as illustrated in FIGS. 9B and 9C.
  • Surfactant layer 61 may comprise, but is not limited to, elements such as Al, In and Ga, but will be dependent upon the composition of layer 54 and the overlying layer of monocrystalline material for optimal results.
  • aluminum (Al) is used for surfactant layer 61 and functions to modify the surface and surface energy of layer 54.
  • surfactant layer 61 is epitaxially grown, to a thickness of one to two monolayers, over layer 24 as illustrated in FIG.
  • MBE molecular beam epitaxy
  • CND chemical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • MEE migration enhanced epitaxy
  • ALE atomic layer epitaxy
  • PVD physical vapor deposition
  • CSSD chemical solution deposition
  • PLD pulsed laser deposition
  • Surfactant layer 61 is then exposed to a halogen such as arsenic, for example, to form capping layer 63 as illustrated in FIG. 9C.
  • Surfactant layer 61 may be exposed to a number of materials to create capping layer 63 such as elements which include, but are not limited to, As, P, Sb and ⁇ .
  • Surfactant layer 61 and capping layer 63 combine to form template layer 60.
  • Monocrystalline material layer 66 which in this example is a compound semiconductor such as GaAs, is then deposited via MBE, CND, MOCVD, MEE, ALE, PVD, CSD, PLD, and the like to form the final structure illustrated in FIG. 9D.
  • FIGS. 10A-10D illustrate possible molecular bond structures for a specific example of a compound semiconductor structure formed in accordance with the embodiment of the invention illustrated in FIGS. 9A-9D. More specifically, FIGS. 10A-10D illustrate the growth of GaAs (layer 66) on the strontium terminated surface of a strontium titanate monocrystalline oxide (layer 54) using a surfactant containing template (layer 60).
  • a monocrystalline material layer 66 such as GaAs on an accommodating buffer layer 54 such as a strontium titanium oxide over amorphous interface layer 58 and substrate layer 52 both of which may comprise materials previously described with reference to layers 28 and 22, respectively in FIGS. 1 and 2, illustrates a critical thickness of about 1000 angstroms where the two-dimensional (2D) and three-dimensional (3D) growth shifts because of the surface energies involved.
  • a critical thickness of about 1000 angstroms where the two-dimensional (2D) and three-dimensional (3D) growth shifts because of the surface energies involved.
  • FIG. 10A illustrates the molecular bond structure of a strontium terminated surface of a strontium titanate monocrystalline oxide layer.
  • An aluminum surfactant layer is deposited on top of the strontium terminated surface and bonds with that surface as illustrated in FIG. 10B, which reacts to form a capping layer comprising a monolayer of Al 2 Sr having the molecular bond structure illustrated in FIG. 10B which forms a diamond-like structure with an sp 3 hybrid terminated surface that is compliant with compound semiconductors such as GaAs.
  • the structure is then exposed to As to form a layer of AlAs as shown in FIG. IOC.
  • GaAs is then deposited to complete the molecular bond structure illustrated in FIG. 10D which has been obtained by 2D growth.
  • the GaAs can be grown to any thickness for forming other semiconductor structures, devices, or integrated circuits.
  • Alkaline earth metals such as those in Group HA are those elements preferably used to form the capping surface of the monocrystalline oxide layer 24 because they are capable of forming a desired molecular structure with aluminum.
  • a surfactant containing template layer aids in the formation of a compliant substrate for the monolithic integration of various material layers including those comprised of Group III-V compounds to form high quality semiconductor structures, devices and integrated circuits.
  • a surfactant containing template may be used for the monolithic integration of a monocrystalline material layer such as a layer comprising Germanium (Ge), for example, to form high efficiency photocells.
  • a device structure in accordance with still another embodiment of the invention is illustrated in cross-section. This embodiment utilizes the formation of a compliant substrate which relies on the epitaxial growth of single crystal oxides on silicon followed by the epitaxial growth of single crystal silicon onto the oxide.
  • An accommodating buffer layer 74 such as a monocrystalline oxide layer is first grown on a substrate layer 72, such as silicon, with an amorphous interface layer 28 as illustrated in FIG. 11.
  • Monocrystalline oxide layer 74 may be comprised of any of those materials previously discussed with reference to layer 24 in FIGS. 1 and 2, while amorphous interface layer 78 is preferably comprised, of any of those materials previously described with reference to the layer 28 illustrated in FIGS. 1 and 2.
  • a silicon layer 81 is deposited over monocrystalline oxide layer 74 via MBE, CVD, MOCVD, MEE, ALE, PVD, CSD, PLD, and the like as illustrated in FIG. 12 with a thickness of a few hundred Angstroms but preferably with a thickness of about 50 Angstroms.
  • Monocrystalline oxide layer 74 preferably has a thickness of about 20 to 100 Angstroms.
  • Rapid thermal annealing is then conducted in the presence of a carbon source such as acetylene or methane, for example at a temperature within a range of about 800°C to 1000°C to form capping layer 82 and silicate amorphous layer 86.
  • a carbon source such as acetylene or methane
  • other suitable carbon sources may be used as long as the rapid thermal annealing step functions to amorphize the monocrystalline oxide layer 74 into a silicate amorphous layer 86 and carbonize the top silicon layer 81 to form capping layer 82 which in this example would be a siUcon carbide (SiC) layer as illustrated in FIG. 13.
  • SiC siUcon carbide
  • the formation of amorphous layer 86 is similar to the formation of layer 36 illustrated in FIG. 3 and may comprise any of those materials described with reference to layer 36 in FIG.
  • a compound semiconductor layer 96 such as gallium nitride (GaN) is grown over the SiC surface by way of MBE, CVD, MOCVD, MEE, ALE, PVD, CSD, PLD, or the like to form a high quality compound semiconductor material for device formation. More specifically, the deposition of GaN and GaN based systems such as GalnN and AlGaN will result in the formation of dislocation nets confined at the silicon/amorphous region.
  • the resulting nitride containing compound semiconductor material may comprise elements from groups in, IV and V of the periodic table and is defect free.
  • this embodiment of the invention possesses a one step formation of the compliant substrate containing a SiC top surface and an amorphous layer on a Si surface. More specifically, this embodiment of the invention uses an intermediate single crystal oxide layer that is amorphosized to form a silicate layer which adsorbs the strain between the layers. Moreover, unlike past use of a SiC substrate, this embodiment of the invention is not limited by wafer size which is usually less than 2 inches in diameter for SiC substrates.
  • nitride containing semiconductor compounds containing group IH-V nitrides and silicon devices can be used for high temperature RF applications and optoelectronics.
  • GaN systems have particular use in the photonic industry for the blue/green and UN light sources and detection. High brightness light emitting diodes
  • LEDs and lasers may also be formed within the Ga ⁇ system.
  • FIGS. 15-17 schematically illustrate, in cross-section, the formation of another embodiment of a device structure in accordance with the invention.
  • This embodiment includes a compliant layer that functions as a transition layer that uses clathrate or Zintl type bonding. More specifically, this embodiment utilizes an intermetallic template layer to reduce the surface energy of the interface between material layers thereby allowing for two dimensional layer by layer growth.
  • the structure illustrated in FIG. 15 includes a monocrystalline substrate 102, an amorphous interface layer 108 and an accommodating buffer layer 104. Amorphous intermediate layer 108 is grown on substrate 102 at the interface between substrate 102 and accommodating buffer layer 104 as previously described with reference to FIGS. 1 and 2.
  • Amo hous interface layer 108 may comprise any of those materials previously described with reference to amorphous interface layer 28 in FIGS. 1 and 2 but preferably comprises a monocrystalline oxide material such as a monocrystalline layer of Sr z Ba ⁇ - z TiOs where z ranges from 0 to 1.
  • Substrate 102 is preferably silicon but may also comprise any of those materials previously described with reference to substrate 22 in FIGS. 1-3.
  • a template layer 130 is deposited over accommodating buffer layer 104 as illustrated in FIG. 16 and preferably comprises a thin layer of Zintl type phase material composed of metals and metalloids having a great deal of ionic character.
  • template layer 130 is deposited by way of MBE, CND, MOCVD, MEE, ALE, PVD, CSD, PLD, or the like to achieve a thickness of one monolayer.
  • Template layer 130 functions as a "soft" layer with non-directional bonding but high crystallinity which absorbs stress build up between layers having lattice mismatch.
  • Materials for template 130 may include, but are not limited to, materials containing Si, Ga, In, and Sb such as, for example, SrAl 2 , SrAl 4 , (MgCaYb)Ga 2 , (Ca,Sr,Eu,Yb)In 2 , BaGe 2 As, and SrSn 2 As 2 .
  • a monocrystalline material layer 126 is epitaxially grown over template layer 130 to achieve the final structure illustrated in FIG. 17.
  • an SrAl 2 layer may be used as template layer 130 and an appropriate monocrystalline material layer 126 such as a compound semiconductor material GaAs is grown over the SrAl 2 .
  • the Al-Ti (from the accommodating buffer layer of layer of Sr z Bai- z TiOs where z ranges from 0 to 1) bond is mostly metallic while the Al-As (from the GaAs layer) bond is weakly covalent.
  • the Sr participates in two distinct types of bonding with part of its electric charge going to the oxygen atoms in the lower accommodating buffer layer 104 comprising Sr z Ba!- z TiO 3 to participate in ionic bonding and the other part of its valence charge being donated to Al in a way that is typically carried out with Zintl phase materials.
  • the amount of the charge transfer depends on the relative electronegativity of elements comprising the template layer 130 as well as on the interatomic distance.
  • Al assumes an sp 3 hybridization and can readily form bonds with monocrystalline material layer 126, which in this example, comprises compound semiconductor material GaAs.
  • the compliant substrate produced by use of the Zintl type template layer used in this embodiment can absorb a large strain without a significant energy cost.
  • the bond strength of the Al is adjusted by changing the volume of the SrAl 2 layer thereby making the device tunable for specific applications which include the monolithic integration of DI-N and Si devices and the monolithic integration of high-k dielectric materials for CMOS technology.
  • the present invention includes structures and methods for fabricating material layers which form semiconductor structures, devices and integrated circuits including other layers such as metal and non-metal layers. More specifically, the invention includes structures and methods for forming a compliant substrate which is used in the fabrication of semiconductor structures, devices and integrated circuits and the material layers suitable for fabricating those structures, devices, and integrated circuits.
  • a monocrystalline semiconductor or compound semiconductor wafer can be used in forming monocrystalline material layers over the wafer.
  • the wafer is essentially a "handle" wafer used during the fabrication of semiconductor electrical components within a monocrystalline layer overlying the wafer. Therefore, electrical components can be formed within semiconductor materials over a wafer of at least approximately 200 millimeters in diameter and possibly at least approximately 300 millimeters.
  • a relatively inexpensive "handle" wafer overcomes the fragile nature of compound semiconductor or other monocrystalline material wafers by placing them over a relatively more durable and easy to fabricate base material. Therefore, an integrated circuit can be formed such that all electrical components, and particularly all active electronic devices, can be formed within or using the monocrystalline material layer even though the substrate itself may include a monocrystalline semiconductor material. Fabrication costs for compound semiconductor devices and other devices employing non-silicon monocrystalline materials should decrease because larger substrates can be processed more economically and more readily compared to the relatively smaller and more fragile substrates (e.g. conventional compound semiconductor wafers).
  • a device structure formed of GaN film in accordance with another embodiment of the invention is illustrated schematically in cross-section in Figs. 18-20. Like the previously described embodiments referred to in Figs. 1-3, this embodiment of the invention involves the process of forming a compliant substrate utilizing the epitaxial growth of single crystal oxides.
  • a monocrystalUne substrate 200 functions as the starting material.
  • Substrate may include a monocrystalline material such as that comprising layer 22 with reference to Figs. 1-3, but is preferably Si and is more preferably Si (100).
  • An accommodating buffer layer 202 is then grown epitaxially over substrate 200 and an amorphous intermediate layer 204 may be formed between substrate 200 and buffer layer 202 by the oxidation of substrate 200 during the growth of buffer layer 202.
  • Buffer layer 202 may be formed of a monocrystalline oxide or nitride material such as that comprising layers 24, 54, 74 and 104 with reference to Figs. 1, 9 A, 11 and 15, respectively.
  • buffer layer 202 is comprised of Sr z Ba ⁇ - z TiO 3; Sr z Ba ⁇ - z ZrO 3> Sr z Ba ! - z HfO 3 , SrzBai-zSnOs or CaTiO 3 epitaxially grown on substrate 200.
  • a monocrystalline material layer 206 is then epitaxially deposited over buffer layer 202.
  • Monocrystalline material layer 206 may be comprised of a monocrystalline material such as that comprising layer 26 with reference to Fig. 1, layer 66 with reference to Fig. 9D, layer 96 with reference to Fig. 14 and layer 126 with reference to Fig.
  • Monocrystalline material layer 206 may have a thickness in the range of from about 10 angstroms to about 200 angstroms, but has a thickness preferably in the range of from about 20 angstroms to about 50 angstroms. It will be appreciated that, while not shown, the structure in Fig. 18 may include a template layer, formed of material such as that comprising layers 30, 60, 81 and 130, between any adjacent monocrystalline layers as described herein. Further, while not shown, it will be appreciated that an additional monocrystalline material layer, similar to layer 38 with reference to Fig. 3, may be formed overlying buffer layer 202 and underlying monocrystalline material layer 206.
  • nitridation may occur using RF plasma, ECR plasma or Eximer laser with N 2 or NH 3 as the nitrogen source at a temperature of from about room temperature to about 700 degrees Celsius.
  • nitride layer 208 comprises partially or totally GaN; when monocrystalline material layer 206 is GaAlAs, nitride layer 208 comprises partially or totally GaAIN; when monocrystalline material layer 206 comprises AlAs, nitride layer 208 comprises partially or totally A1N; and when monocrystalline material layer 206 comprises Si, nitride layer 208 comprises partially or totally SiN.
  • the structure is then annealed at a temperature of about 700 degrees Celsius to about 900 degrees Celsius to form an amorphous layer 210, as illustrated in Fig. 20, similar to layer 36 described with reference to Fig. 3.
  • nitride material such as GaN, GalnN or AlGaN
  • devices such as light emitting devices, high temperature devices and other devices that may take advantage of the high quality crystalline nature of nitride layer 208.
  • GaN including A1N, GalnN, SiN, and AlGaN
  • electrical and optical devices may be achieved which realize a number of advantages.
  • Use of a compliant substrate in the devices reduce stress due to lattice mismatch between the substrate and the GaN film.
  • Dislocation density in the GaN films is also improved.

Abstract

High quality epitaxial layers of GaN can be grown overlying large silicon wafers (200) by forming an amorphous layer (210) on the substrate. The amorphous layer dissipates strain and permits the growth of a high quality GaN layer (208). Any lattice mismatch between the GaN layer and the underlying substrate is taken care of by the amorphous layer.

Description

GaN DEVICES HAVING A COMPLIANT SUBSTRATE
Field of the Invention This invention relates generally to semiconductor structures and devices and to a method for their fabrication, and more specifically to fabrication of semiconductor structures formed of GaN films on compliant substrates.
Background of the Invention Semiconductor devices typically include multiple layers of conductive, insulating, and semiconductive layers. Often, the desirable properties of such layers improve with the crystallinity of the layer. For example, the electron mobility and optical properties of semiconductive layers improves as the crystallinity of the layer increases. Similarly, the free electron concentration of conductive layers and the electron charge displacement and electron energy recoverability of insulative or dielectric films improves as the crystallinity of these layers increases. For many years, attempts have been made to grow various monolithic thin films on a foreign substrate, such as silicon (Si). To achieve optimal characteristics of the various monolithic layers, however, a monocrystalline film of high crystalline quality is desired. Attempts have been made, for example, to grow various monocrystalline layers on a substrate such as germanium, silicon, and various insulators. These attempts have generally been unsuccessful because lattice mismatches between the host crystal and the grown crystal have caused the resulting layer of monocrystalline material to be of low crystalline quality.
If a large area thin film of high quality monocrystalline material was available at low cost, a variety of semiconductor devices could advantageously be fabricated in that film at a low cost compared to the cost of fabricating such devices beginning with a bulk wafer of semiconductor material or in an epitaxial film of such material on a bulk wafer of semiconductor material. In addition, if a thin film of high quality monocrystalline material could be realized beginning with a bulk wafer such as a silicon wafer, an integrated device structure could be achieved that took advantage of the best properties of both the silicon and the high quality monocrystalline material. Accordingly, a need exists for a semiconductor structure that provides a high quality monocrystalline film or layer over another monocrystalline material and for a process for making such a structure. This structure and process could have extensive applications. One such application of this structure and process involves the fabrication of electrical and optical devices from cubic GaN films. To simplify the following discussion, a reference to GaN is to be understood as including GaN, GalnN, AlGaN, SiN and A1N, unless the context makes it clear that only GaN is intended. GaN has a large, direct bandgap, structural stability and high thermal stability which makes it suitable for a wide range of electrical and optical device applications such as lasers, light emitting devices in the blue and green wavelengths, high temperature devices and solar blind detectors.
One significant challenge to large scale production of cubic GaN devices is the lack of bulk substrates formed of suitable lattice-matched material for subsequent high quality epitaxial GaN growth. Currently, GaN film growth is carried out on sapphire substrates or SiC substrates, both substrates of which present disadvantages. SiC substrates are of small size and are expensive. Further, GaN on sapphire is hexagonal and exhibits lower mobility than cubic GaN. In addition, sapphire has a lattice constant and thermal conductivity significantly different from HI-N nitrides such as GaΝ and is electrically insulating. For example, the lattice constant for GaΝ differs by approximately 13-16% from that of sapphire. These significant differences lead to mechanical stresses in the subsequent film growth above the critical thickness, which results in fracturing and voids in the GaΝ layer. Another disadvantage of typical GaΝ films grown on sapphire is the high number of defect dislocations in the GaΝ layers. These defects impact the electrical and optical performance of the GaΝ devices. For example, in optical devices, the defects act as scattering centers requiring a higher laser threshold current density. In electrical devices, dislocations can create deep defect energy levels that increase the leakage current.
Accordingly, a need exists for a semiconductor structure that provides high quality electrical and optical devices formed of GaΝ films and for a process for making such a structure.
Brief Description of the Drawings The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which:
FIGS. 1, 2, and 3 illustrate schematically, in cross section, device structures in accordance with various embodiments of the invention; FLG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer;
FIG. 5 illustrates a high resolution Transmission Electron Micrograph of a structure including a monocrystalline accommodating buffer layer; FIG. 6 illustrates an x-ray diffraction spectrum of a structure including a monocrystalline accommodating buffer layer;
FIG. 7 illustrates a high resolution Transmission Electron Micrograph of a structure including an amorphous oxide layer;
FIG. 8 illustrates an x-ray diffraction spectrum of a structure including an amorphous oxide layer;
FIGS. 9A-9D illustrate schematically, in cross-section, the formation of a device structure in accordance with another embodiment of the invention;
FIGS. 10A-10D illustrate a probable molecular bonding structure of the device structures illustrated in FIGS. 9A-9D; FIGS. 11-14 illustrate schematically, in cross-section, the formation of a device structure in accordance with still another embodiment of the invention;
FIGS. 15-17 illustrate schematically, in cross-section, the formation of yet another embodiment of a device structure in accordance with the invention; and
FIGS. 18-20 illustrate schematically, in cross-section, the formation of another exemplary embodiment of a semiconductor structure fabricated on a semiconductor substrate according to the present invention.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.
Detailed Description of the Drawings FIG. 1 illustrates schematically, in cross section, a portion of a semiconductor structure 20 in accordance with an embodiment of the invention. Semiconductor structure 20 includes a monocrystalline substrate 22, accommodating buffer layer 24 comprising a monocrystalline material, and a monocrystalline material layer 26. In this context, the term "monocrystalline" shall have the meaning commonly used within the semiconductor industry. The term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry. In accordance with one embodiment of the invention, structure 20 also includes an amorphous intermediate layer 28 positioned between substrate 22 and accommodating buffer layer 24. Structure 20 may also include a template layer 30 between the accommodating buffer layer and monocrystalline material layer 26. As will be explained more fully below, the template layer helps to initiate the growth of the monocrystalline material layer on the accommodating buffer layer. The amorphous intermediate layer helps to relieve the strain in the accommodating buffer layer and by doing so, aids in the growth of a high crystalline quality accommodating buffer layer.
Substrate 22, in accordance with an embodiment of the invention, is a monocrystalline semiconductor or compound semiconductor wafer, preferably of large diameter. The wafer can be of, for example, a material from Group IN of the periodic table, and preferably a material from Group IVB. Examples of Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like. Preferably substrate 22 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry. Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate. In accordance with one embodiment of the invention, amorphous intermediate layer 28 is grown on substrate 22 at the interface between substrate 22 and the growing accommodating buffer layer by the oxidation of substrate 22 during the growth of layer 24. The amorphous intermediate layer serves to relieve strain that might otherwise occur in the monocrystalline accommodating buffer layer as a result of differences in the lattice constants of the substrate and the buffer layer. As used herein, lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by the amorphous intermediate layer, the strain may cause defects in the crystalline structure of the accommodating buffer layer. Defects in the crystalline structure of the accommodating buffer layer, in turn, would make it difficult to achieve a high quality crystalline structure in monocrystalline material layer 26 which may comprise a semiconductor material, a compound semiconductor material, or another type of material such as a metal or a non- metal.
Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying substrate and with the overlying material layer. For example, the material could be an oxide or nitride having a lattice structure closely matched to the substrate and to the subsequently applied monocrystalline material layer. Materials that are suitable for the accommodating buffer layer include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for the accommodating buffer layer. Most of these materials are insulators, although strontium ruthenate, for example, is a conductor. Generally, these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitrides may include three or more different metallic elements.
Amorphous interface layer 28 is preferably an oxide formed by the oxidation of the surface of substrate 22, and more preferably is composed of a silicon oxide. The thickness of layer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate 22 and accommodating buffer layer 24. Typically, layer 28 has a thickness in the range of approximately 0.5-5 nm.
The material for monocrystalline material layer 26 can be selected, as desired, for a particular structure or application. For example, the monocrystalline material of layer 26 may comprise a compound semiconductor which can be selected, as needed for a particular semiconductor structure, from any of the Group I-QA and VA elements (TTT-V semiconductor compounds), mixed TE-V compounds, Group H(A or B) and VIA elements (UNI semiconductor compounds), and mixed II-NI compounds. Examples include gallium arsenide (GaAs), gallium indium arsenide (GalnAs), gallium aluminum arsenide (GaAlAs), indium phosphide (InP), cadmium sulfide (CdS), cadmium mercury telluride (CdHgTe), zinc selenide (ZnSe), zinc sulfur selenide (ZnSSe), and the like. However, monocrystalline material layer 26 may also comprise other semiconductor materials, metals, or non-metal materials which are used in the formation of semiconductor structures, devices and/or integrated circuits.
Appropriate materials for template 30 are discussed below. Suitable template materials chemically bond to the surface of the accommodating buffer layer 24 at selected sites and provide sites for the nucleation of the epitaxial growth of monocrystalline material layer 26. When used, template layer 30 has a thickness ranging from about 1 to about 10 monolayers.
FIG. 2 illustrates, in cross section, a portion of a semiconductor structure 40 in accordance with a further embodiment of the invention. Structure 40 is similar to the previously described semiconductor structure 20, except that an additional buffer layer 32 is positioned between accommodating buffer layer 24 and monocrystalline material layer 26. Specifically, the additional buffer layer is positioned between template layer 30 and the overlying layer of monocrystalline material. The additional buffer layer, formed of a semiconductor or compound semiconductor material when the monocrystalline material layer 26 comprises a semiconductor or compound semiconductor material, serves to provide a lattice compensation when the lattice constant of the accommodating buffer layer cannot be adequately matched to the overlying monocrystalline semiconductor or compound semiconductor material layer.
FIG. 3 schematically illustrates, in cross section, a portion of a semiconductor structure 34 in accordance with another exemplary embodiment of the invention. Structure
34 is similar to structure 20, except that structure 34 includes an amorphous layer 36, rather than accommodating buffer layer 24 and amorphous interface layer 28, and an additional monocrystalline layer 38.
As explained in greater detail below, amorphous layer 36 may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above. Monocrystalline layer 38 is then formed (by epitaxial growth) overlying the monocrystalline accommodating buffer layer. The accommodating buffer layer is then exposed to an anneal process to convert the monocrystalline accommodating buffer layer to an amorphous layer. Amorphous layer 36 formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate. Thus, layer 36 may comprise one or two amorphous layers. Formation of amorphous layer 36 between substrate 22 and additional monocrystalline layer 26 (subsequent to layer 38 formation) relieves stresses between layers 22 and 38 and provides a true compliant substrate for subsequent processing-e.g., monocrystalline material layer 26 formation.
The processes previously described above in connection with FIGS. 1 and 2 are adequate for growing monocrystalline material layers over a monocrystalline substrate. However, the process described in connection with FIG. 3, which includes transforming a monocrystalline accommodating buffer layer to an amorphous oxide layer, may be better for growing monocrystalline material layers because it allows any strain in layer 26 to relax.
Additional monocrystalline layer 38 may include any of the materials described throughout this application in connection with either of monocrystalline material layer 26 or additional buffer layer 32. For example, when monocrystalline material layer 26 comprises a semiconductor or compound semiconductor material, layer 38 may include monocrystalline
Group IN or monocrystalline compound semiconductor materials.
In accordance with one embodiment of the present invention, additional monocrystalline layer 38 serves as an anneal cap during layer 36 formation and as a template for subsequent monocrystalline layer 26 formation. Accordingly, layer 38 is preferably thick enough to provide a suitable template for layer 26 growth (at least one monolayer) and thin enough to allow layer 38 to form as a substantially defect free monocrystalline material.
In accordance with another embodiment of the invention, additional monocrystalline layer 38 comprises monocrystalline material (e.g., a material discussed above in connection with monocrystalline layer 26) that is thick enough to form devices within layer 38. In this case, a semiconductor structure in accordance with the present invention does not include monocrystalline material layer 26. In other words, the semiconductor structure in accordance with this embodiment only includes one monocrystalline layer disposed above amorphous oxide layer 36. The following non-limiting, illustrative examples illustrate various combinations of materials useful in structures 20, 40, and 34 in accordance with various alternative embodiments of the invention. These examples are merely illustrative, and it is not intended that the invention be limited to these illustrative examples. Example 1
In accordance with one embodiment of the invention, monocrystalline substrate 22 is a silicon substrate oriented in the (100) direction. The silicon substrate can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200-300 mm. In accordance with this embodiment of the invention, accommodating buffer layer 24 is a monocrystalline layer of SτzB ι.JTi 3 where z ranges from 0 to 1 and the amorphous intermediate layer is a layer of silicon oxide (SiOx) formed at the interface between the silicon substrate and the accommodating buffer layer. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formed layer 26. The accommodating buffer layer can have a thickness of about 2 to about 100 nanometers (nm) and preferably has a thickness of about 5 nm. In general, it is desired to have an accommodating buffer layer thick enough to isolate the compound semiconductor layer from the substrate to obtain the desired electrical and optical properties. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed. The amorphous intermediate layer of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1 to 2 nm.
In accordance with this embodiment of the invention, monocrystalline material layer 26 is a compound semiconductor layer of gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs) having a thickness of about 1 nm to about 100 micrometers (μm) and preferably a thickness of about 0.5 μ to 10 μm. The thickness generally depends on the application for which the layer is being prepared. To facilitate the epitaxial growth of the gallium arsenide or aluminum gallium arsenide on the monocrystalline oxide, a template layer is formed by capping the oxide layer. The template layer is preferably 1-10 monolayers of Ti-As, Sr-O-As, Sr-Ga-O, or Sr-Al-O. By way of a preferred example, 1-2 monolayers of Ti-As or Sr-Ga-O have been illustrated to successfully grow GaAs layers.
Example 2 This embodiment of the invention is an example of structure 40 illustrated in FIG. 2.
Substrate 22, accommodating buffer layer 24, and monocrystalline material layer 26 can be similar to those described in example 1. In addition, an additional buffer layer 32 serves to alleviate any strains that might result from a mismatch of the crystal lattice of the accommodating buffer layer and the lattice of the monocrystalline material. Buffer layer 32 can be a layer of germanium or a GaAs, an aluminum gallium arsenide (AlGaAs), an indium gallium phosphide (InGaP), an aluminum gallium phosphide (AlGaP), an indium gallium arsenide (InGaAs), an aluminum indium phosphide (AllnP), a gallium arsenide phosphide (GaAsP), or an indium gallium phosphide (InGaP) strain compensated superlattice. In accordance with one aspect of this embodiment, buffer layer 32 includes a GaAsχP!-x superlattice, wherein the value of x ranges from 0 to 1. In accordance with another aspect, buffer layer 32 includes an InyGa^yP superlattice, wherein the value of y ranges from 0 to 1. By varying the value of x or y, as the case may be, the lattice constant is varied from bottom to top across the superlattice to create a match between lattice constants of the underlying oxide and the overlying monocrystalline material which in this example is a compound semiconductor material. The compositions of other compound semiconductor materials, such as those listed above, may also be similarly varied to manipulate the lattice constant of layer 32 in a like manner. The superlattice can have a thickness of about 50-500 nm and preferably has a thickness of about 100-200 nm. The template for this structure can be the same of that described in example 1. Alternatively, buffer layer 32 can be a layer of monocrystalline germanium having a thickness of 1-50 nm and preferably having a thickness of about 2-20 nm. In using a germanium buffer layer, a template layer of either germanium- strontium (Ge-Sr) or germanium-titanium (Ge-Ti) having a thickness of about one monolayer can be used as a nucleating site for the subsequent growth of the monocrystalline material layer which in this example is a compound semiconductor material. The formation of the oxide layer is capped with either a monolayer of strontium or a monolayer of titanium to act as a nucleating site for the subsequent deposition of the monocrystalline germanium. The monolayer of strontium or titanium provides a nucleating site to which the first monolayer of germanium can bond.
Example 3 This example provides exemplary materials useful in structure 34, as illustrated in FIG. 3. Substrate material 22, template layer 30, and monocrystalline material layer 26 may be the same as those described above in connection with example 1.
Amorphous layer 36 is an amorphous oxide layer which is suitably formed of a combination of amorphous intermediate layer materials (e.g., layer 28 materials as described above) and accommodating buffer layer materials (e.g., layer 24 materials as described above). For example, amorphous layer 36 may include a combination of SiOx and SrzBai-z TiO3 (where z ranges from 0 to l),which combine or mix, at least partially, during an anneal process to form amorphous oxide layer 36.
The thickness of amorphous layer 36 may vary from application to application and may depend on such factors as desired insulating properties of layer 36, type of monocrystalline material comprising layer 26, and the like. In accordance with one exemplary aspect of the present embodiment, layer 36 thickness is about 2 nm to about 100 nm, preferably about 2-10 nm, and more preferably about 5-6 nm.
Layer 38 comprises a monocrystalline material that can be grown epitaxially over a monocrystalline oxide material such as material used to form accommodating buffer layer 24. In accordance with one embodiment of the invention, layer 38 includes the same materials as those comprising layer 26. For example, if layer 26 includes GaAs, layer 38 also includes GaAs. However, in accordance with other embodiments of the present invention, layer 38 may include materials different from those used to form layer 26. In accordance with one exemplary embodiment of the invention, layer 38 is about 1 monolayer to about 100 nm thick.
Referring again to FIGS. 1 - 3, substrate 22 is a monocrystalline substrate such as a monocrystalline silicon or gallium arsenide substrate. The crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation. In similar manner, accommodating buffer layer 24 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation. The lattice constants of the accommodating buffer layer and the monocrystalline substrate must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved. In this context the terms "substantially equal" and "substantially matched" mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer.
HG. 4 illustrates graphically the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal. Curve 42 illustrates the boundary of high crystalline quality material. The area to the right of curve 42 represents layers that have a large number of defects. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved.
In accordance with one embodiment of the invention, substrate 22 is a (100) or (111) oriented monocrystalline silicon wafer and accommodating buffer layer 24 is a layer of strontium barium titanate. Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material by 45° with respect to the crystal orientation of the silicon substrate wafer. The inclusion in the structure of amorphous interface layer 28, a silicon oxide layer in this example, if it is of sufficient thickness, serves to reduce strain in the titanate monocrystalline layer that might result from any mismatch in the lattice constants of the host silicon wafer and the grown titanate layer. As a result, in accordance with an embodiment of the invention, a high quality, thick, monocrystalline titanate layer is achievable.
Still referring to FIGS. 1 - 3, layer 26 is a layer of epitaxially grown monocrystalline material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation. In accordance with one embodiment of the invention, the lattice constant of layer 26 differs from the lattice constant of substrate 22. To achieve high crystalline quality in this epitaxially grown monocrystalUne layer, the accommodating buffer layer must be of high crystalline quality. In addition, in order to achieve high crystalline quality in layer
26, substantial matching between the crystal lattice constant of the host crystal, in this case, the monocrystalline accommodating buffer layer, and the grown crystal is desired. With properly selected materials this substantial matching of lattice constants is achieved as a result of rotation of the crystal orientation of the grown crystal with respect to the orientation of the host crystal. For example, if the grown crystal is gallium arsenide, or aluminum gallium arsenide, and the accommodating buffer layer is monocrystalline SrxBai-xTiO3, substantial matching of crystal lattice constants of the two materials is achieved, wherein the crystal orientation of the grown layer is rotated by 45° with respect to the orientation of the host monocrystalline oxide. Similarly, if the host material is a strontium or barium zirconate or a strontium or barium hafnate or barium tin oxide and the compound semiconductor layer is indium phosphide or gallium indium arsenide or aluminum indium arsenide, substantial matching of crystal lattice constants can be achieved by rotating the orientation of the grown crystal layer by 45° with respect to the host oxide crystal. In some instances, a crystalline semiconductor buffer layer between the host oxide and the grown monocrystalline material layer can be used to reduce strain in the grown monocrystalline material layer that might result from small differences in lattice constants. Better crystalline quality in the grown monocrystalline material layer can thereby be achieved.
The following example illustrates a process, in accordance with one embodiment of the invention, for fabricating a semiconductor structure such as the structures depicted in HGS. 1 - 3. The process starts by providing a monocrystalline semiconductor substrate comprising silicon or germanium. In accordance with a preferred embodiment of the invention, the semiconductor substrate is a silicon wafer having a (100) orientation. The substrate is preferably oriented on axis or, at most, about 4° off axis. At least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures. The term "bare" in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material. As is well known, bare silicon is highly reactive and readily forms a native oxide. The term "bare" is intended to encompass such a native oxide. A thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process in accordance with the invention. In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline substrate, the native oxide layer must first be removed to expose the crystalline structure of the underlying substrate. The following process is preferably carried out by molecular beam epitaxy (MBE), although other epitaxial processes may also be used in accordance with the present invention. The native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus. In the case where strontium is used, the substrate is then heated to a temperature of about 850° C to cause the strontium to react with the native silicon oxide layer. The strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface. The resultant surface, which exhibits an ordered 2x1 structure, includes strontium, oxygen, and silicon. The ordered 2x1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide. The template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer. In accordance with an alternate embodiment of the invention, the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkali earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 850°C. At this temperature a solid state reaction takes place between the strontium oxide and the native silicon oxide causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer. Following the removal of the silicon oxide from the surface of the substrate, in accordance with one embodiment of the invention, the substrate is cooled to a temperature in the range of about 200-800°C and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy. The MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources. The ratio of strontium and titanium is approximately 1:1. The partial pressure of oxygen is initially set at a minimum value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value. The overpressure of oxygen causes the growth of an amorphous silicon oxide layer at the interface between the underlying substrate and the growing strontium titanate layer. The growth of the silicon oxide layer results from the diffusion of oxygen through the growing strontium titanate layer to the interface where the oxygen reacts with silicon at the surface of the underlying substrate. The strontium titanate grows as an ordered monocrystal with the crystalline orientation rotated by 45° with respect to the ordered 2x1 crystalline structure of the underlying substrate. Strain that otherwise might exist in the strontium titanate layer because of the small mismatch in lattice constant between the silicon substrate and the growing crystal is relieved in the amorphous silicon oxide intermediate layer.
After the strontium titanate layer has been grown to the desired thickness, the monocrystalline strontium titanate is capped by a template layer that is conducive to the subsequent growth of an epitaxial layer of a desired monocrystalline material. For example, for the subsequent growth of a monocrystalline compound semiconductor material layer of gallium arsenide, the MBE growth of the strontium titanate monocrystalline layer can be capped by terminating the growth with 1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen, 1-2 monolayers of strontium, or with 1-2 monolayers of strontium-oxygen. Following the formation of this capping layer, arsenic is deposited to form a Ti-As bond, a Ti-O-As bond or a Sr-O-As. Any of these form an appropriate template for deposition and formation of a gallium arsenide monocrystalline layer. Following the formation of the template, gallium is subsequently introduced to the reaction with the arsenic and gallium arsenide forms. Alternatively, gallium can be deposited on the capping layer to form a Sr-O- Ga bond, and arsenic is subsequently introduced with the gallium to form the GaAs.
FIG. 5 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with one embodiment of the present invention. Single crystal SrTiO3 accommodating buffer layer 24 was grown epitaxially on silicon substrate 22. During this growth process, amorphous interfacial layer 28 is formed which relieves strain due to lattice mismatch. GaAs compound semiconductor layer 26 was then grown epitaxially using template layer 30.
FIG. 6 illustrates an x-ray diffraction spectrum taken on a structure including GaAs monocrystalline layer 26 comprising GaAs grown on silicon substrate 22 using accommodating buffer layer 24. The peaks in the spectrum indicate that both the accommodating buffer layer 24 and GaAs compound semiconductor layer 26 are single crystal and (100) orientated.
The structure illustrated in FIG. 2 can be formed by the process discussed above with the addition of an additional buffer layer deposition step. The buffer layer is formed overlying the template layer before the deposition of the monocrystalline material layer. If the buffer layer is a monocrystalUne material comprising a compound semiconductor superlattice, such a superlattice can be deposited, by MBE for example, on the template described above. If instead the buffer layer is a monocrystalline material layer comprising a layer of germanium, the process above is modified to cap the strontium titanate monocrystalUne layer with a final layer of either strontium or titanium and then by depositing germanium to react with the strontium or titanium. The germanium buffer layer can then be deposited directly on this template.
Structure 34, illustrated in FIG. 3, may be formed by growing an accommodating buffer layer, forming an amorphous oxide layer over substrate 22, and growing semiconductor layer 38 over the accommodating buffer layer, as described above. The accommodating buffer layer and the amorphous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amorphous, thereby forming an amorphous layer such that the combination of the amorphous oxide layer and the now amorphous accommodating buffer layer form a single amorphous oxide layer 36. Layer 26 is then subsequently grown over layer 38. Alternatively, the anneal process may be carried out subsequent to growth of layer 26.
In accordance with one aspect of this embodiment, layer 36 is formed by exposing substrate 22, the accommodating buffer layer, the amorphous oxide layer, and monocrystalline layer 38 to a rapid thermal anneal process with a peak temperature of about 700°C to about 1000°C and a process time of about 5 seconds to about 10 minutes. However, other suitable anneal processes may be employed to convert the accommodating buffer layer to an amorphous layer in accordance with the present invention. For example, laser annealing, electron beam annealing, or "conventional" thermal annealing processes (in the proper environment) may be used to form layer 36. When conventional thermal annealing is employed to form layer 36, an overpressure of one or more constituents of layer 30 may be required to prevent degradation of layer 38 during the anneal process. For example, when layer 38 includes GaAs, the anneal environment preferably includes an overpressure of arsenic to mitigate degradation of layer 38.
As noted above, layer 38 of structure 34 may include any materials suitable for either of layers 32 or 26. Accordingly, any deposition or growth methods described in connection with either layer 32 or 26, may be employed to deposit layer 38.
FIG. 7 is a high resolution TEM of semiconductor material manufactured in accordance with the embodiment of the invention illustrated in FIG. 3. In accordance with this embodiment, a single crystal SrTiO3 accommodating buffer layer was grown epitaxially on silicon substrate 22. During this growth process, an amorphous interfacial layer forms as described above. Next, additional monocrystalline layer 38 comprising a compound semiconductor layer of GaAs is formed above the accommodating buffer layer and the accommodating buffer layer is exposed to an anneal process to form amorphous oxide layer 36.
FIG. 8 illustrates an x-ray diffraction spectrum taken on a structure including additional monocrystalline layer 38 comprising a GaAs compound semiconductor layer and amorphous oxide layer 36 formed on silicon substrate 22. The peaks in the spectrum indicate that GaAs compound semiconductor layer 38 is single crystal and (100) orientated and the lack of peaks around 40 to 50 degrees indicates that layer 36 is amorphous. The process described above illustrates a process for forming a semiconductor structure including a silicon substrate, an overlying oxide layer, and a monocrystalline material layer comprising a gallium arsenide compound semiconductor layer by the process of molecular beam epitaxy. The process can also be carried out by the process of chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), migration enhanced epitaxy (MEE), atomic layer epitaxy (ALE), physical vapor deposition (PVD), chemical solution deposition (CSD), pulsed laser deposition (PLD), or the like. Further, by a similar process, other monocrystalline accommodating buffer layers such as alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown. Further, by a similar process such as MBE, other monocrystalline material layers comprising other III-N and II-NI monocrystalline compound semiconductors, semiconductors, metals and non-metals can be deposited overlying the monocrystalline oxide accommodating buffer layer. Each of the variations of monocrystalline material layer and monocrystalline oxide accommodating buffer layer uses an appropriate template for initiating the growth of the monocrystalline material layer. For example, if the accommodating buffer layer is an alkaline earth metal zirconate, the oxide can be capped by a thin layer of zirconium. The deposition of zirconium can be followed by the deposition of arsenic or phosphorus to react with the zirconium as a precursor to depositing indium gallium arsenide, indium aluminum arsenide, or indium phosphide respectively. Similarly, if the monocrystalline oxide accommodating buffer layer is an alkaline earth metal hafnate, the oxide layer can be capped by a thin layer of hafnium. The deposition of hafnium is followed by the deposition of arsenic or phosphorous to react with the hafnium as a precursor to the growth of an indium gallium arsenide, indium aluminum arsenide, or indium phosphide layer, respectively. In a similar manner, strontium titanate can be capped with a layer of strontium or strontium and oxygen and barium titanate can be capped with a layer of barium or barium and oxygen. Each of these depositions can be followed by the deposition of arsenic or phosphorus to react with the capping material to form a template for the deposition of a monocrystalline material layer comprising compound semiconductors such as indium gallium arsenide, indium aluminum arsenide, or indium phosphide.
The formation of a device structure in accordance with another embodiment of the invention is illustrated schematically in cross-section in FIGS. 9A-9D. Like the previously described embodiments referred to in FIGS. 1-3, this embodiment of the invention involves the process of forming a compliant substrate utilizing the epitaxial growth of single crystal oxides, such as the formation of accommodating buffer layer 24 previously described with reference to FIGS. 1 and 2 and amorphous layer 36 previously described with reference to FIG. 3, and the formation of a template layer 30. However, the embodiment illustrated in FIGS. 9A-9D utilizes a template that includes a surfactant to facilitate layer-by-layer monocrystalline material growth.
Turning now to FIG. 9 A, an amorphous intermediate layer 58 is grown on substrate 52 at the interface between substrate 52 and a growing accommodating buffer layer 54, which is preferably a monocrystalline crystal oxide layer, by the oxidation of substrate 52 during the growth of layer 54. Layer 54 is preferably a monocrystalline oxide material such as a monocrystalline layer of SrJBa zTiOs where z ranges from 0 to 1. However, layer 54 may also comprise any of those compounds previously described with reference layer 24 in FIGS. 1-2 and any of those compounds previously described with reference to layer 36 in FIG. 3 which is formed from layers 24 and 28 referenced in FIGS. 1 and 2.
Layer 54 is grown with a strontium (Sr) terminated surface represented in FIG. 9A by hatched line 55 which is followed by the addition of a template layer 60 which includes a surfactant layer 61 and capping layer 63 as illustrated in FIGS. 9B and 9C. Surfactant layer 61 may comprise, but is not limited to, elements such as Al, In and Ga, but will be dependent upon the composition of layer 54 and the overlying layer of monocrystalline material for optimal results. In one exemplary embodiment, aluminum (Al) is used for surfactant layer 61 and functions to modify the surface and surface energy of layer 54. Preferably, surfactant layer 61 is epitaxially grown, to a thickness of one to two monolayers, over layer 24 as illustrated in FIG. 9B by way of molecular beam epitaxy (MBE), although other epitaxial processes may also be performed including chemical vapor deposition (CND), metal organic chemical vapor deposition (MOCVD), migration enhanced epitaxy (MEE), atomic layer epitaxy (ALE), physical vapor deposition (PVD), chemical solution deposition (CSD), pulsed laser deposition (PLD), or the like.
Surfactant layer 61 is then exposed to a halogen such as arsenic, for example, to form capping layer 63 as illustrated in FIG. 9C. Surfactant layer 61 may be exposed to a number of materials to create capping layer 63 such as elements which include, but are not limited to, As, P, Sb and Ν. Surfactant layer 61 and capping layer 63 combine to form template layer 60. Monocrystalline material layer 66, which in this example is a compound semiconductor such as GaAs, is then deposited via MBE, CND, MOCVD, MEE, ALE, PVD, CSD, PLD, and the like to form the final structure illustrated in FIG. 9D.
FIGS. 10A-10D illustrate possible molecular bond structures for a specific example of a compound semiconductor structure formed in accordance with the embodiment of the invention illustrated in FIGS. 9A-9D. More specifically, FIGS. 10A-10D illustrate the growth of GaAs (layer 66) on the strontium terminated surface of a strontium titanate monocrystalline oxide (layer 54) using a surfactant containing template (layer 60).
The growth of a monocrystalline material layer 66 such as GaAs on an accommodating buffer layer 54 such as a strontium titanium oxide over amorphous interface layer 58 and substrate layer 52, both of which may comprise materials previously described with reference to layers 28 and 22, respectively in FIGS. 1 and 2, illustrates a critical thickness of about 1000 angstroms where the two-dimensional (2D) and three-dimensional (3D) growth shifts because of the surface energies involved. In order to maintain a true layer by layer growth (Frank Van der Mere growth), the following relationship must be satisfied:
"STO ■> (OlNT "*" OGOAS ) where the surface energy of the monocrystalline oxide layer 54 must be greater than the surface energy of the amorphous interface layer 58 added to the surface energy of the GaAs layer 66. Since it is impracticable to satisfy this equation, a surfactant containing template was used, as described above with reference to FIGS. 9B-9D, to increase the surface energy of the monocrystalline oxide layer 54 and also to shift the crystalline structure of the template to a diamond-like structure that is in compliance with the original GaAs layer.
FIG. 10A illustrates the molecular bond structure of a strontium terminated surface of a strontium titanate monocrystalline oxide layer. An aluminum surfactant layer is deposited on top of the strontium terminated surface and bonds with that surface as illustrated in FIG. 10B, which reacts to form a capping layer comprising a monolayer of Al2Sr having the molecular bond structure illustrated in FIG. 10B which forms a diamond-like structure with an sp3 hybrid terminated surface that is compliant with compound semiconductors such as GaAs. The structure is then exposed to As to form a layer of AlAs as shown in FIG. IOC. GaAs is then deposited to complete the molecular bond structure illustrated in FIG. 10D which has been obtained by 2D growth. The GaAs can be grown to any thickness for forming other semiconductor structures, devices, or integrated circuits. Alkaline earth metals such as those in Group HA are those elements preferably used to form the capping surface of the monocrystalline oxide layer 24 because they are capable of forming a desired molecular structure with aluminum.
In this embodiment, a surfactant containing template layer aids in the formation of a compliant substrate for the monolithic integration of various material layers including those comprised of Group III-V compounds to form high quality semiconductor structures, devices and integrated circuits. For example, a surfactant containing template may be used for the monolithic integration of a monocrystalline material layer such as a layer comprising Germanium (Ge), for example, to form high efficiency photocells. Turning now to FIGS. 11-14, the formation of a device structure in accordance with still another embodiment of the invention is illustrated in cross-section. This embodiment utilizes the formation of a compliant substrate which relies on the epitaxial growth of single crystal oxides on silicon followed by the epitaxial growth of single crystal silicon onto the oxide. An accommodating buffer layer 74 such as a monocrystalline oxide layer is first grown on a substrate layer 72, such as silicon, with an amorphous interface layer 28 as illustrated in FIG. 11. Monocrystalline oxide layer 74 may be comprised of any of those materials previously discussed with reference to layer 24 in FIGS. 1 and 2, while amorphous interface layer 78 is preferably comprised, of any of those materials previously described with reference to the layer 28 illustrated in FIGS. 1 and 2. Substrate 72, although preferably silicon, may also comprise any of those materials previously described with reference to substrate 22 in FIGS. 1-3.
Next, a silicon layer 81 is deposited over monocrystalline oxide layer 74 via MBE, CVD, MOCVD, MEE, ALE, PVD, CSD, PLD, and the like as illustrated in FIG. 12 with a thickness of a few hundred Angstroms but preferably with a thickness of about 50 Angstroms. Monocrystalline oxide layer 74 preferably has a thickness of about 20 to 100 Angstroms.
Rapid thermal annealing is then conducted in the presence of a carbon source such as acetylene or methane, for example at a temperature within a range of about 800°C to 1000°C to form capping layer 82 and silicate amorphous layer 86. However, other suitable carbon sources may be used as long as the rapid thermal annealing step functions to amorphize the monocrystalline oxide layer 74 into a silicate amorphous layer 86 and carbonize the top silicon layer 81 to form capping layer 82 which in this example would be a siUcon carbide (SiC) layer as illustrated in FIG. 13. The formation of amorphous layer 86 is similar to the formation of layer 36 illustrated in FIG. 3 and may comprise any of those materials described with reference to layer 36 in FIG. 3 but the preferable material will be dependent upon the capping layer 82 used for silicon layer 81. Finally, a compound semiconductor layer 96, such as gallium nitride (GaN) is grown over the SiC surface by way of MBE, CVD, MOCVD, MEE, ALE, PVD, CSD, PLD, or the like to form a high quality compound semiconductor material for device formation. More specifically, the deposition of GaN and GaN based systems such as GalnN and AlGaN will result in the formation of dislocation nets confined at the silicon/amorphous region. The resulting nitride containing compound semiconductor material may comprise elements from groups in, IV and V of the periodic table and is defect free.
Although GaN has been grown on SiC substrate in the past, this embodiment of the invention possesses a one step formation of the compliant substrate containing a SiC top surface and an amorphous layer on a Si surface. More specifically, this embodiment of the invention uses an intermediate single crystal oxide layer that is amorphosized to form a silicate layer which adsorbs the strain between the layers. Moreover, unlike past use of a SiC substrate, this embodiment of the invention is not limited by wafer size which is usually less than 2 inches in diameter for SiC substrates.
The monolithic integration of nitride containing semiconductor compounds containing group IH-V nitrides and silicon devices can be used for high temperature RF applications and optoelectronics. GaN systems have particular use in the photonic industry for the blue/green and UN light sources and detection. High brightness light emitting diodes
(LEDs) and lasers may also be formed within the GaΝ system.
FIGS. 15-17 schematically illustrate, in cross-section, the formation of another embodiment of a device structure in accordance with the invention. This embodiment includes a compliant layer that functions as a transition layer that uses clathrate or Zintl type bonding. More specifically, this embodiment utilizes an intermetallic template layer to reduce the surface energy of the interface between material layers thereby allowing for two dimensional layer by layer growth. The structure illustrated in FIG. 15 includes a monocrystalline substrate 102, an amorphous interface layer 108 and an accommodating buffer layer 104. Amorphous intermediate layer 108 is grown on substrate 102 at the interface between substrate 102 and accommodating buffer layer 104 as previously described with reference to FIGS. 1 and 2. Amo hous interface layer 108 may comprise any of those materials previously described with reference to amorphous interface layer 28 in FIGS. 1 and 2 but preferably comprises a monocrystalline oxide material such as a monocrystalline layer of SrzBaϊ-zTiOs where z ranges from 0 to 1. Substrate 102 is preferably silicon but may also comprise any of those materials previously described with reference to substrate 22 in FIGS. 1-3.
A template layer 130 is deposited over accommodating buffer layer 104 as illustrated in FIG. 16 and preferably comprises a thin layer of Zintl type phase material composed of metals and metalloids having a great deal of ionic character. As in previously described embodiments, template layer 130 is deposited by way of MBE, CND, MOCVD, MEE, ALE, PVD, CSD, PLD, or the like to achieve a thickness of one monolayer. Template layer 130 functions as a "soft" layer with non-directional bonding but high crystallinity which absorbs stress build up between layers having lattice mismatch. Materials for template 130 may include, but are not limited to, materials containing Si, Ga, In, and Sb such as, for example, SrAl2, SrAl4, (MgCaYb)Ga2, (Ca,Sr,Eu,Yb)In2, BaGe2As, and SrSn2As2. A monocrystalline material layer 126 is epitaxially grown over template layer 130 to achieve the final structure illustrated in FIG. 17. As a specific example, an SrAl2 layer may be used as template layer 130 and an appropriate monocrystalline material layer 126 such as a compound semiconductor material GaAs is grown over the SrAl2. The Al-Ti (from the accommodating buffer layer of layer of SrzBai-zTiOs where z ranges from 0 to 1) bond is mostly metallic while the Al-As (from the GaAs layer) bond is weakly covalent. The Sr participates in two distinct types of bonding with part of its electric charge going to the oxygen atoms in the lower accommodating buffer layer 104 comprising SrzBa!-zTiO3 to participate in ionic bonding and the other part of its valence charge being donated to Al in a way that is typically carried out with Zintl phase materials. The amount of the charge transfer depends on the relative electronegativity of elements comprising the template layer 130 as well as on the interatomic distance. In this example, Al assumes an sp3 hybridization and can readily form bonds with monocrystalline material layer 126, which in this example, comprises compound semiconductor material GaAs.
The compliant substrate produced by use of the Zintl type template layer used in this embodiment can absorb a large strain without a significant energy cost. In the above example, the bond strength of the Al is adjusted by changing the volume of the SrAl2 layer thereby making the device tunable for specific applications which include the monolithic integration of DI-N and Si devices and the monolithic integration of high-k dielectric materials for CMOS technology.
Clearly, those embodiments specifically describing structures having compound semiconductor portions and Group IN semiconductor portions, are meant to illustrate embodiments of the present invention and not limit the present invention. There are a multiplicity of other combinations and other embodiments of the present invention. For example, the present invention includes structures and methods for fabricating material layers which form semiconductor structures, devices and integrated circuits including other layers such as metal and non-metal layers. More specifically, the invention includes structures and methods for forming a compliant substrate which is used in the fabrication of semiconductor structures, devices and integrated circuits and the material layers suitable for fabricating those structures, devices, and integrated circuits. By using embodiments of the present invention, it is now simpler to integrate devices that include monocrystalline layers comprising semiconductor and compound semiconductor materials as well as other material layers that are used to form those devices with other components that work better or are easily and/or inexpensively formed within semiconductor or compound semiconductor materials. This allows a device to be shrunk, the manufacturing costs to decrease, and yield and reliability to increase.
In accordance with one embodiment of this invention, a monocrystalline semiconductor or compound semiconductor wafer can be used in forming monocrystalline material layers over the wafer. In this manner, the wafer is essentially a "handle" wafer used during the fabrication of semiconductor electrical components within a monocrystalline layer overlying the wafer. Therefore, electrical components can be formed within semiconductor materials over a wafer of at least approximately 200 millimeters in diameter and possibly at least approximately 300 millimeters.
By the use of this type of substrate, a relatively inexpensive "handle" wafer overcomes the fragile nature of compound semiconductor or other monocrystalline material wafers by placing them over a relatively more durable and easy to fabricate base material. Therefore, an integrated circuit can be formed such that all electrical components, and particularly all active electronic devices, can be formed within or using the monocrystalline material layer even though the substrate itself may include a monocrystalline semiconductor material. Fabrication costs for compound semiconductor devices and other devices employing non-silicon monocrystalline materials should decrease because larger substrates can be processed more economically and more readily compared to the relatively smaller and more fragile substrates (e.g. conventional compound semiconductor wafers).
The formation of a device structure formed of GaN film in accordance with another embodiment of the invention is illustrated schematically in cross-section in Figs. 18-20. Like the previously described embodiments referred to in Figs. 1-3, this embodiment of the invention involves the process of forming a compliant substrate utilizing the epitaxial growth of single crystal oxides.
Turning now to Fig. 18, to fabricate a GaN film structure, a monocrystalUne substrate 200 functions as the starting material. Substrate may include a monocrystalline material such as that comprising layer 22 with reference to Figs. 1-3, but is preferably Si and is more preferably Si (100). An accommodating buffer layer 202 is then grown epitaxially over substrate 200 and an amorphous intermediate layer 204 may be formed between substrate 200 and buffer layer 202 by the oxidation of substrate 200 during the growth of buffer layer 202. Buffer layer 202 may be formed of a monocrystalline oxide or nitride material such as that comprising layers 24, 54, 74 and 104 with reference to Figs. 1, 9 A, 11 and 15, respectively. Preferably, buffer layer 202 is comprised of SrzBaι-zTiO3; SrzBaι-zZrO3> SrzBa!- zHfO3, SrzBai-zSnOs or CaTiO3 epitaxially grown on substrate 200. A monocrystalline material layer 206 is then epitaxially deposited over buffer layer 202. Monocrystalline material layer 206 may be comprised of a monocrystalline material such as that comprising layer 26 with reference to Fig. 1, layer 66 with reference to Fig. 9D, layer 96 with reference to Fig. 14 and layer 126 with reference to Fig. 17, but is preferably GaAs (100), GaAlAs (100), AlAs (100) or Si (100). Monocrystalline material layer 206 may have a thickness in the range of from about 10 angstroms to about 200 angstroms, but has a thickness preferably in the range of from about 20 angstroms to about 50 angstroms. It will be appreciated that, while not shown, the structure in Fig. 18 may include a template layer, formed of material such as that comprising layers 30, 60, 81 and 130, between any adjacent monocrystalline layers as described herein. Further, while not shown, it will be appreciated that an additional monocrystalline material layer, similar to layer 38 with reference to Fig. 3, may be formed overlying buffer layer 202 and underlying monocrystalline material layer 206. Referring to Fig. 19, the structure shown is subjected to a nitrogen source under conditions sufficient to nitride monocrystalline layer 206 partially or totally to form a cubic nitride layer 208. For example, nitridation may occur using RF plasma, ECR plasma or Eximer laser with N2 or NH3 as the nitrogen source at a temperature of from about room temperature to about 700 degrees Celsius. Accordingly, when monocrystalline material layer 206 is GaAs, upon nitridation, nitride layer 208 comprises partially or totally GaN; when monocrystalline material layer 206 is GaAlAs, nitride layer 208 comprises partially or totally GaAIN; when monocrystalline material layer 206 comprises AlAs, nitride layer 208 comprises partially or totally A1N; and when monocrystalline material layer 206 comprises Si, nitride layer 208 comprises partially or totally SiN. The structure is then annealed at a temperature of about 700 degrees Celsius to about 900 degrees Celsius to form an amorphous layer 210, as illustrated in Fig. 20, similar to layer 36 described with reference to Fig. 3. An additional layer of nitride material, such as GaN, GalnN or AlGaN, may then be grown on nitride layer 208 for subsequent fabrication of devices, such as light emitting devices, high temperature devices and other devices that may take advantage of the high quality crystalline nature of nitride layer 208.
By fabricating GaN (including A1N, GalnN, SiN, and AlGaN) films on compliant substrates as described above, electrical and optical devices may be achieved which realize a number of advantages. Use of a compliant substrate in the devices reduce stress due to lattice mismatch between the substrate and the GaN film. Dislocation density in the GaN films is also improved.
In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarding in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, solution to occur or become more pronounced are not to be constructed as critical, required, or essential features or elements of any or all of the claims. As used, herein, the terms "comprises," "comprising" or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Claims

We claim:
1. A semiconductor structure comprising: a monocrystalline substrate; an amorphous layer formed on the substrate; and a first monocrystalline nitride material layer overlying the amorphous layer and formed of at least one from the group comprising GaN, GalnN, AlGaN, SiN and A1N.
2. The semiconductor structure of claim 1, wherein the amorphous layer comprises an oxide formed as a monocrystalline oxide and subsequently heat treated to convert the monocrystalline oxide to an amorphous oxide.
3. The semiconductor structure of claim 1, wherein the first monocrystalline nitride material layer is formed by nitridation of a first monocrystalline material layer selected from the group comprising GaAs, GalnAs, AlGaAs, Si and AlAs.
4. The semiconductor structure of claim 1, wherein the substrate comprises silicon.
5. The semiconductor structure of claim 2, wherein the monocrystalUne oxide is formed of material selected from the group comprising SrJBa^TiOs, SrzBat-zZrOs, SrzBat-zH Os, SrzBai-zSnOs and CaTiO3, where z ranges from 0 to approximately 1.
6. The semiconductor structure of claim 1, further comprising a monocrystalline material layer formed overlying the amorphous layer and underlying the first monocrystalline nitride material layer.
7. The semiconductor structure of claim 1, further comprising a template layer positioned between the amorphous layer and the monocrystalline nitride material layer.
8. The semiconductor structure of claim 7, wherein the template layer is formed of material selected from the group comprising Ti-As, Sr-O-As, Sr-Ga-O, Ti-O-As, or Sr-Al-O.
9. The semiconductor structure of claim 7, wherein the template layer comprises a Zintl-type phase material.
10. The semiconductor structure of claim 9, wherein the Zintl-type phase material comprises at least one of SrAl2, SrAL*, (MgCaYb)Ga2, (Ca, Sr, Eu, Yb)In2, BaGe2As, and SrSn2As2.
11. The semiconductor structure of claim 7, wherein the template layer comprises a surfactant material.
12. The semiconductor structure of claim 11, wherein the surfactant material comprises at least one of Al, In, and Ga.
13. The semiconductor structure of claim 11, wherein the template layer further comprises a capping layer.
14. The semiconductor structure of claim 13, wherein the capping layer is formed by exposing the surfactant material to a cap-inducing material.
15. The semiconductor structure of claim 14, wherein the cap-inducing material comprises at least one of As, P, Sb, and N.
16. The semiconductor structure of claim 13, wherein the surfactant comprises Al, and the capping layer comprises Al2Sr.
17. The semiconductor structure of claim 3, wherein said first monocrystalUne material layer has a thickness in the range of from about 20 angstroms to about 50 angstroms.
18. A process for fabricating a semiconductor structure comprising: providing a monocrystalline substrate; epitaxially growing an accommodating buffer layer overlying the substrate; epitaxially growing a first monocrystalline material layer overlying the accommodating buffer layer; nitriding at least a portion of the first monocrystalline material layer to form a first monocrystalline nitride material layer; and heat treating the structure to convert the accommodating buffer layer to an amorphous layer.
19. The process of claim 18, further comprising forming a second monocrystalline nitride material layer overlying the first monocrystalline nitride material layer.
20. The process of claim 18, further comprising forming an amorphous oxide layer underlying the accommodating buffer layer during epitaxially growing the accommodating buffer layer.
21. The process of claim 18, wherein providing a monocrystalline substrate comprises providing a substrate formed of silicon.
22. The process of claim 18, further comprising epitaxially growing a second monocrystalline material layer overlying the accommodating buffer layer and underlying the first monocrystalline material layer.
23. The process of claim 18, wherein epitaxially growing a first monocrystalline material layer comprises epitaxially growing a first monocrystalline material layer selected from the group comprising GaAs, GalnAs, AlGaAs, Si and AlAs.
24. The process of claim 18, wherein epitaxially growing an accommodating buffer layer comprises epitaxially growing an accommodating buffer layer selected from the group comprising SrzBa!-z,TiO3, SrzBat-zjZrOs, SrzBa^HfOs, SrzBa^SnOs, and CaTiO3, where z ranges from 0 to approximately 1.
25. The process of claim 18, wherein each of the steps of epitaxially growing comprises epitaxially growing by a process selected from the group consisting of MBE, MOCVD, MEE, CVD, PVD, PLD, CSD and ALE.
26. The process of claim 18, wherein nitriding comprises nitriding by a process selected from the group comprising RF plasma processing, ECR plasma processing, or Eximer laser processing.
27. The process of claim 18, wherein heat treating comprises subjecting the structure to a temperature in the range of from about 700 degrees Celsius to about 900 degrees Celsius.
28. The process of claim 18, further comprising forming a template layer positioned between the accommodating buffer layer and the first monocrystalUne material layer.
29. The process of claim 18, wherein the nitriding comprises nitriding to form a first monocrystalline nitride material layer formed of material selected from the group comprising GaN, GalnN, AlGaN, SiN and A1N.
30. The process of claim 18, wherein epitaxially growing a first monocrystalline material layer comprises epitaxially growing a first monocrystalline material layer having a thickness in the range of from about 20 angstroms to about 50 angstroms.
31. A semiconductor structure fabricated from a process comprising: providing a monocrystalUne substrate; epitaxially growing an accommodating buffer layer overlying the substrate; epitaxially growing a first monocrystalline material layer overlying the accommodating buffer layer; nitriding at least a portion of the first monocrystalline material layer to form a first monocrystalline nitride material layer; and heat treating the structure to convert the accommodating buffer layer to an amorphous layer.
32. The semiconductor structure of claim 31, wherein the process further comprises forming a second monocrystalline nitride material layer overlying the first monocrystalline nitride material layer.
33. The semiconductor structure of claim 31, wherein the process further comprises forming an amorphous oxide layer underlying the accommodating buffer layer during epitaxially growing the accommodating buffer layer.
34. The semiconductor structure of claim 31, wherein providing a monocrystalline substrate comprises providing a substrate formed of silicon.
35. The semiconductor structure of claim 31, wherein the process further comprises epitaxially growing a second monocrystalline material layer overlying the accommodating buffer layer and underlying the first monocrystalline material layer.
36. The semiconductor structure of claim 31, wherein epitaxially growing a first monocrystalline material layer comprises epitaxially growing a first monocrystalline material layer selected from the group comprising GaAs, GalnAs, AlGaAs, Si and AlAs.
37. The semiconductor structure of claim 31, wherein epitaxially growing an accommodating buffer layer comprises epitaxially growing an accommodating buffer layer selected from the group comprising SrzBa^TiOs, SrzBat-zZrOs, SrzBa^zHfOs. SrzBa^zSnOs and CaTiO3, where z ranges from 0 to approximately 1.
38. The semiconductor structure of claim 31, wherein each of the steps of epitaxially growing comprises epitaxially growing by a process selected from the group consisting of MBE, MOCVD, MEE, CVD, PVD, PLD, CSD and ALE.
39. The semiconductor structure of claim 31, wherein nitriding comprises nitriding by a process selected from the group comprising RF plasma processing, ECR plasma processing, or Eximer laser processing.
40. The semiconductor structure of claim 31, wherein heat treating comprises subjecting the structure to a temperature in the range of from about 700 degrees Celsius to about 900 degrees Celsius.
41. The semiconductor structure of claim 31, wherein the process further comprises forming a template layer positioned between the accommodating buffer layer and the first monocrystalline material layer.
42. The semiconductor structure of claim 31, wherein the nitriding comprises nitriding to form a first monocrystalline nitride material layer formed of material selected from the group comprising GaN, GalnN, AlGaN, SiN and A1N.
43. The semiconductor structure of claim 31, wherein epitaxially growing a first monocrystalline material layer comprises epitaxially growing a first monocrystalline material layer having a thickness in the range of from about 10 angstroms to about 100 angstroms.
PCT/US2001/046663 2001-01-19 2001-12-06 Gan layer on a substrate with an amorphous layer WO2002058164A2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006012298A1 (en) * 2004-06-28 2006-02-02 Nitronex Corporation Gallium nitride material and methods associated with the same

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004017425A1 (en) * 2002-08-16 2004-02-26 Midwest Research Institute Multi-junction, monolithic solar cell with active silicon substrate
US20060162767A1 (en) * 2002-08-16 2006-07-27 Angelo Mascarenhas Multi-junction, monolithic solar cell with active silicon substrate
EP1583139A1 (en) * 2004-04-02 2005-10-05 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Method for depositing a group III-nitride material on a silicon substrate and device therefor
US8431253B2 (en) * 2004-07-08 2013-04-30 Los Alamos National Security, Llc Cubic nitride templates
JP2007123824A (en) * 2005-09-27 2007-05-17 Toyoda Gosei Co Ltd Electronic device using group-iii nitride based compound semiconductor
DE102005056950A1 (en) * 2005-09-30 2007-04-05 Osram Opto Semiconductors Gmbh Semiconductor substrate of GaAs and semiconductor device
US7670928B2 (en) * 2006-06-14 2010-03-02 Intel Corporation Ultra-thin oxide bonding for S1 to S1 dual orientation bonding
FR2921200B1 (en) * 2007-09-18 2009-12-18 Centre Nat Rech Scient EPITAXIC MONOLITHIC SEMICONDUCTOR HETEROSTRUCTURES AND PROCESS FOR THEIR MANUFACTURE
DE102008042212A1 (en) * 2008-09-19 2010-04-01 Carl Zeiss Smt Ag Reflective optical element and method for its production
EP2206808B1 (en) * 2008-12-23 2017-07-12 Imec Method for manufacturing a mono-crystalline semiconductor layer on a substrate
TWI381501B (en) * 2009-01-17 2013-01-01 Univ Ishou An isolation layer substrate with metal ion migration and its encapsulation structure
US8299351B2 (en) * 2009-02-24 2012-10-30 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Epitaxial growth of III-V compounds on (111) silicon for solar cells
CN102484166B (en) * 2009-09-07 2015-09-02 东电电子太阳能股份公司 Manufacture the method for photovoltaic cell structure
JP2012015304A (en) * 2010-06-30 2012-01-19 Sumitomo Electric Ind Ltd Semiconductor device
US20130025531A1 (en) * 2011-07-25 2013-01-31 Capano Michael A Methods for modifying crystallographic symmetry on the surface of a silicon wafer
US20130032810A1 (en) * 2011-08-03 2013-02-07 Bridgelux, Inc. Led on silicon substrate using zinc-sulfide as buffer layer
KR20130081956A (en) 2012-01-10 2013-07-18 삼성전자주식회사 Method for growing nitride semiconductor
US10937649B2 (en) * 2012-06-18 2021-03-02 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Epitaxial growth of cubic and hexagonal InN films and their alloys with AlN and GaN
KR102311677B1 (en) 2014-08-13 2021-10-12 삼성전자주식회사 Semiconductor device and method of manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6100578A (en) * 1997-08-29 2000-08-08 Sony Corporation Silicon-based functional matrix substrate and optical integrated oxide device
WO2001004943A1 (en) * 1999-07-07 2001-01-18 Matsushita Electric Industrial Co., Ltd. Multilayered body, method for fabricating multilayered body, and semiconductor device
WO2002047127A2 (en) * 2000-12-08 2002-06-13 Motorola, Inc. Pyroelectric device on a monocrystalline semiconductor substrate

Family Cites Families (252)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US563543A (en) * 1896-07-07 Baling-press
US3617951A (en) 1968-11-21 1971-11-02 Western Microwave Lab Inc Broadband circulator or isolator of the strip line or microstrip type
US3670213A (en) 1969-05-24 1972-06-13 Tokyo Shibaura Electric Co Semiconductor photosensitive device with a rare earth oxide compound forming a rectifying junction
US4404265A (en) 1969-10-01 1983-09-13 Rockwell International Corporation Epitaxial composite and method of making
US3766370A (en) 1971-05-14 1973-10-16 Hewlett Packard Co Elementary floating point cordic function processor and shifter
US3802967A (en) 1971-08-27 1974-04-09 Rca Corp Iii-v compound on insulating substrate and its preparation and use
US3914137A (en) 1971-10-06 1975-10-21 Motorola Inc Method of manufacturing a light coupled monolithic circuit by selective epitaxial deposition
US3758199A (en) 1971-11-22 1973-09-11 Sperry Rand Corp Piezoelectrically actuated light deflector
US3818451A (en) 1972-03-15 1974-06-18 Motorola Inc Light-emitting and light-receiving logic array
US4006989A (en) 1972-10-02 1977-02-08 Raytheon Company Laser gyroscope
US3935031A (en) 1973-05-07 1976-01-27 New England Institute, Inc. Photovoltaic cell with enhanced power output
US4084130A (en) 1974-01-18 1978-04-11 Texas Instruments Incorporated Laser for integrated optical circuits
US4120588A (en) * 1976-07-12 1978-10-17 Erik Chaum Multiple path configuration for a laser interferometer
NL7710164A (en) 1977-09-16 1979-03-20 Philips Nv METHOD OF TREATING A SINGLE CRYSTAL LINE BODY.
US4174422A (en) 1977-12-30 1979-11-13 International Business Machines Corporation Growing epitaxial films when the misfit between film and substrate is large
US4284329A (en) 1978-01-03 1981-08-18 Raytheon Company Laser gyroscope system
US4146297A (en) * 1978-01-16 1979-03-27 Bell Telephone Laboratories, Incorporated Tunable optical waveguide directional coupler filter
US4174504A (en) 1978-01-25 1979-11-13 United Technologies Corporation Apparatus and method for cavity dumping a Q-switched laser
US4242595A (en) 1978-07-27 1980-12-30 University Of Southern California Tunnel diode load for ultra-fast low power switching circuits
US4297656A (en) 1979-03-23 1981-10-27 Harris Corporation Plural frequency oscillator employing multiple fiber-optic delay line
FR2453423A1 (en) 1979-04-04 1980-10-31 Quantel Sa THICK OPTICAL ELEMENT WITH VARIABLE CURVATURE
JPS5696834A (en) 1979-12-28 1981-08-05 Mitsubishi Monsanto Chem Co Compound semiconductor epitaxial wafer and manufacture thereof
US4424589A (en) 1980-04-11 1984-01-03 Coulter Systems Corporation Flat bed scanner system and method
US4452720A (en) 1980-06-04 1984-06-05 Teijin Limited Fluorescent composition having the ability to change wavelengths of light, shaped article of said composition as a light wavelength converting element and device for converting optical energy to electrical energy using said element
US4289920A (en) 1980-06-23 1981-09-15 International Business Machines Corporation Multiple bandgap solar cell on transparent substrate
DE3168688D1 (en) 1980-11-06 1985-03-14 Toshiba Kk Method for manufacturing a semiconductor device
US4442590A (en) 1980-11-17 1984-04-17 Ball Corporation Monolithic microwave integrated circuit with integral array antenna
US4392297A (en) 1980-11-20 1983-07-12 Spire Corporation Process of making thin film high efficiency solar cells
GB2096785B (en) 1981-04-09 1984-10-10 Standard Telephones Cables Ltd Integrated optic device
JPS57177583A (en) 1981-04-14 1982-11-01 Int Standard Electric Corp Holl effect device
JPS57176785A (en) 1981-04-22 1982-10-30 Hitachi Ltd Semiconductor laser device
GB2115996B (en) 1981-11-02 1985-03-20 Kramer Kane N Portable data processing and storage system
US4439014A (en) 1981-11-13 1984-03-27 Mcdonnell Douglas Corporation Low voltage electro-optic modulator
US4626878A (en) 1981-12-11 1986-12-02 Sanyo Electric Co., Ltd. Semiconductor optical logical device
US4525871A (en) 1982-02-03 1985-06-25 Massachusetts Institute Of Technology High speed optoelectronic mixer
US4482422A (en) 1982-02-26 1984-11-13 Rca Corporation Method for growing a low defect monocrystalline layer on a mask
JPS58158944A (en) 1982-03-16 1983-09-21 Futaba Corp Semiconductor device
US4484332A (en) 1982-06-02 1984-11-20 The United States Of America As Represented By The Secretary Of The Air Force Multiple double heterojunction buried laser device
US4482906A (en) 1982-06-30 1984-11-13 International Business Machines Corporation Gallium aluminum arsenide integrated circuit structure using germanium
US4594000A (en) 1983-04-04 1986-06-10 Ball Corporation Method and apparatus for optically measuring distance and velocity
US4756007A (en) 1984-03-08 1988-07-05 Codex Corporation Adaptive communication rate modem
US4629821A (en) 1984-08-16 1986-12-16 Polaroid Corporation Photovoltaic cell
JPH069334B2 (en) 1984-09-03 1994-02-02 株式会社東芝 Optical / electrical integrated device
US4773063A (en) 1984-11-13 1988-09-20 University Of Delaware Optical wavelength division multiplexing/demultiplexing system
US4661176A (en) 1985-02-27 1987-04-28 The United States Of America As Represented By The Secretary Of The Air Force Process for improving the quality of epitaxial silicon films grown on insulating substrates utilizing oxygen ion conductor substrates
US4748485A (en) 1985-03-21 1988-05-31 Hughes Aircraft Company Opposed dual-gate hybrid structure for three-dimensional integrated circuits
JPS61255074A (en) 1985-05-08 1986-11-12 Mitsubishi Electric Corp Photoelectric conversion semiconductor device
US4846926A (en) 1985-08-26 1989-07-11 Ford Aerospace & Communications Corporation HcCdTe epitaxially grown on crystalline support
EP0214610B1 (en) 1985-09-03 1990-12-05 Daido Tokushuko Kabushiki Kaisha Epitaxial gallium arsenide semiconductor wafer and method of producing the same
JPS6263828A (en) 1985-09-06 1987-03-20 Yokogawa Electric Corp Vibration type transducer and its manufacture
US4695120A (en) * 1985-09-26 1987-09-22 The United States Of America As Represented By The Secretary Of The Army Optic-coupled integrated circuits
US5140387A (en) * 1985-11-08 1992-08-18 Lockheed Missiles & Space Company, Inc. Semiconductor device in which gate region is precisely aligned with source and drain regions
JPS62119196A (en) 1985-11-18 1987-05-30 Univ Nagoya Method for growing compound semiconductor
US4872046A (en) 1986-01-24 1989-10-03 University Of Illinois Heterojunction semiconductor device with <001> tilt
FR2595509B1 (en) 1986-03-07 1988-05-13 Thomson Csf COMPONENT IN SEMICONDUCTOR MATERIAL EPITAXIA ON A SUBSTRATE WITH DIFFERENT MESH PARAMETER AND APPLICATION TO VARIOUS SEMICONDUCTOR COMPONENTS
US4804866A (en) * 1986-03-24 1989-02-14 Matsushita Electric Works, Ltd. Solid state relay
US4777613A (en) 1986-04-01 1988-10-11 Motorola Inc. Floating point numeric data processor
US4901133A (en) 1986-04-02 1990-02-13 Texas Instruments Incorporated Multilayer semi-insulating film for hermetic wafer passivation and method for making same
US4774205A (en) 1986-06-13 1988-09-27 Massachusetts Institute Of Technology Monolithic integration of silicon and gallium arsenide devices
US4891091A (en) 1986-07-14 1990-01-02 Gte Laboratories Incorporated Method of epitaxially growing compound semiconductor materials
US4866489A (en) * 1986-07-22 1989-09-12 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US4888202A (en) 1986-07-31 1989-12-19 Nippon Telegraph And Telephone Corporation Method of manufacturing thin compound oxide film and apparatus for manufacturing thin oxide film
JP2516604B2 (en) 1986-10-17 1996-07-24 キヤノン株式会社 Method for manufacturing complementary MOS integrated circuit device
US4723321A (en) 1986-11-07 1988-02-02 American Telephone And Telegraph Company, At&T Bell Laboratories Techniques for cross-polarization cancellation in a space diversity radio system
JPH07120835B2 (en) 1986-12-26 1995-12-20 松下電器産業株式会社 Optical integrated circuit
US4772929A (en) 1987-01-09 1988-09-20 Sprague Electric Company Hall sensor with integrated pole pieces
US4876208A (en) 1987-01-30 1989-10-24 Yellowstone Diagnostics Corporation Diffraction immunoassay apparatus and method
US4868376A (en) 1987-05-15 1989-09-19 Smartcard International Inc. Intelligent portable interactive personal data system
US4815084A (en) 1987-05-20 1989-03-21 Spectra Diode Laboratories, Inc. Semiconductor laser with integrated optical elements
US4801184A (en) * 1987-06-15 1989-01-31 Eastman Kodak Company Integrated optical read/write head and apparatus incorporating same
JPS6414949A (en) 1987-07-08 1989-01-19 Nec Corp Semiconductor device and manufacture of the same
JPH0766922B2 (en) 1987-07-29 1995-07-19 株式会社村田製作所 Method for manufacturing semiconductor device
GB8718552D0 (en) * 1987-08-05 1987-09-09 British Railways Board Track to train communications systems
US5081062A (en) * 1987-08-27 1992-01-14 Prahalad Vasudev Monolithic integration of silicon on insulator and gallium arsenide semiconductor technologies
FI81926C (en) 1987-09-29 1990-12-10 Nokia Oy Ab FOERFARANDE FOER UPPBYGGNING AV GAAS-FILMER PAO SI- OCH GAAS-SUBSTRATER.
JPH0695554B2 (en) 1987-10-12 1994-11-24 工業技術院長 Method for forming single crystal magnesia spinel film
US4885376A (en) 1987-10-13 1989-12-05 Iowa State University Research Foundation, Inc. New types of organometallic reagents and catalysts for asymmetric synthesis
US4802182A (en) 1987-11-05 1989-01-31 Xerox Corporation Monolithic two dimensional waveguide coupled cavity laser/modulator
US4981714A (en) 1987-12-14 1991-01-01 Sharp Kabushiki Kaisha Method of producing ferroelectric LiNb1-31 x Tax O3 0<x<1) thin film by activated evaporation
JPH01207920A (en) 1988-02-16 1989-08-21 Oki Electric Ind Co Ltd Manufacture of inp semiconductor thin film
JP2691721B2 (en) 1988-03-04 1997-12-17 富士通株式会社 Semiconductor thin film manufacturing method
US4912087A (en) 1988-04-15 1990-03-27 Ford Motor Company Rapid thermal annealing of superconducting oxide precursor films on Si and SiO2 substrates
US5130269A (en) * 1988-04-27 1992-07-14 Fujitsu Limited Hetero-epitaxially grown compound semiconductor substrate and a method of growing the same
US5063166A (en) 1988-04-29 1991-11-05 Sri International Method of forming a low dislocation density semiconductor device
US5238869A (en) * 1988-07-25 1993-08-24 Texas Instruments Incorporated Method of forming an epitaxial layer on a heterointerface
US4910164A (en) 1988-07-27 1990-03-20 Texas Instruments Incorporated Method of making planarized heterostructures using selective epitaxial growth
US4889402A (en) 1988-08-31 1989-12-26 American Telephone And Telegraph Company, At&T Bell Laboratories Electro-optic polarization modulation in multi-electrode waveguides
US4963949A (en) 1988-09-30 1990-10-16 The United States Of America As Represented Of The United States Department Of Energy Substrate structures for InP-based devices
US4952420A (en) 1988-10-12 1990-08-28 Advanced Dielectric Technologies, Inc. Vapor deposition patterning method
JPH02105910A (en) * 1988-10-14 1990-04-18 Hitachi Ltd Logic integrated circuit
EP0365875B1 (en) * 1988-10-28 1995-08-09 Texas Instruments Incorporated Capped anneal
US5286985A (en) * 1988-11-04 1994-02-15 Texas Instruments Incorporated Interface circuit operable to perform level shifting between a first type of device and a second type of device
US5063081A (en) 1988-11-14 1991-11-05 I-Stat Corporation Method of manufacturing a plurality of uniform microfabricated sensing devices having an immobilized ligand receptor
US5087829A (en) * 1988-12-07 1992-02-11 Hitachi, Ltd. High speed clock distribution system
US4965649A (en) 1988-12-23 1990-10-23 Ford Aerospace Corporation Manufacture of monolithic infrared focal plane arrays
US5028563A (en) * 1989-02-24 1991-07-02 Laser Photonics, Inc. Method for making low tuning rate single mode PbTe/PbEuSeTe buried heterostructure tunable diode lasers and arrays
US4999842A (en) * 1989-03-01 1991-03-12 At&T Bell Laboratories Quantum well vertical cavity laser
US4990974A (en) 1989-03-02 1991-02-05 Thunderbird Technologies, Inc. Fermi threshold field effect transistor
US5237233A (en) * 1989-03-03 1993-08-17 E. F. Johnson Company Optoelectronic active circuit element
US5057694A (en) * 1989-03-15 1991-10-15 Matsushita Electric Works, Ltd. Optoelectronic relay circuit having charging path formed by a switching transistor and a rectifying diode
US4934777A (en) * 1989-03-21 1990-06-19 Pco, Inc. Cascaded recirculating transmission line without bending loss limitations
US5198269A (en) * 1989-04-24 1993-03-30 Battelle Memorial Institute Process for making sol-gel deposited ferroelectric thin films insensitive to their substrates
US5067809A (en) 1989-06-09 1991-11-26 Oki Electric Industry Co., Ltd. Opto-semiconductor device and method of fabrication of the same
US5399898A (en) * 1992-07-17 1995-03-21 Lsi Logic Corporation Multi-chip semiconductor arrangements using flip chip dies
US5055445A (en) 1989-09-25 1991-10-08 Litton Systems, Inc. Method of forming oxidic high Tc superconducting materials on substantially lattice matched monocrystalline substrates utilizing liquid phase epitaxy
US4959702A (en) * 1989-10-05 1990-09-25 Motorola, Inc. Si-GaP-Si heterojunction bipolar transistor (HBT) on Si substrate
US5051790A (en) 1989-12-22 1991-09-24 David Sarnoff Research Center, Inc. Optoelectronic interconnections for integrated circuits
JPH088214B2 (en) * 1990-01-19 1996-01-29 三菱電機株式会社 Semiconductor device
US5310707A (en) * 1990-03-28 1994-05-10 Superconductivity Research Laboratory International Substrate material for the preparation of oxide superconductors
US5122852A (en) * 1990-04-23 1992-06-16 Bell Communications Research, Inc. Grafted-crystal-film integrated optics and optoelectronic devices
US5018816A (en) * 1990-06-11 1991-05-28 Amp Incorporated Optical delay switch and variable delay system
US5188976A (en) * 1990-07-13 1993-02-23 Hitachi, Ltd. Manufacturing method of non-volatile semiconductor memory device
GB2250751B (en) * 1990-08-24 1995-04-12 Kawasaki Heavy Ind Ltd Process for the production of dielectric thin films
DE4027024A1 (en) * 1990-08-27 1992-03-05 Standard Elektrik Lorenz Ag FIBER GYRO
US5281834A (en) * 1990-08-31 1994-01-25 Motorola, Inc. Non-silicon and silicon bonded structure and method of manufacture
US5064781A (en) 1990-08-31 1991-11-12 Motorola, Inc. Method of fabricating integrated silicon and non-silicon semiconductor devices
US5060031A (en) 1990-09-18 1991-10-22 Motorola, Inc Complementary heterojunction field effect transistor with an anisotype N+ ga-channel devices
US5119448A (en) * 1990-09-21 1992-06-02 Tacan Corporation Modular micro-optical systems and method of making such systems
US5216359A (en) * 1991-01-18 1993-06-01 University Of North Carolina Electro-optical method and apparatus for testing integrated circuits
US5387811A (en) * 1991-01-25 1995-02-07 Nec Corporation Composite semiconductor device with a particular bipolar structure
KR940005454B1 (en) * 1991-04-03 1994-06-18 삼성전자 주식회사 Compound semiconductor device
SE468267B (en) * 1991-04-10 1992-11-30 Ericsson Telefon Ab L M TERMINAL FOR A FREQUENCY PART, OPTICAL COMMUNICATION SYSTEM
US5225031A (en) * 1991-04-10 1993-07-06 Martin Marietta Energy Systems, Inc. Process for depositing an oxide epitaxially onto a silicon substrate and structures prepared with the process
US5482003A (en) * 1991-04-10 1996-01-09 Martin Marietta Energy Systems, Inc. Process for depositing epitaxial alkaline earth oxide onto a substrate and structures prepared with the process
US5523879A (en) * 1991-04-26 1996-06-04 Fuji Xerox Co., Ltd. Optical link amplifier and a wavelength multiplex laser oscillator
US5185589A (en) * 1991-05-17 1993-02-09 Westinghouse Electric Corp. Microwave film bulk acoustic resonator and manifolded filter bank
US5194397A (en) * 1991-06-05 1993-03-16 International Business Machines Corporation Method for controlling interfacial oxide at a polycrystalline/monocrystalline silicon interface
EP0584410A1 (en) * 1991-07-05 1994-03-02 Conductus, Inc. Superconducting electronic structures and methods of preparing same
US5148504A (en) * 1991-10-16 1992-09-15 At&T Bell Laboratories Optical integrated circuit designed to operate by use of photons
US5283462A (en) * 1991-11-04 1994-02-01 Motorola, Inc. Integrated distributed inductive-capacitive network
US5404373A (en) * 1991-11-08 1995-04-04 University Of New Mexico Electro-optical device
US5397428A (en) * 1991-12-20 1995-03-14 The University Of North Carolina At Chapel Hill Nucleation enhancement for chemical vapor deposition of diamond
JP3250673B2 (en) * 1992-01-31 2002-01-28 キヤノン株式会社 Semiconductor element substrate and method of manufacturing the same
US5446719A (en) * 1992-02-05 1995-08-29 Sharp Kabushiki Kaisha Optical information reproducing apparatus
US5155658A (en) * 1992-03-05 1992-10-13 Bell Communications Research, Inc. Crystallographically aligned ferroelectric films usable in memories and method of crystallographically aligning perovskite films
JP3379106B2 (en) * 1992-04-23 2003-02-17 セイコーエプソン株式会社 Liquid jet head
EP0568064B1 (en) * 1992-05-01 1999-07-14 Texas Instruments Incorporated Pb/Bi-containing high-dielectric constant oxides using a non-Pb/Bi-containing perovskite as a buffer layer
US5326721A (en) * 1992-05-01 1994-07-05 Texas Instruments Incorporated Method of fabricating high-dielectric constant oxides on semiconductors using a GE buffer layer
WO1994003931A1 (en) * 1992-08-07 1994-02-17 Asahi Kasei Kogyo Kabushiki Kaisha Nitride based semiconductor device and manufacture thereof
JPH0667046A (en) * 1992-08-21 1994-03-11 Sharp Corp Optical integrated circuit
JPH06151872A (en) * 1992-11-09 1994-05-31 Mitsubishi Kasei Corp Fet device
DE69331538T2 (en) * 1992-12-01 2002-08-29 Matsushita Electric Ind Co Ltd Process for producing an electrical thin film
US5248564A (en) * 1992-12-09 1993-09-28 Bell Communications Research, Inc. C-axis perovskite thin films grown on silicon dioxide
JP3047656B2 (en) * 1993-01-12 2000-05-29 株式会社村田製作所 Method for producing InSb thin film
KR100293596B1 (en) * 1993-01-27 2001-09-17 가나이 쓰도무 Clock Distribution Circuit in LSI
US5293050A (en) * 1993-03-25 1994-03-08 International Business Machines Corporation Semiconductor quantum dot light emitting/detecting devices
US5452118A (en) * 1993-04-20 1995-09-19 Spire Corporation Optical heterodyne receiver for fiber optic communications system
US5480829A (en) * 1993-06-25 1996-01-02 Motorola, Inc. Method of making a III-V complementary heterostructure device with compatible non-gold ohmic contacts
US5572040A (en) * 1993-07-12 1996-11-05 Peregrine Semiconductor Corporation High-frequency wireless communication system on a single ultrathin silicon on sapphire chip
US5291866A (en) * 1993-07-20 1994-03-08 Kosa David R Pulse charger
US6139483A (en) * 1993-07-27 2000-10-31 Texas Instruments Incorporated Method of forming lateral resonant tunneling devices
US5394489A (en) * 1993-07-27 1995-02-28 At&T Corp. Wavelength division multiplexed optical communication transmitters
JPH07114746A (en) * 1993-08-25 1995-05-02 Sony Corp Optical device
JPH0766366A (en) * 1993-08-26 1995-03-10 Hitachi Ltd Semiconductor multilayered structure and semiconductor device using same
JPH07133192A (en) * 1993-11-04 1995-05-23 Sumitomo Electric Ind Ltd Film forming device and film forming method
JP3395318B2 (en) * 1994-01-07 2003-04-14 住友化学工業株式会社 Method for growing group 3-5 compound semiconductor crystal
US5561305A (en) * 1994-02-16 1996-10-01 The United States Of America As Represented By The Secretary Of The Army Method and apparatus for performing internal device structure analysis of a dual channel transistor by multiple-frequency Schubnikov-de Haas analysis
JP3360105B2 (en) * 1994-03-04 2002-12-24 富士通株式会社 Method for manufacturing semiconductor device
US5481102A (en) * 1994-03-31 1996-01-02 Hazelrigg, Jr.; George A. Micromechanical/microelectromechanical identification devices and methods of fabrication and encoding thereof
JP3771287B2 (en) * 1994-04-15 2006-04-26 富士写真フイルム株式会社 Waveguide type electro-optic element
US5491461A (en) * 1994-05-09 1996-02-13 General Motors Corporation Magnetic field sensor on elemental semiconductor substrate with electric field reduction means
US6064783A (en) * 1994-05-25 2000-05-16 Congdon; Philip A. Integrated laser and coupled waveguide
JP2643833B2 (en) * 1994-05-30 1997-08-20 日本電気株式会社 Semiconductor memory device and method of manufacturing the same
US5828080A (en) * 1994-08-17 1998-10-27 Tdk Corporation Oxide thin film, electronic device substrate and electronic device
US5559368A (en) * 1994-08-30 1996-09-24 The Regents Of The University Of California Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation
US5873977A (en) * 1994-09-02 1999-02-23 Sharp Kabushiki Kaisha Dry etching of layer structure oxides
US5635741A (en) * 1994-09-30 1997-06-03 Texas Instruments Incorporated Barium strontium titanate (BST) thin films by erbium donor doping
US5486406A (en) * 1994-11-07 1996-01-23 Motorola Green-emitting organometallic complexes for use in light emitting devices
US5677551A (en) * 1994-11-15 1997-10-14 Fujitsu Limited Semiconductor optical device and an optical processing system that uses such a semiconductor optical system
JP2679653B2 (en) * 1994-12-05 1997-11-19 日本電気株式会社 Semiconductor device
US5635453A (en) * 1994-12-23 1997-06-03 Neocera, Inc. Superconducting thin film system using a garnet substrate
US5772758A (en) * 1994-12-29 1998-06-30 California Institute Of Technology Near real-time extraction of deposition and pre-deposition characteristics from rotating substrates and control of a deposition apparatus in near real-time
JP3557011B2 (en) * 1995-03-30 2004-08-25 株式会社東芝 Semiconductor light emitting device and manufacturing method thereof
US5528209A (en) * 1995-04-27 1996-06-18 Hughes Aircraft Company Monolithic microwave integrated circuit and method
US5606184A (en) * 1995-05-04 1997-02-25 Motorola, Inc. Heterostructure field effect device having refractory ohmic contact directly on channel layer and method for making
KR100193219B1 (en) * 1995-07-06 1999-06-15 박원훈 Passive polarizer
US5753934A (en) * 1995-08-04 1998-05-19 Tok Corporation Multilayer thin film, substrate for electronic device, electronic device, and preparation of multilayer oxide thin film
US5905571A (en) * 1995-08-30 1999-05-18 Sandia Corporation Optical apparatus for forming correlation spectrometers and optical processors
US6022963A (en) * 1995-12-15 2000-02-08 Affymetrix, Inc. Synthesis of oligonucleotide arrays using photocleavable protecting groups
KR100199095B1 (en) * 1995-12-27 1999-06-15 구본준 Capacitor of semiconductor memory device and its fabrication method
US5861966A (en) * 1995-12-27 1999-01-19 Nynex Science & Technology, Inc. Broad band optical fiber telecommunications network
FR2744578B1 (en) * 1996-02-06 1998-04-30 Motorola Semiconducteurs HIGH FREQUENCY AMPLIFIER
JP3435966B2 (en) * 1996-03-13 2003-08-11 株式会社日立製作所 Ferroelectric element and method of manufacturing the same
TW410272B (en) * 1996-05-07 2000-11-01 Thermoscan Lnc Enhanced protective lens cover
SE518132C2 (en) * 1996-06-07 2002-08-27 Ericsson Telefon Ab L M Method and apparatus for synchronizing combined receivers and transmitters in a cellular system
US5729566A (en) * 1996-06-07 1998-03-17 Picolight Incorporated Light emitting device having an electrical contact through a layer containing oxidized material
US5838851A (en) * 1996-06-24 1998-11-17 Trw Inc. Optical-loop signal processing using reflection mechanisms
JP3082671B2 (en) * 1996-06-26 2000-08-28 日本電気株式会社 Transistor element and method of manufacturing the same
US5863326A (en) * 1996-07-03 1999-01-26 Cermet, Inc. Pressurized skull crucible for crystal growth using the Czochralski technique
US5858814A (en) * 1996-07-17 1999-01-12 Lucent Technologies Inc. Hybrid chip and method therefor
IL119006A (en) * 1996-08-04 2001-04-30 B G Negev Technologies And App Tunable delay line optical filters
US6023082A (en) * 1996-08-05 2000-02-08 Lockheed Martin Energy Research Corporation Strain-based control of crystal anisotropy for perovskite oxides on semiconductor-based material
AU3632697A (en) * 1996-08-12 1998-03-06 Energenius, Inc. Semiconductor supercapacitor system, method for making same and articles produced therefrom
JP4114709B2 (en) * 1996-09-05 2008-07-09 株式会社神戸製鋼所 Diamond film formation method
EP0839653A3 (en) * 1996-10-29 1999-06-30 Matsushita Electric Industrial Co., Ltd. Ink jet recording apparatus and its manufacturing method
US5953468A (en) * 1996-11-01 1999-09-14 Mendez R&D Associates Scalable, quantized, delay-line array based on nested, generalized spirals
US5719417A (en) * 1996-11-27 1998-02-17 Advanced Technology Materials, Inc. Ferroelectric integrated circuit structure
JP3414227B2 (en) * 1997-01-24 2003-06-09 セイコーエプソン株式会社 Ink jet recording head
US5937115A (en) * 1997-02-12 1999-08-10 Foster-Miller, Inc. Switchable optical components/structures and methods for the fabrication thereof
US5864543A (en) * 1997-02-24 1999-01-26 At&T Wireless Services, Inc. Transmit/receive compensation in a time division duplex system
US6022671A (en) * 1997-03-11 2000-02-08 Lightwave Microsystems Corporation Method of making optical interconnects with hybrid construction
US5872493A (en) * 1997-03-13 1999-02-16 Nokia Mobile Phones, Ltd. Bulk acoustic wave (BAW) filter having a top portion that includes a protective acoustic mirror
CN1131548C (en) * 1997-04-04 2003-12-17 松下电器产业株式会社 Ohmic electrode forming method and semiconductor device
US5857049A (en) * 1997-05-05 1999-01-05 Lucent Technologies, Inc., Precision alignment of optoelectronic devices
US6103403A (en) * 1997-05-15 2000-08-15 University Of Kentucky Research Foundation Intellectual Property Development Clathrate structure for electronic and electro-optic applications
US5869845A (en) * 1997-06-26 1999-02-09 Texas Instruments Incorporated Resonant tunneling memory
US6013553A (en) * 1997-07-24 2000-01-11 Texas Instruments Incorporated Zirconium and/or hafnium oxynitride gate dielectric
US5940691A (en) * 1997-08-20 1999-08-17 Micron Technology, Inc. Methods of forming SOI insulator layers and methods of forming transistor devices
US6184144B1 (en) * 1997-10-10 2001-02-06 Cornell Research Foundation, Inc. Methods for growing defect-free heteroepitaxial layers
US6181920B1 (en) * 1997-10-20 2001-01-30 Ericsson Inc. Transmitter that selectively polarizes a radio wave
JP4204108B2 (en) * 1997-11-06 2009-01-07 エピフォトニクス株式会社 Optical waveguide device and manufacturing method thereof
US6376337B1 (en) * 1997-11-10 2002-04-23 Nanodynamics, Inc. Epitaxial SiOx barrier/insulation layer
JP3092659B2 (en) * 1997-12-10 2000-09-25 日本電気株式会社 Thin film capacitor and method of manufacturing the same
US6020222A (en) * 1997-12-16 2000-02-01 Advanced Micro Devices, Inc. Silicon oxide insulator (SOI) semiconductor having selectively linked body
US6140696A (en) * 1998-01-27 2000-10-31 Micron Technology, Inc. Vertically mountable semiconductor device and methods
US6278523B1 (en) * 1998-02-13 2001-08-21 Centre National De La Recherche Scientifique-Cnrs Optical sensor on a silicon substrate and application for the in situ measurement of a fluorescent marker in the small bronchia
US6069581A (en) * 1998-02-20 2000-05-30 Amerigon High performance vehicle radar system
US6011646A (en) * 1998-02-20 2000-01-04 The Regents Of The Unviersity Of California Method to adjust multilayer film stress induced deformation of optics
GB2334594A (en) * 1998-02-20 1999-08-25 Fujitsu Telecommunications Eur Arrayed waveguide grating device
US6055179A (en) * 1998-05-19 2000-04-25 Canon Kk Memory device utilizing giant magnetoresistance effect
US6338756B2 (en) * 1998-06-30 2002-01-15 Seh America, Inc. In-situ post epitaxial treatment process
JP3450713B2 (en) * 1998-07-21 2003-09-29 富士通カンタムデバイス株式会社 Semiconductor device, method for manufacturing the same, and method for manufacturing microstrip line
US6103008A (en) * 1998-07-30 2000-08-15 Ut-Battelle, Llc Silicon-integrated thin-film structure for electro-optic applications
US6393167B1 (en) * 1998-07-31 2002-05-21 Monica K. Davis Fast, environmentally-stable fiber switches using a Sagnac interferometer
US6392253B1 (en) * 1998-08-10 2002-05-21 Arjun J. Saxena Semiconductor device with single crystal films grown on arrayed nucleation sites on amorphous and/or non-single crystal surfaces
US6300615B1 (en) * 1998-08-31 2001-10-09 Canon Kabushiki Kaisha Photoelectric conversion apparatus
US6022410A (en) * 1998-09-01 2000-02-08 Motorola, Inc. Alkaline-earth metal silicides on silicon
US6191011B1 (en) * 1998-09-28 2001-02-20 Ag Associates (Israel) Ltd. Selective hemispherical grain silicon deposition
TW399309B (en) * 1998-09-30 2000-07-21 World Wiser Electronics Inc Cavity-down package structure with thermal via
US6343171B1 (en) * 1998-10-09 2002-01-29 Fujitsu Limited Systems based on opto-electronic substrates with electrical and optical interconnections and methods for making
US6232806B1 (en) * 1998-10-21 2001-05-15 International Business Machines Corporation Multiple-mode clock distribution apparatus and method with adaptive skew compensation
JP3408762B2 (en) * 1998-12-03 2003-05-19 シャープ株式会社 Semiconductor device having SOI structure and method of manufacturing the same
FR2786887B1 (en) * 1998-12-08 2001-01-26 Cit Alcatel SEMICONDUCTOR PHASE MODULATOR
US6173474B1 (en) * 1999-01-08 2001-01-16 Fantom Technologies Inc. Construction of a vacuum cleaner head
US6180486B1 (en) * 1999-02-16 2001-01-30 International Business Machines Corporation Process of fabricating planar and densely patterned silicon-on-insulator structure
JP4631103B2 (en) * 1999-05-19 2011-02-16 ソニー株式会社 Semiconductor device and manufacturing method thereof
US6340788B1 (en) * 1999-12-02 2002-01-22 Hughes Electronics Corporation Multijunction photovoltaic cells and panels using a silicon or silicon-germanium active substrate cell for space and terrestrial applications
US6251738B1 (en) * 2000-01-10 2001-06-26 International Business Machines Corporation Process for forming a silicon-germanium base of heterojunction bipolar transistor
US6404027B1 (en) * 2000-02-07 2002-06-11 Agere Systems Guardian Corp. High dielectric constant gate oxides for silicon-based devices
JP2001251283A (en) * 2000-03-06 2001-09-14 Hitachi Ltd Interface circuit
US6348373B1 (en) * 2000-03-29 2002-02-19 Sharp Laboratories Of America, Inc. Method for improving electrical properties of high dielectric constant films
US20020008234A1 (en) * 2000-06-28 2002-01-24 Motorola, Inc. Mixed-signal semiconductor structure, device including the structure, and methods of forming the device and the structure
US6521996B1 (en) * 2000-06-30 2003-02-18 Intel Corporation Ball limiting metallurgy for input/outputs and methods of fabrication
JP2002023123A (en) * 2000-07-11 2002-01-23 Fujitsu Ltd Optical circuit provided with optical waveguide for guiding minor light
US6661940B2 (en) * 2000-07-21 2003-12-09 Finisar Corporation Apparatus and method for rebroadcasting signals in an optical backplane bus system
US6677655B2 (en) * 2000-08-04 2004-01-13 Amberwave Systems Corporation Silicon wafer with embedded optoelectronic material for monolithic OEIC
US6524651B2 (en) * 2001-01-26 2003-02-25 Battelle Memorial Institute Oxidized film structure and method of making epitaxial metal oxide structure
US6528374B2 (en) * 2001-02-05 2003-03-04 International Business Machines Corporation Method for forming dielectric stack without interfacial layer
US6297598B1 (en) * 2001-02-20 2001-10-02 Harvatek Corp. Single-side mounted light emitting diode module
JP4056226B2 (en) * 2001-02-23 2008-03-05 株式会社ルネサステクノロジ Semiconductor device
US6788839B2 (en) * 2001-03-19 2004-09-07 General Instrument Corporation Time slot tunable all-optical packet data routing switch
US6589887B1 (en) * 2001-10-11 2003-07-08 Novellus Systems, Inc. Forming metal-derived layers by simultaneous deposition and evaporation of metal

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6100578A (en) * 1997-08-29 2000-08-08 Sony Corporation Silicon-based functional matrix substrate and optical integrated oxide device
WO2001004943A1 (en) * 1999-07-07 2001-01-18 Matsushita Electric Industrial Co., Ltd. Multilayered body, method for fabricating multilayered body, and semiconductor device
WO2002047127A2 (en) * 2000-12-08 2002-06-13 Motorola, Inc. Pyroelectric device on a monocrystalline semiconductor substrate

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006012298A1 (en) * 2004-06-28 2006-02-02 Nitronex Corporation Gallium nitride material and methods associated with the same
US7339205B2 (en) 2004-06-28 2008-03-04 Nitronex Corporation Gallium nitride materials and methods associated with the same
US7352015B2 (en) 2004-06-28 2008-04-01 Nitronex Corporation Gallium nitride materials and methods associated with the same
US8748298B2 (en) 2004-06-28 2014-06-10 International Rectifier Corporation Gallium nitride materials and methods associated with the same
US10096701B2 (en) 2004-06-28 2018-10-09 Infineon Technologies Americas Corp. Gallium nitride materials and methods associated with the same

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