WO2002057893A3 - Method and apparatus for reducing power consuption in a digital processor - Google Patents

Method and apparatus for reducing power consuption in a digital processor Download PDF

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Publication number
WO2002057893A3
WO2002057893A3 PCT/US2001/051064 US0151064W WO02057893A3 WO 2002057893 A3 WO2002057893 A3 WO 2002057893A3 US 0151064 W US0151064 W US 0151064W WO 02057893 A3 WO02057893 A3 WO 02057893A3
Authority
WO
WIPO (PCT)
Prior art keywords
instruction
pipeline
sleep mode
reducing power
core
Prior art date
Application number
PCT/US2001/051064
Other languages
French (fr)
Other versions
WO2002057893A2 (en
Inventor
Daniel Hansson
Original Assignee
Arc Internat Uk Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Arc Internat Uk Ltd filed Critical Arc Internat Uk Ltd
Priority to AU2002246904A priority Critical patent/AU2002246904A1/en
Publication of WO2002057893A2 publication Critical patent/WO2002057893A2/en
Publication of WO2002057893A3 publication Critical patent/WO2002057893A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30083—Power or thermal control instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3228—Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3243—Power saving in microcontroller unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30156—Special purpose encoding of instructions, e.g. Gray coding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for reducing power consumption within a pipelined processor. In one embodiment, the method of the invention comprises defining an instruction which invokes a 'sleep mode' within the processor and pipeline; inserting the instruction into the pipeline; decoding and executing the instruction, stalling the pipeline in response to the sleep mode instruction; disabling memory in response to the sleep mode instruction; and awaking the core from sleep mode based on the occurence of a predetermined event. Methods for structuring core pipeline logic and extension instructions to reduce core power consumption under various conditions are described. Methods and apparatus for synthesizing logic implementing the aforementioned methodology are also disclosed.
PCT/US2001/051064 2000-10-27 2001-10-25 Method and apparatus for reducing power consuption in a digital processor WO2002057893A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002246904A AU2002246904A1 (en) 2000-10-27 2001-10-25 Method and apparatus for reducing power consuption in a digital processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US24407100P 2000-10-27 2000-10-27
US60/244,071 2000-10-27

Publications (2)

Publication Number Publication Date
WO2002057893A2 WO2002057893A2 (en) 2002-07-25
WO2002057893A3 true WO2002057893A3 (en) 2003-05-30

Family

ID=22921254

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/051064 WO2002057893A2 (en) 2000-10-27 2001-10-25 Method and apparatus for reducing power consuption in a digital processor

Country Status (2)

Country Link
AU (1) AU2002246904A1 (en)
WO (1) WO2002057893A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050085281A (en) * 2002-12-04 2005-08-29 코닌클리즈케 필립스 일렉트로닉스 엔.브이. Software-based control of microprocessor power dissipation
US20060200651A1 (en) * 2005-03-03 2006-09-07 Collopy Thomas K Method and apparatus for power reduction utilizing heterogeneously-multi-pipelined processor
US8595279B2 (en) * 2006-02-27 2013-11-26 Qualcomm Incorporated Floating-point processor with reduced power requirements for selectable subprecision
US20090293072A1 (en) 2006-07-21 2009-11-26 Sony Service Centre (Europe) N.V. System having plurality of hardware blocks and method of operating the same
US8918446B2 (en) 2010-12-14 2014-12-23 Intel Corporation Reducing power consumption in multi-precision floating point multipliers
CN107977227A (en) * 2016-10-21 2018-05-01 超威半导体公司 The pipeline of separate hardware data path including different instruction type

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06332693A (en) * 1993-05-27 1994-12-02 Hitachi Ltd Issuing system of suspending instruction with time-out function
US5485625A (en) * 1992-06-29 1996-01-16 Ford Motor Company Method and apparatus for monitoring external events during a microprocessor's sleep mode
WO1996009583A2 (en) * 1994-09-23 1996-03-28 Cambridge Consultants Limited Data processing circuits and interfaces
US5584031A (en) * 1993-11-09 1996-12-10 Motorola Inc. System and method for executing a low power delay instruction
US5774709A (en) * 1995-12-06 1998-06-30 Lsi Logic Corporation Enhanced branch delay slot handling with single exception program counter
JP2001282548A (en) * 2000-03-29 2001-10-12 Matsushita Electric Ind Co Ltd Communication equipment and communication method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5485625A (en) * 1992-06-29 1996-01-16 Ford Motor Company Method and apparatus for monitoring external events during a microprocessor's sleep mode
JPH06332693A (en) * 1993-05-27 1994-12-02 Hitachi Ltd Issuing system of suspending instruction with time-out function
US5584031A (en) * 1993-11-09 1996-12-10 Motorola Inc. System and method for executing a low power delay instruction
WO1996009583A2 (en) * 1994-09-23 1996-03-28 Cambridge Consultants Limited Data processing circuits and interfaces
US5774709A (en) * 1995-12-06 1998-06-30 Lsi Logic Corporation Enhanced branch delay slot handling with single exception program counter
JP2001282548A (en) * 2000-03-29 2001-10-12 Matsushita Electric Ind Co Ltd Communication equipment and communication method

Also Published As

Publication number Publication date
AU2002246904A1 (en) 2002-07-30
WO2002057893A2 (en) 2002-07-25

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