WO2002043463A3 - Systems and methods for generating hardware description code - Google Patents

Systems and methods for generating hardware description code Download PDF

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Publication number
WO2002043463A3
WO2002043463A3 PCT/US2001/017397 US0117397W WO0243463A3 WO 2002043463 A3 WO2002043463 A3 WO 2002043463A3 US 0117397 W US0117397 W US 0117397W WO 0243463 A3 WO0243463 A3 WO 0243463A3
Authority
WO
WIPO (PCT)
Prior art keywords
hardware description
description code
methods
systems
files
Prior art date
Application number
PCT/US2001/017397
Other languages
French (fr)
Other versions
WO2002043463A2 (en
Inventor
Spencer Hao Tiong
Alvin Swee Hock Lim
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to EP01939663A priority Critical patent/EP1364318A2/en
Priority to AU2001265156A priority patent/AU2001265156A1/en
Priority to KR10-2003-7007119A priority patent/KR20030066684A/en
Priority to JP2002545454A priority patent/JP2004514995A/en
Publication of WO2002043463A2 publication Critical patent/WO2002043463A2/en
Publication of WO2002043463A3 publication Critical patent/WO2002043463A3/en

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G01R31/318357—Simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318364—Generation of test inputs, e.g. test vectors, patterns or sequences as a result of hardware simulation, e.g. in an HDL environment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G01R31/318591—Tools
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/02—CAD in a network environment, e.g. collaborative CAD or distributed simulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99941—Database schema or data structure
    • Y10S707/99942—Manipulating data structure, e.g. compression, compaction, compilation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99941—Database schema or data structure
    • Y10S707/99943—Generating database or data structure, e.g. via user interface
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99941—Database schema or data structure
    • Y10S707/99944—Object-oriented database structure
    • Y10S707/99945—Object-oriented database structure processing

Abstract

An Internet hardware description code generation system, methods, and scripts are provided. The Internet hardware description code generation system (185) includes a hardware description code generation host (200) adapted to generate one or more hardware description language files (220) in response to one or more input parameters (210). A user upload input parameters corresponding to a circuit to the hardware description code host (200). In response, the host generates one or more hardware description language (HDL) files (220) that describe the circuit. Cgi scripts may be used to generate the HDL files (220).
PCT/US2001/017397 2000-11-28 2001-05-29 Systems and methods for generating hardware description code WO2002043463A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP01939663A EP1364318A2 (en) 2000-11-28 2001-05-29 Systems and methods for generating hardware description code
AU2001265156A AU2001265156A1 (en) 2000-11-28 2001-05-29 Systems and methods for generating hardware description code
KR10-2003-7007119A KR20030066684A (en) 2000-11-28 2001-05-29 Systems and methods for generating hardware description code
JP2002545454A JP2004514995A (en) 2000-11-28 2001-05-29 System and method for generating hardware description code

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/724,134 US6539520B1 (en) 2000-11-28 2000-11-28 Systems and methods for generating hardware description code
US09/724,134 2000-11-28

Publications (2)

Publication Number Publication Date
WO2002043463A2 WO2002043463A2 (en) 2002-06-06
WO2002043463A3 true WO2002043463A3 (en) 2003-07-24

Family

ID=24909155

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/017397 WO2002043463A2 (en) 2000-11-28 2001-05-29 Systems and methods for generating hardware description code

Country Status (8)

Country Link
US (1) US6539520B1 (en)
EP (1) EP1364318A2 (en)
JP (1) JP2004514995A (en)
KR (1) KR20030066684A (en)
CN (1) CN1484799A (en)
AU (1) AU2001265156A1 (en)
TW (1) TW552555B (en)
WO (1) WO2002043463A2 (en)

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US6973631B2 (en) * 2002-07-18 2005-12-06 Incentia Design Systems Corp. Scan insertion with bypass login in an IC design
JP4426166B2 (en) * 2002-11-01 2010-03-03 ユー・エム・シー・ジャパン株式会社 Semiconductor device design method, semiconductor device design program, and semiconductor device
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JP5229834B2 (en) * 2008-09-30 2013-07-03 株式会社アドバンテスト Circuit design method, circuit design system, and recording medium
US20100175038A1 (en) * 2009-01-06 2010-07-08 Internationl Buisness Machines Corporation Techniques for Implementing an Engineering Change Order in an Integrated Circuit Design
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Also Published As

Publication number Publication date
EP1364318A2 (en) 2003-11-26
KR20030066684A (en) 2003-08-09
WO2002043463A2 (en) 2002-06-06
JP2004514995A (en) 2004-05-20
AU2001265156A1 (en) 2002-06-11
US6539520B1 (en) 2003-03-25
CN1484799A (en) 2004-03-24
TW552555B (en) 2003-09-11

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