WO2002025740A1

WO2002025740A1 - High-voltage diode and method for the production thereof

Info

Publication number: WO2002025740A1
Application number: PCT/DE2001/003240
Authority: WO
Inventors: Reiner Barthelmess; Frank Pfirsch; Anton Mauder; Gerhard Schmidt
Original assignee: eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG; Infineon Technologies Ag
Priority date: 2000-09-22
Filing date: 2001-08-24
Publication date: 2002-03-28
Also published as: US20030183900A1; DE50107925D1; EP1307923B1; DE10047152B4; EP1307923A1; DE10047152A1; JP2004510333A; US6770917B2

Abstract

The invention relates to a high-voltage diode and to a method for the production thereof. According to the invention, only three masking steps are required due to the use of adjustment structures (6) and of a chipping stopper with an edge passivation (12) comprised of a-C:H or a-Si.

Description

description

High-voltage diode and process for its manufacture

The present invention relates to a high-voltage diode according to the. The preamble of claim 1 and a method for producing such a high-voltage diode.

Up to now, high-voltage diodes, which are intended for higher voltages, in particular above approximately 400 V, have been provided with edge terminations from field plates, field rings, dielectric insulating layers, semi-insulating covers and varying doping in the edge region when using planar structures. These measures are used individually or in combination, although for example also

Field plates, field rings and dielectric insulation layers are used together.

It has been shown that in the manufacture of the diode, even more steps are required for an edge termination that meets the requirements placed on it than for setting the desired pass-through and switching properties. For example, diode edges based on field plates require relatively complex manufacturing processes.

In detail, in C. Mingues and G. Charitat: "Efficiency of Junction Termination Techniques vs. Oxide Trapped Charges", 1997, IEEE International Symposium on Power Semiconductor Devices and ICs, Weimar, pages 137 to 140, edge seals with field rings, semi-insulating layers or a JTE (Junction Termination Extension) especially compared with regard to their sensitivity to oxide charges. For high-voltage applications, the use of SIPOS techniques is recommended as semi-insulating layers.

EP-B1-0 341 453 discloses a MOS semiconductor component for high reverse voltage, in which field plates are arranged on insulating layers of different thicknesses. Some of these field plates serve as channel or channel stoppers. Such field plates used as channel stoppers in diodes are often connected to the backside potential of the diode by a p-conducting region in the edge region, although a connection via an n-conducting region would in itself be more advantageous because this could reliably prevent a p-conducting channel , However, an additional mask step would be required for such a connection via an n-conducting region in an otherwise customary production process.

So-called chipping stoppers are intended to prevent crystal defects from spreading from the saw edge into the active area of the respective chips when sawing a disk into individual chips. These chipping stoppers are usually realized by a field oxide between the functional edge area of the chip and the saw frame.

If highly blocking pn junctions are only covered with dielectric passivation layers, changes in the long-term blocking stability can be observed when the external pn junction is exposed to the effects of moisture, alkaline or metallic contamination, etc. when the pn junction is blocked , These changes are caused by drift of ion charges in the electric field of the reverse pn junction on or in the passivation layer. Depending on the sign of the ion charges and also on the structure of the edge termination, ie depending on the so-called edge contour, the ion charges can lead to an increase or a decrease in the blocking capacity of the pn junction.

In the case of a diode with a p-conducting anode, the influence of such surface charges in and on the passivation layer increases with decreasing doping in the n-conducting base and therefore with increasing volume blocking capacity of the diode, which leads to a dramatic

Increases the risk of blocking instabilities. In this context, reference should be made to the so-called Yoshida effect: when using insulator layers for passivation a drift in the reverse voltage is occasionally observed as a result of an injection of hot electrons during the forward load when switching to the blocking state of the pn junction.

By using semi-insulating layers directly on the pn junctions, the influence of such surface charges can be suppressed with suitable settings of the layer and interface parameters, such as, for example, the layer thickness and doping of the insulating layers. The semi-insulating layers that are currently used for the passivation of pn junctions consist, for example, of amorphous silicon (a-Si) or of hydrogen-doped amorphous carbon (aC: H), as described in EP-Bl-0 400 178 and EP-Bl-0 381 111. With these semi-insulating layers, with appropriate optimization of the amorphous crystalline heterojunctions between these layers and the electrically active silicon substrate, parasitic effects, such as an increased reverse current or the formation of inversion layers, can be avoided. In addition, due to their finite density of states, semi-insulating passivation layers can actively build up image charges and thus shield external charges that penetrate from the outside, as well as dissipating them into specified charge carriers due to their finite specific conductivity. Overall, a semi-insulating passivation leads to a significantly improved long-term stability compared to a dielectric passivation.

It is an object of the present invention to provide a high-voltage diode for reverse voltages, in particular above approximately 400 V and preferably above approximately 500 V, which can be produced with the least possible process complexity and thus a small number of photographic techniques and is readily available in the edge area with a channel stopper Avoidance of leakage currents and a chipping stopper to limit the expansion of saw defects; in addition, a method for producing such a high-voltage diode is to be created. This object is achieved in a high-voltage diode according to the preamble of claim 1 according to the invention by the features contained in the characterizing part.

An advantageous method for producing the high-voltage diode according to the invention is specified in claim 12.

Advantageous developments of the invention result from the subclaims.

The measures (a) and (b) specified in the characterizing part of claim 1 each serve individually to enable a high-voltage diode that can be produced with little effort for masks and adjustment and via a channel stopper, chipping stopper etc. has. Measures (a) and (b) can advantageously be used together. Of course, it is also possible to create a high-voltage diode that only implements one of these measures.

The high-voltage diode according to the invention can be a fast switching diode or else a rectifier and universal diode in different voltage and current classes. The high-voltage diode can have one or more field rings depending on the desired voltage class in its edge area.

In the high-voltage diode according to the invention, the semiconductor body preferably consists of n-type silicon, into which a p-type trough-shaped zone is introduced.

Instead of an n-type silicon body, a p-type silicon body with an n-type trough-shaped zone can also be provided.

The semiconductor material is not limited to silicon. Instead of silicon, it is also possible, for example, to use SiC or an A _I ι _I B _v semiconductor material. The invention is explained in more detail below with reference to drawings in which FIGS. 1 to 5 show different steps for producing the high-voltage diode according to the invention.

1 shows an n-type silicon substrate 1, to which an approximately 0.5 μm thick silicon dioxide layer 2 is applied to the front, for example in a furnace process with moist oxidation. Instead of silicon dioxide, another material, for example silicon nitride, can optionally be selected for this layer 2.

Structures for the anode of the diode and possibly in the edge region for field rings are then introduced into the silicon dioxide layer 2 by means of photolithography. For this purpose, a photoresist layer is applied to the silicon dioxide layer 2, exposed and developed. In this development, the areas of the photoresist layer in which the anode and possibly field rings are to be produced are removed. An etchant, for example during wet chemical etching, is brought into action on the silicon dioxide layer 2 exposed in this way in order to remove the silicon dioxide layer in the areas mentioned.

This is then followed by a further etching step in which a silicon removal of, for example, 10 ... 1000 n, preferably 50 ... 200 nm, in the exposed surface of the silicon substrate 1, that is to say in the areas of the "introduced into the silicon dioxide layer 2" Window "is made. This silicon removal can be carried out via the still existing photoresist or via the silicon dioxide layer 2 remaining after removal of the photoresist. The arrangement shown in FIG. 2 is thus obtained, which on the silicon substrate 1 contains the remaining parts of the silicon dioxide layer 2 and in windows 3 to 5 for an anode (window 3)

Field ring (window 4) and adjustment structures shows that are defined in a scratch frame on the edge of the respective semiconductor chip (right edge in Fig. 2) (window 5). Instead of one Field ring can also be provided several field rings. If necessary, the field rings can also be dispensed with. The adjustment is made on the remaining edges or steps 6 of the window 5 that form adjustment structures.

During the etching of the silicon substrate 1 in the windows 3 to 5, the silicon dioxide layer can be further etched back wet-chemically via the lacquer mask still present, in order to provide a certain distance 7 between the p-dopings to be introduced later in the windows 3 to 5 and the edges 6 of the adjustment structures or to generate the stage formed by this in the silicon substrate 1. The remaining photoresist is removed at the latest after this possible etching back. The arrangement shown in FIG. 2 (without additional etching back of the silicon substrate) or in FIG. 3 (with additional etching back of the silicon substrate) is thus present.

It should also be noted that in the present exemplary embodiment, silicon is removed in windows 3 to 5. At least this removal takes place in the window 3 in order to produce an edge or step as an adjustment structure in the area of a trough 8 outside an anode contact 13 (cf. below).

The arrangement shown in FIG. 2 can thus be generated in such a way that the silicon removal in windows 3 to 5 takes place via the remaining silicon dioxide layer 2 (oxide mask) or via the photoresist still present on this silicon dioxide layer 2.

In the following it is assumed that the arrangement of

Fig. 3 is processed. However, it is also possible to process the arrangement from FIG. 2 in a corresponding manner. In this case, however, there is no distance 7 between the edge of the remaining silicon dioxide layer 2 and the edges 6 of the juicing structures. Rather, these edges 6 of the adjustment structures then directly adjoin the edge of the windows 3 to 5. This is followed by p-doping, for example with boron, in order to produce a p-type trough-shaped zone 8, a p-type field ring 9 and, in the region of the chipping stopper, a p-type ring 10, as shown in FIG. 4 are. The trough-shaped zone 8 as well as the field ring 9 and the ring 10 can be produced, for example, in one stage by means of ion implantation or else in multiple stages. It is thus possible, particularly for fast-switching diodes for zone 8, to provide them with a p ⁺ -conducting anode emitter of low penetration depth, the dopant dose of which is between 1.3 x 10 ¹² dopant atoms cm " ² and 5 x 10 ¹³ dopant atoms cm ^"2 , and to dope the rest of zone 8 with a dose of about (1.3 ... 3) x 10 ¹² dopant atoms cm ^{" 2} (see also DE-Al-100 31 461) ,

There are now different variants for the further processing of the arrangement shown in FIG. 4, in which necessary process steps, such as the introduction of an n-doping (for example phosphorus) on the rear side of the semiconductor substrate 1, that is to say the rear side of the wafer, serve as the rear side emitter Formation of an n ⁺ -conducting silicon layer 11, for example by ion implantation, the etching off of the remaining silicon dioxide layer 2 (sacrificial oxide) on the front of the pane, the application and structuring of an edge passivation layer 12 with a chipping stopper 12a each made of amorphous carbon (aC.) Doped in particular with hydrogen .H) using a lithography step, the deposition and the structuring of a front side metallization from, for example, AlSi to form an anode contact 13 and a channel stopper 14, and the deposition of a rear side metallization from, for example, AlSi to form a cathode contact 15, and optionally tative process steps, such as the thin grinding or etching of the silicon substrate 1 from the rear to final thickness, the introduction of an n-type doping as a field stop layer 16 on the rear of the pane and diffusion of this n-type doping, the introduction of heavy metal atoms for charge carrier lifetime adjustment, heavy metal diffusion, radiation to charge carrier lifetime setting, annealing the front side metallization and annealing the back metal pre ^¬ be taken. In these process steps, the edges 6 are used as adjustment structures, if necessary. It is even possible to carry out the p-type doping for the zone 8, the field ring 9 and the ring 10, that is to say the introduction of the front side p-contact or the p-type emitter with ion implantation at a later point in time.

These individual process variants are summarized in the following table. Process variant 1 is particularly suitable for base material consisting of silicon substrate wafers obtained by zone drawing (FZ), while process variants 2 and 3 are also suitable for Czochralski (CZ) substrate wafers or for those with epitaxial layers ") Wafers are beneficial.

The edge passivation layer 12 (and thus the chipping stopper 12a) can optionally also consist of amorphous silicon (a-Si).

In the case of the various process variants above, the process step "radiation, if necessary, for setting the charge carrier life" is carried out several times, since depending on the dose used, ion buds and the type of radiation require different temperature budgets to heal radiation damage.

The edge passivation layer 12, which consists in particular of hydrogen-doped amorphous carbon, partially acts as a chipping stopper 12a and prevents crystal defects from spreading out of a scribe frame into an active area when a silicon wafer is separated or sawn into chips. In the scratching frame itself, the passivation layer 12 is opened analogously to the contact holes for the anode contact 13 and the channel stopper 14, but there is no covering with metal here. The channel stopper 14 acts as a field plate and prevents the further spreading of a space charge zone outwards into the scoring frame. This makes it possible to reduce the necessary edge width, especially in the case of a high-resistance base material for the silicon substrate 1.

The channel stopper 14 can also be connected to a p-type region, as indicated by a dashed line 17 in FIG. 5. This p-conducting region should then have the same electrical potential as the back of the silicon substrate, that is to say it should be connected to the cathode contact 15.

However, it is particularly advantageous if the channel stopper 14 is connected directly to an n-conducting region, as shown in FIG. 5.

In addition to the field ring 9, further field rings 9 can optionally be provided between the active area, that is to say the trough-shaped zone 8, and a sawing edge 18, and these may also be provided with all or part of metal structures. The field ring 9 can also have such a metal structure.

The high-voltage diode according to the invention can be thanks to the adjustment structures 6, which are located outside the anode contact 13, and the execution of the chipping stopper 12a in the edge region by the passivation layer 12 using only a total of three masking steps for the generation of the structured silicon dioxide layer 2, the Produce the passivation layer 12 and the front-side metallization from the anode contact 13 and the channel stopper 14. In this case, the adjustment structure 6 can advantageously be used, which allows precise positioning of the anode contact 13 and the channel stopper 14, for example. LIST OF REFERENCE NUMBERS

1 silicon substrate 2 silicon dioxide layer

3 windows for tub

4 windows for field ring

5 windows for chipping stopper ring

6 edge 7 distance

8 trough-shaped zone

9 field ring

10 chipping stopper ring

11 n ⁺ conductive silicon layer 12 passivation layer

12a chipping stopper

13 anode contact

14 channel stopper

15 cathode contact 16 field stop layer

17 dashed line for p-type region

18 saw edge

Claims

claims

1. High-voltage diode with:

a trough-shaped zone (8) of one conduction type, which is provided in a first main surface of a semiconductor body (1) of the other, on the one conduction type of opposite conduction type,

a metal contact (13) provided on the trough-shaped zone (8),

a rear side metallization (15) opposite the metal contact (13) on a second main surface of the semiconductor body (1) opposite the first main surface,

- An edge termination with a channel stopper (14) and

- A passivation layer (12) on the first main surface in the area between the metal contact (13) and the

Channel stopper (14) is provided and covers the pn junction occurring on the first main surface, characterized in that

- The passivation layer (12) consists of amorphous, hydrogen-doped carbon or amorphous silicon and in the area of the semiconductor body (1) outside the channel stopper (14) serves as a chipping stopper (12a) and

- At least one edge (6) is provided as an adjustment structure in the first main surface in the region of the trough-shaped zone (8).

2. High-voltage diode according to claim 1, characterized in that the edge termination has one or more field rings (9).

3. High-voltage diode of claims 1 or 2, characterized in that the channel stopper (14) is provided on the semiconductor body (1).

4. High-voltage diode according to one of claims 1 to 3, characterized in that the channel stopper (14) is provided in an area of one line type.

5. High-voltage diode according to one of claims 1 to 4, characterized in that between the semiconductor body (1) and a cathode metallization (15) a field stop layer (16) of the other line type and a highly doped emitter layer (11) other line types are provided.

6. High-voltage diode according to one of claims 1 to 5, characterized in that the adjustment structures (6) made of silicon steps in the first main surface with a height of about 10 ... 1000 nm, preferably 50 ... 200 nm exist.

7. High-voltage diode according to one of claims 1 to 6, characterized in that the adjustment structures (6) are located outside the anode contact (13).

8. High-voltage diode according to one of claims 1 to 7, characterized in that the passivation layer (12) does not extend to the saw edge (18) of the semiconductor body.

9. High-voltage diode according to one of claims 1 to 8, dadur ch gekennz ei chnet that in the region of the sawing edge (18) an annular zone (10) of one line type can be exposed on the first main surface.

10. High-voltage diode according to one of claims 1 to 9, characterized in that the trough-shaped zone (8) of one conduction type with a dose of (1.3 ... 3) x 10 ¹² dopant atoms cm ^"2 is doped to operate the high-voltage diode as a fast freewheeling diode.

11. High-voltage diode according to claim 10, characterized in that a surface area of the trough-shaped zone (8) is doped with a dose between 1.3 x 10 ¹² dopant atoms cm ^"2 and 5 x 10 ¹³ dopant atoms cm" ² is.

12. A method for producing the high-voltage diode according to one of claims 1 to 11, characterized by the following method steps:

(a) producing a mask insulating layer (2) on a semiconductor body (1),

(b) structuring the mask insulation layer (2) to produce at least one window (3, 4, 5) for a trough-shaped zone (8),

(c) generating steps as adjustment structures (6) in the silicon body (1) through the windows (3, 4, 5),

(d) creating the trough-shaped zone (8) through the window (3), each with a conduction type opposite to the conduction type of the semiconductor body (1),

(e) removing the structured mask insulation layer (2),

(f) applying and structuring a passivation layer (12) made of amorphous, hydrogen-doped by means of a lithography step, adjusted with the adjustment structures (6)

Carbon or amorphous silicon,

(g) applying and structuring a metal contact (13) and a channel stopper (14) in windows of the structured passivation layer (12) on a front side of the trough-shaped zone (8) or the semiconductor body (1) and

(h) applying a metallization (15) to the back of the semiconductor body (1).

13. The method according to claim 12, characterized in that structuring for a field ring (9) and a chipping stopper ring (10) is carried out in method step (b).

14. The method according to claim 12 or 13, characterized in that at least one of the following method steps is carried out before or after method step (d): (i) thin grinding and / or etching of the semiconductor body (1) to final thickness,

(j) introducing a doping of the other conductivity type as a field stop layer (16) on the back of the semiconductor body

(1) and outdiffusion of this doping, (k) introducing an n-type doping on the back of the semiconductor body (1) as a backside emitter (11), in particular by ion implantation,

(1) introduction of heavy metal atoms for charge carrier lifetime adjustment and (m) diffusion of the heavy metal atoms.

15. The method according to claims 12 and 14, characterized in that one of the method steps (1) and (m) is carried out before or after the method step (d).

16. The method according to claims 12 and 14, characterized in that process steps (i) to (k) are carried out according to process steps (1) and (m).

17. The method according to any one of claims 12 to 16, characterized in that the following method step is carried out after method step (e) and before method step ():

(n) Irradiation of the semiconductor body (1) and / or zones (8) and rings (9, 10) contained therein for setting the charge carrier lifetime.

18. The method according to any one of claims 12 to 17, characterized in that after step (f) and before step (g), the following step is carried out:

(o) Irradiation of the semiconductor body (1) and / or the zones (8) and rings (9, 10) contained therein for setting the charge carrier lifetime.

19. The method according to any one of claims 12 to 18, characterized in that after process step (g) at least one of the following process steps is carried out:

(p) annealing the front side metallization from the metal contact (13) and the channel stopper (14) and

(q) Irradiation of the semiconductor body (1) and the zones (8) and rings (9, 10) contained therein for setting the charge carrier lifetime.

20. The method according to any one of claims 12 to 19, characterized in that the method steps (i) and (k) after the method step

(q) be carried out.

21. Method according to one of claims 12 to 20, so that after the method step (h) the following method step is carried out: (r) annealing the metallization (15) on the back of the semiconductor body.

22. The method according to any one of claims 12 to 21, characterized in that the mask insulating layer (2) is carried out in a furnace process with moist oxidation to a layer thickness of about 0.5 microns.

23. The method according to any one of claims 12 to 22, characterized in that the adjustment structures (6) through to a depth of 10 ... 1000 nm, preferably 50 ... 200 nm in the semiconductor body (1) Etching can be introduced.

24. The method according to claim 23, so that an isotropic etching is carried out for the etching.

25. The method according to any one of claims 12 to 24, characterized in that the adjustment structures (6) are provided with a distance (7) from the windows (3, 4, 5).

26. The method according to any one of claims 12 to 25, characterized in that only three photo-technology steps are carried out to produce the high-voltage diode.