WO2002014886A3 - Method to descramble the data mapping in memory circuits - Google Patents

Method to descramble the data mapping in memory circuits Download PDF

Info

Publication number
WO2002014886A3
WO2002014886A3 PCT/US2001/023168 US0123168W WO0214886A3 WO 2002014886 A3 WO2002014886 A3 WO 2002014886A3 US 0123168 W US0123168 W US 0123168W WO 0214886 A3 WO0214886 A3 WO 0214886A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory circuits
descramble
data mapping
pattern
automatic
Prior art date
Application number
PCT/US2001/023168
Other languages
French (fr)
Other versions
WO2002014886A2 (en
Inventor
Gunther Lehmann
Gerd Frankowsky
Louis Hsu
Armin Reith
Original Assignee
Infineon Technologies Corp
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/675,953 external-priority patent/US6601205B1/en
Application filed by Infineon Technologies Corp, Ibm filed Critical Infineon Technologies Corp
Priority to KR10-2003-7002110A priority Critical patent/KR20030024862A/en
Priority to EP01959122A priority patent/EP1309877A2/en
Publication of WO2002014886A2 publication Critical patent/WO2002014886A2/en
Publication of WO2002014886A3 publication Critical patent/WO2002014886A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Abstract

An automatic method for the generation of a logical hardware test pattern in memory circuits is based on a given physical pattern. The method includes the backwards transformation from a given set of logical data pattern. Since the method is automatic, no knowledge of the data scrambling inside the memory circuit is required.
PCT/US2001/023168 2000-08-15 2001-07-23 Method to descramble the data mapping in memory circuits WO2002014886A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR10-2003-7002110A KR20030024862A (en) 2000-08-15 2001-07-23 Method to descramble the data mapping in memory circuits
EP01959122A EP1309877A2 (en) 2000-08-15 2001-07-23 Method to descramble the data mapping in memory circuits

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US22542500P 2000-08-15 2000-08-15
US60/225,425 2000-08-15
US09/675,953 US6601205B1 (en) 2000-09-29 2000-09-29 Method to descramble the data mapping in memory circuits
US09/675,953 2000-09-29

Publications (2)

Publication Number Publication Date
WO2002014886A2 WO2002014886A2 (en) 2002-02-21
WO2002014886A3 true WO2002014886A3 (en) 2002-07-11

Family

ID=26919582

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/023168 WO2002014886A2 (en) 2000-08-15 2001-07-23 Method to descramble the data mapping in memory circuits

Country Status (4)

Country Link
EP (1) EP1309877A2 (en)
KR (1) KR20030024862A (en)
TW (1) TW556202B (en)
WO (1) WO2002014886A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100836739B1 (en) * 2006-12-02 2008-06-10 한국전자통신연구원 Apparatus and method for mapping logical-physical connection of robot device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5720031A (en) * 1995-12-04 1998-02-17 Micron Technology, Inc. Method and apparatus for testing memory devices and displaying results of such tests
US5841785A (en) * 1995-07-12 1998-11-24 Advantest Corporation Memory testing apparatus for testing a memory having a plurality of memory cell arrays arranged therein
WO2000040986A1 (en) * 1999-01-08 2000-07-13 Teradyne, Inc. Pattern generator for a packet-based memory tester

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841785A (en) * 1995-07-12 1998-11-24 Advantest Corporation Memory testing apparatus for testing a memory having a plurality of memory cell arrays arranged therein
US5720031A (en) * 1995-12-04 1998-02-17 Micron Technology, Inc. Method and apparatus for testing memory devices and displaying results of such tests
WO2000040986A1 (en) * 1999-01-08 2000-07-13 Teradyne, Inc. Pattern generator for a packet-based memory tester

Also Published As

Publication number Publication date
EP1309877A2 (en) 2003-05-14
KR20030024862A (en) 2003-03-26
WO2002014886A2 (en) 2002-02-21
TW556202B (en) 2003-10-01

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