WO2001093327A1 - Semiconductor component, electrically conductive structure therefor, and process for production thereof - Google Patents

Semiconductor component, electrically conductive structure therefor, and process for production thereof Download PDF

Info

Publication number
WO2001093327A1
WO2001093327A1 PCT/IB2001/000891 IB0100891W WO0193327A1 WO 2001093327 A1 WO2001093327 A1 WO 2001093327A1 IB 0100891 W IB0100891 W IB 0100891W WO 0193327 A1 WO0193327 A1 WO 0193327A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrically conductive
semiconductor component
semiconductor
conductive structure
layers
Prior art date
Application number
PCT/IB2001/000891
Other languages
French (fr)
Inventor
Norbert Ammann
Joerg Baumbach
Original Assignee
Tyco Electronics Amp Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tyco Electronics Amp Gmbh filed Critical Tyco Electronics Amp Gmbh
Priority to DE10196279T priority Critical patent/DE10196279T1/en
Priority to AU62566/01A priority patent/AU6256601A/en
Publication of WO2001093327A1 publication Critical patent/WO2001093327A1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/183Connection portion, e.g. seal
    • H01L2924/18301Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Definitions

  • An object of the invention is therefore to reduce the size of semiconductor components and/or systems containing semiconductor components. This and other objects are achieved according to the invention by the semiconductor components and the processes for production thereof wherein the points of contact are a constituent of an electrically conductive structure embedded in the semiconductor component housing and terminating externally flush therewith.
  • the substrate 1 consists, in the example considered, of metal, for example of copper, aluminum or steel, and is 200 ⁇ m to 300 ⁇ m thick.
  • a layer of electrically conductive material is initially applied to this substrate 1. After its production, this layer forms the electrically conductive structure 3, and a base 4, on which the semiconductor chip, which is later to be accommodated in the semiconductor component 5, is placed and fixed.
  • the production of the layer begins in that the substrate 1 is coated on its upper side with a photosensitive material 2. How the coating is applied, i.e. whether a liquid material is applied, or whether a film coated with the material is laminated onto the substrate 1, or whether the material is applied to the substrate 1 in another way, is unimportant in the example considered.
  • the layer of material is approximately 6 ⁇ m thick in the example considered.
  • the substrate 1 coated with the material 2 is illustrated in Fig. IB.
  • the photosensitive material 2 is then exposed and developed in such a way that it is removed at the points at which the substrate 1 is to be provided with the electrically conductive layer.
  • development is carried out using an agent which causes the photosensitive material 2 remaining on the substrate 1 to have a ramp-like course at the transition between the points at which the photosensitive material 2 remains on the substrate 1 and the points at which the photosensitive material 2 has been removed from the substrate 1.
  • agents are agents which cause the photosensitive material 2 remaining on the substrate 1 to shrink upon drying after treatment with the agent.
  • the substrate 1 with the photosensitive material 2 structured as described is illustrated in Fig. lC.
  • the substrate 1 is then in the state illustrated in Fig. ID. Afterwards the photosensitive material 2 still on the substrate 1 is removed. The substrate 1 is then in the state illustrated in Fig. IE.
  • electrical connections to the semiconductor chip 5 are formed by wire bonding to the electrically conductive structure 3.
  • the bonding wires are denoted by the reference numeral 7 in the figures. See Fig. IF.
  • Fig. 1H is the finished semiconductor component.
  • the parts of the electrically conductive structure 3 and of the base 4 originally resting thereon are exposed.
  • the electrically conductive structure 3 and the base 4 terminate flush with the semiconductor component housings formed by the casting compound 8.
  • the parts of the electrically conductive structure 3, now exposed, can be used as points of contact.
  • the exposed part of the base 4 can also serve as a cooling face by means of which the heat produced in the semiconductor chip 5 and conveyed by the base 4 can be released to the outside.
  • Fig. 2H shows the adhesive 6, by means of dashed lines. This indicates that the adhesive 6 can also still be removed.
  • the second electrically conductive layer is subsequently applied to the dielectric 9.
  • This layer is preferably applied by sputtering.
  • the material used for coating which in the example considered is again nickel, is applied to the upper side of the dielectric layer in such a way that the second electrically conductive layer produced as a result also has the desired structure.
  • the nickel furthermore reaches the channels formed by the previous exposure and development of the dielectric layer for connecting the second electric layer to the first electrically conductive layer and deposits itself therein (predominantly on the side walls thereof) in such a way that an electric connection between the first electrically conductive layer and the second electrically conductive layer is formed as a result.
  • a second electrically conductive layer is formed on the dielectric layer and connected to selected parts of the first electrically conductive layer located beneath the dielectric layer.
  • the resulting assembly is illustrated in Fig. 30.
  • a dielectric layer is initially again applied to the assembly shown in Fig. 30 and structured as desired. This is done in the manner described above with reference to Fig. 3B.
  • the channels via which the electrically conductive layer located beneath the further dielectric layer is connected to the electrically conductive layer therebelow are also filled with a dielectric.
  • substantially only the side walls of these channels are covered by an electrically conductive layer.
  • a further electrically conductive layer having a desired structure is applied thereto. This is done in the manner described above with reference to Fig. 30. Because of frequent repetition of the processes described with reference to Fig. 3B and 30 an electrically conductive structure with any number of superimposed electrically conductive layers can be produced.
  • an electrically conductive structure can be applied to the dielectric layer in a single operation for a large number of semiconductor components
  • the electrically conductive layer can also be thicker or thinner than in the examples considered.
  • the thickness of the electrically conductive layer is preferably in the range between 1 ⁇ m and 10 ⁇ m. Good results can also be achieved, however, if the electrically conductive layer is up to 15 ⁇ m or up to 20 ⁇ m thick.
  • the described semiconductor components, the described electrically conductive structures for semiconductor components and the described processes for production thereof make possible a reduction in size and a very simple and rapid production of semiconductor components and systems containing semiconductor components, irrespective of particulars regarding the practical realization.
  • the electrically conductive structures to be provided in the semiconductor component for producing the points of contact and/or connections between the semiconductor chip, the points of contact, and/or further components contained in the semiconductor component are formed by thin layers of electrically conductive material, the height of the semiconductor component can be reduced.
  • the production of electrically conductive structures by using thin electrically conductive layers even permits multilayered electrically conductive structures to be accommodated in the smallest of spaces. Because of the multilayered electrically conductive structures, complex connections between the semiconductor chip, the points of contact of the semiconductor component and/or further components which are provided in the semiconductor component can also be made within the semiconductor component and/or connections which are normally made outside of the semiconductor component can be moved into the semiconductor component. As a result, even complex multi-chip semiconductor components can be produced which are smaller and, at the same time, more powerful than hitherto.

Abstract

The described semiconductor component has an electrically conductive structure for producing points of contact for connection of the semiconductor component to other devices, and connections between components provided in the semiconductor component to one another and/or to the points of contact is formed by a very thin electrically conductive layer or layers. The electrically conductive structure is produced on a temporary substrate which is removed after integration of the electrically conductive structure into the semiconductor component. The semiconductor component furthermore has a particular positioning of the components contained therein, which permits complete or partial omission of cooling of the semiconductor component. Such semiconductor components or such systems containing semiconductor components are very small but can still be produced quickly and simply.

Description

SEMICONDUCTOR COMPONENT, ELECTRICALLY CONDUCTIVE STRUCTURE THEREFOR, AND PROCESS FOR PRODUCTION THEREOF
The present invention relates to semiconductor devices and more particularly to packaging such devices .
Semiconductor components, including microprocessors, microcontrollers, or memory chips, and processes for producing the semiconductor components are known. One example is shown in US patent 5,656,550.
For almost as long as semiconductor components have been in existence, attempts have been made to make them smaller. Development in this field can, however, scarcely keep up with growing demands for size reduction. It would be desirable for portable appliances, such as mobile phones and laptop computers, if the semiconductor components and/or the assemblies containing them were even smaller. An object of the invention is therefore to reduce the size of semiconductor components and/or systems containing semiconductor components. This and other objects are achieved according to the invention by the semiconductor components and the processes for production thereof wherein the points of contact are a constituent of an electrically conductive structure embedded in the semiconductor component housing and terminating externally flush therewith.
The invention will be described in more detail below with the aid of embodiments with reference to the drawings, in which:
Figures 1A to 1H show schematic views to illustrate a first process described below for producing semiconductor components; Figures 2A to 2H show schematic views to illustrate a second process described below for producing semiconductor components; and
Figures 3A to 3F show schematic views to illustrate a third process described below for producing semiconductor components.
With regard to the figures, it is to be noted that, even though they are sectional views, they do not contain any hatching; it has been omitted for the purpose of greater clarity. Furthermore, reference is made at this point to the fact that the elements which are denoted by the same reference numerals in the various drawings are the same elements, or elements corresponding to one another. The semiconductor component described below is, for example, a microprocessor, microcontroller, memory chip (RAM, ROM, flash memory) or any other semiconductor component .
A first process for producing a semiconductor component formed as mentioned is now described with reference to Fig. 1A to 1H.
The production of the semiconductor component begins in that a temporary substrate 1 formed by a plate-like element is prepared. This state is illustrated in Fig. 1A.
The substrate 1 consists, in the example considered, of metal, for example of copper, aluminum or steel, and is 200 μm to 300 μm thick.
A layer of electrically conductive material is initially applied to this substrate 1. After its production, this layer forms the electrically conductive structure 3, and a base 4, on which the semiconductor chip, which is later to be accommodated in the semiconductor component 5, is placed and fixed. The production of the layer begins in that the substrate 1 is coated on its upper side with a photosensitive material 2. How the coating is applied, i.e. whether a liquid material is applied, or whether a film coated with the material is laminated onto the substrate 1, or whether the material is applied to the substrate 1 in another way, is unimportant in the example considered. The layer of material is approximately 6 μm thick in the example considered. The substrate 1 coated with the material 2 is illustrated in Fig. IB.
The photosensitive material 2 is then exposed and developed in such a way that it is removed at the points at which the substrate 1 is to be provided with the electrically conductive layer. In the example considered, development is carried out using an agent which causes the photosensitive material 2 remaining on the substrate 1 to have a ramp-like course at the transition between the points at which the photosensitive material 2 remains on the substrate 1 and the points at which the photosensitive material 2 has been removed from the substrate 1. Such agents are agents which cause the photosensitive material 2 remaining on the substrate 1 to shrink upon drying after treatment with the agent. The substrate 1 with the photosensitive material 2 structured as described is illustrated in Fig. lC.
Then, application of the thin layer of electrically conductive material is begun at the points at which the photosensitive material 2 has been removed. In the example considered a ultilayered structure is applied, namely initially an approximately 6 μm thick nickel layer 31, and another approximately 1 μm thick gold layer 32 on top. These layers are produced by an electroplating process. The nickel layer 31 can then begin to grow at those points at which the photosensitive material 2 has been removed. The nickel settles at the points of the substrate 1 free of the photosensitive material 2 and grows into an ever thicker layer. When the nickel layer 31 has attained the desired thickness, this process is terminated and the application of the gold layer 32 onto the nickel layer
31 is begun. This is also effected by means of an electroplating process. When the gold layer 32 has attained the desired thickness the process is terminated. As a result, the production of the layer forming the electrically conductive structure 3 and the base 4 is terminated. The substrate 1 is then in the state illustrated in Fig. ID. Afterwards the photosensitive material 2 still on the substrate 1 is removed. The substrate 1 is then in the state illustrated in Fig. IE.
It can clearly be seen from Fig. IE that the layer 31, 32 applied to the substrate 1 has a non-rectangular cross-section; the cross-section is narrower at the bottom than further up. It will be better understood later that because of this cross-section, the layer 31,
32 can be integrated into the semiconductor component in such a way that even when it comes to rest on the edge of the semiconductor component housing, it cannot detach therefrom. It should be understood that layer 31, 32 does not have to have the exact cross-section shown in Fig. IE. The only condition which must be fulfilled is that the cross-section has its greatest width at a point which, once the layer 3 is integrated in the semiconductor component, does not come to rest on the outer edge of the semiconductor component.
The semiconductor chip 5, is then placed on and fixed to the substrate 1 on a base 4 formed by the previous coating of the substrate 1. Fixing is preferably by means of an adhesive 6 but can also be accomplished in any other way.
Then, electrical connections to the semiconductor chip 5 are formed by wire bonding to the electrically conductive structure 3. The bonding wires are denoted by the reference numeral 7 in the figures. See Fig. IF.
Then, the assembly is covered by a casting compound 8 as illustrated in Fig. 1G. The casting compound surrounds all previously mentioned parts of the semiconductor component except the substrate 1 and forms a housing, which fixes the parts of the semiconductor component in their correct position and protects them from damage .
Finally the substrate 1 is removed. This can be done by etching. The resulting assembly shown in Fig. 1H is the finished semiconductor component.
As can be seen from Fig. 1H, as a result of the removal of the substrate 1, the parts of the electrically conductive structure 3 and of the base 4 originally resting thereon are exposed. The electrically conductive structure 3 and the base 4 terminate flush with the semiconductor component housings formed by the casting compound 8. The parts of the electrically conductive structure 3, now exposed, can be used as points of contact. The exposed part of the base 4 can also serve as a cooling face by means of which the heat produced in the semiconductor chip 5 and conveyed by the base 4 can be released to the outside.
A semiconductor component designed and produced as described has proved to be advantageous in many ways: on the one hand it has a very small (thin) electrically conductive structure for producing the points of contact for the connection of the semiconductor component to other elements and for the connection of the points of contact to the semiconductor chip 5, and in addition also contains a cooling element. As a result, the semiconductor component and/or the system containing the semiconductor component, can be formed considerably smaller than was previously the case. The semiconductor component has an extremely low height and need no longer be cooled by cooling elements placed on the outside of the semiconductor component or, if need be, by comparatively small cooling elements. The same or similar advantages can also be achieved moreover by the semiconductor components described below with reference to Fig. 2 and 3.
A semiconductor component which is constructed somewhat differently and its production is now described with reference to Fig. 2A to 2H. The construction and the production of the semiconductor component in accordance with Fig. 1 and the construction and production of the semiconductor component in accordance with Fig. 2 are for the most part identical. The only difference is that the semiconductor chip 5 of the semiconductor component in accordance with Fig. 2 is glued directly onto the substrate 1. Accordingly the production of the semiconductor component in accordance with Fig. 2 is largely identical to the production of the semiconductor component in accordance with Fig. 1. Therefore, for the most part, reference can be made to the corresponding embodiments of the semiconductor component in accordance with Fig. 1.
The starting point is again the temporary substrate 1 already used in the semiconductor component in accordance with Fig. 1. The substrate 1 is coated with a photosensitive material 2. Afterwards the photosensitive material 2 is removed from the substrate 1 by appropriate exposure and development at the points at which an electrically conductive layer is to be applied to the substrate 1. As can be seen from Fig. 2C showing the resulting assembly, in the case of the semiconductor component in accordance with Fig. 2 however, these are only those points at which the substrate 1 is to be provided with the electrically conductive structures 3. With the semiconductor component in accordance with Fig. 2 the base 4 is not required. The photosensitive material 2 is moreover exposed and developed as was described with reference to Fig. 1, in particular to Fig. 1C. Subsequently, the electrically conductive layer forming the electrically conductive structure 3 is applied to the points of the substrate 1 from which the photosensitive material 2 has been removed.
Then, the photosensitive material 2 still present on the substrate 1 is removed. The resulting assembly is illustrated in Fig. 2E.
Subsequently, the semiconductor chip 5 is mounted and connected to the electrically conductive structure 3. The semiconductor chip 5 is, as has already been mentioned above, not placed on a base as in the case of the semiconductor component in accordance with Fig. 1, but directly on to the substrate 1. Fixing is again preferably by means of the adhesive 6. The construction of the resulting assembly is illustrated in Fig. 2F. Then, the assembly shown in Fig. 2F is covered with the casting compound which later forms the semiconductor component housing. The resulting assembly is illustrated in Fig. 2G.
Finally, the substrate 1 is removed and the resulting assembly is shown in Fig. 2H. Fig. 2H shows the adhesive 6, by means of dashed lines. This indicates that the adhesive 6 can also still be removed.
The semiconductor component shown in Fig. 2 and described with reference thereto has an even lower height than the semiconductor component in accordance with Fig. 1. This is because the semiconductor chip 5, by virtue of the fact that it is not arranged on a base but directly on the temporary substrate 1, comes to rest closer to the lower edge of the semiconductor component than is the case with the semiconductor component in accordance with Fig. 1, and because, as a result, the highest point of the bonding wires 7 decisively determining the height of the semiconductor component is lowered without a substantial change in the shape of the bonding wire loop relative to the lower side of the semiconductor component. The omission of the base 4, does not constitute a disadvantage with the semiconductor component in accordance with Fig. 2. Because of its immediate proximity to the lower edge of the semiconductor component, the semiconductor chip 5 in particular is well cooled, even without the base 4. Above all, if the adhesive 6 is also removed and the semiconductor chip 5 is therefore no longer covered by anything at its lower side, the semiconductor chip experiences even better cooling than is the case with an assembly on a base, regardless of how it is constructed.
As was already mentioned above, the electrically conductive structure formed by the electrically conductive layer can also be multilayered. The construction and production of a semiconductor component having a multilayered electrically conductive structure is described below with reference to Fig. 3A to 3F.
The starting point is again a temporary substrate 1. An electrically conductive layer is applied to this substrate 1 in the manner described with reference to Fig. 1. This electrically conductive layer is formed in the example considered, however, only" by a nickel layer 31. The application of a gold layer 32 to this nickel layer is dispensed with here because, as will be described later, this nickel layer, described below as a first electrically conductive layer, is to be connected only to a second electrically conductive layer arranged thereabove and, as in the case of the semiconductor component in accordance with Fig. 1, is used as a base 4 on which the semiconductor chip 5 is later placed. The substrate 1 and the steps to be carried out to apply the first electrically conductive layer are illustrated in Fig. 3A. The individual illustrations of Fig. 3A correspond to Fig. 1A to IE, so, with regard to further details, reference can be made to the description referring thereto.
The substrate 1 provided with the first electrically conductive layer is then coated with a photosensitive dielectric 9. In this case both the electrically conductive layer and the non-coated parts of the substrate 1 are covered by a dielectric layer. Subsequently, the dielectric 9 is exposed and developed in such a way that, at the points at which the second electrically conductive layer to be applied to the dielectric 9 is connected to the first electrically conductive layer extending beneath the dielectric 9, and at the point where the base 4 is located, it is removed down to the first electrically conductive layer. The resulting assembly is illustrated in Fig. 3B.
The second electrically conductive layer is subsequently applied to the dielectric 9. This layer is preferably applied by sputtering. The material used for coating, which in the example considered is again nickel, is applied to the upper side of the dielectric layer in such a way that the second electrically conductive layer produced as a result also has the desired structure. The nickel furthermore reaches the channels formed by the previous exposure and development of the dielectric layer for connecting the second electric layer to the first electrically conductive layer and deposits itself therein (predominantly on the side walls thereof) in such a way that an electric connection between the first electrically conductive layer and the second electrically conductive layer is formed as a result. As a result, a second electrically conductive layer is formed on the dielectric layer and connected to selected parts of the first electrically conductive layer located beneath the dielectric layer. The resulting assembly is illustrated in Fig. 30.
If a further electrically conductive layer is to be provided above the second electrically conductive layer, a dielectric layer is initially again applied to the assembly shown in Fig. 30 and structured as desired. This is done in the manner described above with reference to Fig. 3B. For the sake of completeness, reference is made to the fact that when applying the dielectric layer, the channels via which the electrically conductive layer located beneath the further dielectric layer is connected to the electrically conductive layer therebelow, are also filled with a dielectric. As was already mentioned, substantially only the side walls of these channels are covered by an electrically conductive layer. Following the application and structuring of this further dielectric layer, a further electrically conductive layer having a desired structure is applied thereto. This is done in the manner described above with reference to Fig. 30. Because of frequent repetition of the processes described with reference to Fig. 3B and 30 an electrically conductive structure with any number of superimposed electrically conductive layers can be produced.
It is advantageous if the electrically conductive layers to which the bonding are soldered, are produced from a material which permits particularly good connections, for example from gold.
In the example considered, the multilayered electrically conductive structure comprises three electrically conductive layers which are separated from one another by a dielectric layer in each case and are connected to one another at selected points by the connecting structures penetrating the dielectric layers. The two lower electrically conductive layers consist only of nickel and the uppermost electrically conductive layer is coated with gold.
After the multilayered electrically conductive structure is finished, the semiconductor chip 5 is inserted. In the example considered, this is done by gluing the semiconductor chip to the base 4. It should be clear that the semiconductor chip could be placed directly onto the substrate 1 as in the case of the semiconductor component in accordance with Fig. 2. Subsequently, the semiconductor chip 5 is connected to selected points of the uppermost electrically conductive layer (or another electrically conductive layer) by means of bonding wires 7. This is illustrated in Fig. 3D.
Then, the assembly shown in Fig. 3D is covered by the casting compound 8 forming the semiconductor component housing. This is illustrated in Fig. 3E . Subsequently the substrate 1 is removed. The finished semiconductor component is illustrated in Fig. 3F. As a result of the removal of the substrate 1, the multilayered electrically conductive structure, more precisely, the lowest electrically conductive layer thereof, terminates with the semiconductor component housing formed by the casting compound in a flush manner. As a result, even with a multilayered electrically conductive structure, certain parts thereof can be used as points of contact.
It should be clear that multilayered electrically conductive structures of the above-described type can also be produced in a manner different to that described above .
The provision of a multilayered electrically conductive structure in the semiconductor component makes it possible to realize any complex connections between the semiconductor chip 5, the points of contact of the semiconductor component and/or further components which are accommodated in the semiconductor component. Even electrical connections which are normally made outside of the semiconductor component can be moved into the semiconductor component.
The semiconductor component is not, or certainly not automatically, larger as a result of the provision of a multilayered electrically conductive structure, in particular if the multilayered electrically conductive structure is produced as described above or similarly, in other words using thin electrically conductive layers. The semiconductor component described with reference to Fig. 3 is still smaller in structure, despite the provision of a three-layered electrically conductive structure, than a semiconductor component produced in the conventional manner without a multilayered electrically conductive structure.
Despite the advantages mentioned of the described semiconductor components, these are not in any way expensive and complicated to produce. Production is particularly simple if the components forming the semiconductor components are joined together at least partially using processing stages, which simultaneously advances the production of a plurality of semiconductor components. This is the case not only in the production of the above-described semiconductor components but also in the production of any other semiconductor components. The processing stages used in the production of semiconductor components, which simultaneously bring about the production of a plurality of semiconductor components, can be produced particularly easily, however, with the semiconductor components described above .
The use of the temporary substrate is an ideal prerequisite for the simultaneous production of a large number of semiconductor components. An appropriately large substrate must merely be used. Electrically conductive structures 3 and bases 4 can be applied to a large substrate for a large number of semiconductor component [s] and a correspondingly large number of semiconductor components can be assembled as in the examples described above.
The simultaneous production of a large number of semiconductor components using a common substrate simplifies their production considerably. In the examples described above, it means that
- not every individual semiconductor component has to be brought to the next workstation after each processing step and be aligned and processed there,
- the photosensitive material 2 can be applied to the substrate 1 in a single operation for a large number of semiconductor components,
- the photosensitive material 2 can be exposed in a single operation for a large number of semiconductor components, - the photosensitive material 2 can be developed in a single operation for a large number of semiconductor components,
- the substrate 1 can be coated with the electrically conductive layer in a single operation for a large number of semiconductor components,
- the photosensitive material 2 can be removed in a single operation for a large number of semiconductor components,
- a dielectric layer can be applied in the case of a multilayered electrically conductive structure in a single operation for a large number of semiconductor components,
- the dielectric layer can be exposed in a single operation for a large number of semiconductor components,
- the dielectric layer can be developed in a single operation for a large number of semiconductor components,
- an electrically conductive structure can be applied to the dielectric layer in a single operation for a large number of semiconductor components,
- not every semiconductor component has to be surrounded individually by a dam by means of which separation of the casting compound forming the semiconductor component housing is prevented (it is sufficient if a common dam is formed for a plurality or all of the semiconductor components to be produced' simultaneously; the semiconductor components to be connected to one another by the application of the casting compound can then be separated by sawing or cutting them apart, for example by water jet cutting),
- the semiconductor component components can be covered by the casting compound in a single operation for a large number of semiconductor components, and
- the substrate can be removed in a single operation for a large number of semiconductor components .
It should be clear that the processes described can be modified in many aspects. The substrate 1 preferably but not limited to a thickness of 200 μm to 300 μm. It can also be thicker or thinner.
Furthermore, the photoelectric material 2 is preferably but not limited to a thickness of 6 μm. The material 2 can also be thicker or thinner and its thickness is also independent of the thickness of the electrically conductive layer to be applied to the substrate 1. It can even prove to be advantageous if the photosensitive material layer is thinner than the nickel layer to be applied to the substrate. In this case the nickel layer accumulates from the point at which it reaches a thickness corresponding to the thickness of the layer of material, not only upwards but also sideways, and this has the positive effect that the lateral limiting faces of the electrically conductive layers have a still more marked overhang structure and therefore ensure an even better retention of the electrically conductive layer in the housing formed by the casting compound. In this case, structuring of the photosensitive material 2 in such a way that it has a ramp-like profile at the transition to the points where it has been removed from the substrate may possibly even be dispensed with.
The photosensitive material 2 can also be applied to the substrate 1 directly in the structure it should have, so that the substrate 1 can be provided with an electrically conductive layer as described. This is possible, for example, if the photosensitive material 2 is applied to the substrate by a printing process, for example by a screen printing process. As a result, use of a photosensitive material is not necessary and neither is structuring of the material by means of appropriate exposure and development as desired. For the sake of completeness it is noted that it is also advantageous in this case if the photosensitive material 2 has a ramp-like course at the transitions to the points where there is no material.
Furthermore, the fact that the electrically conductive layers are multilayered does not represent a limitation. They can also be composed of more or fewer layers, for example they can either consist of a nickel layer only or a gold layer only, or a copper layer, a nickel layer and a gold layer.
In principle any other materials can also be used to produce the electrically conductive layer.
The electrically conductive layer can also be thicker or thinner than in the examples considered. The thickness of the electrically conductive layer is preferably in the range between 1 μm and 10 μm. Good results can also be achieved, however, if the electrically conductive layer is up to 15 μm or up to 20 μm thick.
The electrically conductive layer also does not need to be applied to the substrate by an electroplating process. It is also possible to apply the electrically conductive layer by sputtering or to place and fix prefabricated electrically conductive structures on/to the substrate. In this event it would not be necessary for the substrate to consist of metal. It is of course also possible to design and extend the electrically conductive layer in such a way that semiconductor chips 5 with flip-chip design can be assembled on the electrically conductive structure. When using semiconductor chips with flip-chip design, it has proved to be advantageous if the semiconductor component housing is only so high such that the semiconductor chip terminates with the upper side of the housing in a flush manner. As a result, the semiconductor components can be designed even lower than was previously the case. A semiconductor component containing a flip-chip can be so small that it is only slightly larger than the flip-chip itself.
The described semiconductor components, the described electrically conductive structures for semiconductor components and the described processes for production thereof make possible a reduction in size and a very simple and rapid production of semiconductor components and systems containing semiconductor components, irrespective of particulars regarding the practical realization.
A whole range of advantages can be achieved as a result of the provision of the features mentioned.
Since the electrically conductive structures to be provided in the semiconductor component for producing the points of contact and/or connections between the semiconductor chip, the points of contact, and/or further components contained in the semiconductor component are formed by thin layers of electrically conductive material, the height of the semiconductor component can be reduced. The production of electrically conductive structures by using thin electrically conductive layers even permits multilayered electrically conductive structures to be accommodated in the smallest of spaces. Because of the multilayered electrically conductive structures, complex connections between the semiconductor chip, the points of contact of the semiconductor component and/or further components which are provided in the semiconductor component can also be made within the semiconductor component and/or connections which are normally made outside of the semiconductor component can be moved into the semiconductor component. As a result, even complex multi-chip semiconductor components can be produced which are smaller and, at the same time, more powerful than hitherto.
As a result of the fact that the layers forming the electrically conductive structures have a non- rectangular cross-section, layers extending on the outside of the semiconductor component housing can be securely integrated into the semiconductor component housing in all circumstances and cannot detach themselves therefrom.
The formation of the thin layers forming the electrically conductive structures on a temporary substrate, and the removal of this temporary substrate after integration of the electrically conductive structure supported by it into the semiconductor component mean that even the thinnest layers can be integrated in the semiconductor component quickly and simply.
The temporary substrate also facilitates placing of the semiconductor chip within the semiconductor component as desired. If use is made of this possibility to the effect that the semiconductor chip is placed on an element (formed on the substrate element) with high thermal conductivity, and/or that the semiconductor chip is only partially surrounded by the semiconductor component housing, then additional measures for cooling the semiconductor component can be completely or partially dispensed with. As a result, the size of the system containing the semiconductor component is reduced.
Furthermore, the temporary substrate can be used as a common substrate for a plurality of semiconductor components which are to be produced simultaneously. If this is done and the joining of the individual parts which fit together to produce the semiconductor component is carried out at least partially using processing stages, which simultaneously bring about the production of a plurality of semiconductor components, then, on top of that, the semiconductor components can also be produced particularly quickly and simply.

Claims

1. A semiconductor component having a semiconductor chip (5) , points of contact for electrical connection of the semiconductor component to other devices, and a housing (8) incorporating the individual parts of the semiconductor component being characterized in that the points of contact are a constituent of an electrically conductive structure (3) embedded in the semiconductor component housing and terminating externally flush therewith.
2. The semiconductor component according to claim 1, characterized in that the electrically conductive structure (3) is multilayered.
3. The semiconductor component according to claim 1, characterized in that the electrically conductive structure (3) is formed by a number of thin layers (31; 32; 31, 32) of electrically conductive material corresponding to the number of layers of the electrically conductive structure.
4. The semiconductor component according to claim 3, characterized in that the electrically conductive layers
(31; 32; 31, 32) have a thickness between 1 μm and 20 μm.
5. The semiconductor component according to claim 3, characterized in that the electrically conductive layers
(31; 32; 31, 32) have a thickness between 1 μm and 15 μm.
6. The semiconductor component according to claim 3, characterized in that the electrically conductive layers (31; 32; 31, 32) have a thickness between 1 μm and 10 μm.
7. The semiconductor component according to one of claims 3 to 6, characterized in that the electrically conductive layers (31; 32; 31, 32) consist at least partially of a plurality of superimposed layers (31, 32) consisting of different materials.
8. The semiconductor component according to claim 3, characterized in that the electrically conductive layers (31; 32; 31, 32) have a non-rectangular cross-section.
9. The Semiconductor component according to claim 8, characterized in that the cross-section of the electrically conductive layers (31; 32; 31, 32), have a smaller width in the region which comes to rest on the outside than in a region located further inside the semiconductor component.
10. A semiconductor component having a semiconductor chip (5), points of contact for electrical connection of the semiconductor component to other devices, a housing (8) incorporating the individual parts of the semiconductor component being characterized in that the semiconductor chip (5) is placed on an element (4) with high thermal conductivity.
11. The semiconductor component according to claim 10, characterized in that the element (4) supporting the semiconductor chip (5) consists of metal.
12. The semiconductor component according to claim 10, characterized in that the element (4) supporting the semiconductor chip (5) is only partially surrounded by the semiconductor component housing (8) .
13. The semiconductor component according to one of claims 10 to 12, characterized in that at least one of the sides not supporting the semiconductor chip (5) of the element (4) supporting the semiconductor chip terminates flush with one of the outer faces of the semiconductor component housing (8) .
14. A semiconductor component with a semiconductor chip (5), oints of contact for electrical connection of the semiconductor component to other devices, and a housing (8) incorporating the individual parts of the semiconductor component, being characterized in that the semiconductor chip (5) is only partially surrounded by the semiconductor component housing (8) .
15. A Process for producing a semiconductor component having a semiconductor chip (5) ,points of contact for electrical connection of the semiconductor component to other devices, and a housing (8) incorporating the individual parts of the semiconductor component, characterized in that an electrically conductive structure (3) or parts of an electrically conductive structure are used as points of contact, which structure is formed on a temporary substrate (1), and in that the temporary substrate is removed at a point in time after the embedding of the electrically conductive structure in the semiconductor component housing (8) .
16. The process according to claim 15, characterized in that a substrate (1) with electrically conductive structures (3) is used for a plurality of semiconductor components, and in that by using the one substrate, a plurality of semiconductor components can be produced simultaneously.
17. A Process for producing a semiconductor component with a semiconductor chip (5) ,points of contact for electrical connection of the semiconductor component to other devices, and a housing (8) incorporating the individual parts of the semiconductor component, characterized in that the individual parts (3 to 9) which fit together to produce the semiconductor component are joined at least partially by using processing stages, which simultaneously bring about the production of a plurality of semiconductor components.
18. The process according to claim 17, characterized in that by using a common substrate (1), a plurality of semiconductor components are produced simultaneously.
19. The process according to claim 18, characterized in that a dam which surrounds a plurality or all of the semiconductor components which are to be produced simultaneously is prodμced on the common substrate (l),the region inside the dam is filled with a compound forming the semiconductor component housing (8), and at a later point in time semiconductor components which are held together by the compound are separated by sawing or cutting them apart.
20. The process according to claim 19,, characterized in that the common substrate (1) is removed at a point in time between the application of the compound forming the semiconductor component housing (8) and the separation of the semiconductor components.
21. An electrically conductive structure for a semiconductor component, characterized in that the electrically conductive structure (3) is formed by one or more thin layers (31; 32; 31, 32) of electrically conductive material, which are structured in accordance with the electrically conductive structure which they are to form.
22. The electrically conductive structure according to claim 21, characterized in that the electrically conductive structure is multilayered.
23. The electrically conductive structure according to claim 22, characterized in that the electrically conductive structure (3) is formed by a number of thin layers (31; 32; 31, 32) of electrically conductive material corresponding to the number of plies of the electrically conductive structure, which thin layers are structured in accordance with the electrically conductive structure which they are to form.
24. The electrically conductive structure according to claim 23, characterized in that the electrically conductive structure (3) is provided on a substrate (1) which can be removed from the structure.
25. The electrically conductive structure according to claim 24, characterized in that the electrically conductive layers (31; 32; 31, 32) have a thickness between 1 μm and 20 μm.
26. The electrically conductive structure according to claim 24, characterized in that the electrically conductive layers (31; 32; 31, 32) have a thickness between 1 μm and 15 μm.
27. The electrically conductive structure according to claim 24, characterized in that the electrically conductive layers (31; 32; 31, 32) have a thickness between 1 μm and 10 μm.
28. The Electrically conductive structure according claims 27, characterized in that the electrically conductive layers (31; 32; 31, 32) consist at least partially of a plurality of superimposed layers (31, 32) consisting of different materials.
29. The electrically conductive structure according to claim 28, characterized in that the electrically conductive layers (31; 32; 31, 32) have a non- rectangular cross-section.
30. The electrically conductive structure according to claim 29, characterized in that the cross-section of the electrically conductive layers (31; 32; 31, 32), which should be a constituent of the external face of the semiconductor component, has a smaller width in the region coming to rest on the outside than in a region located further inside the semiconductor component.
PCT/IB2001/000891 2000-06-02 2001-05-22 Semiconductor component, electrically conductive structure therefor, and process for production thereof WO2001093327A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE10196279T DE10196279T1 (en) 2000-06-02 2001-05-22 Semiconductor component, electrically conductive structure therefor and process for the production thereof
AU62566/01A AU6256601A (en) 2000-06-02 2001-05-22 Semiconductor component, electrically conductive structure therefor, and processfor production thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10027492.7 2000-06-02
DE10027492 2000-06-02

Publications (1)

Publication Number Publication Date
WO2001093327A1 true WO2001093327A1 (en) 2001-12-06

Family

ID=7644540

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2001/000891 WO2001093327A1 (en) 2000-06-02 2001-05-22 Semiconductor component, electrically conductive structure therefor, and process for production thereof

Country Status (2)

Country Link
AU (1) AU6256601A (en)
WO (1) WO2001093327A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008059301A1 (en) * 2006-11-14 2008-05-22 Infineon Technologies Ag An electronic component and method for its production

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208756A (en) * 1983-05-12 1984-11-27 Sony Corp Manufacture of semiconductor device package
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
EP0751561A1 (en) * 1994-03-18 1997-01-02 Hitachi Chemical Co., Ltd. Semiconductor package manufacturing method and semiconductor package
EP0773584A2 (en) * 1995-11-08 1997-05-14 Fujitsu Limited Device having resin package and method of producing the same
JPH11195733A (en) * 1997-10-28 1999-07-21 Seiko Epson Corp Semiconductor device and manufacture thereof, and conductive board thereof
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208756A (en) * 1983-05-12 1984-11-27 Sony Corp Manufacture of semiconductor device package
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
EP0751561A1 (en) * 1994-03-18 1997-01-02 Hitachi Chemical Co., Ltd. Semiconductor package manufacturing method and semiconductor package
EP0773584A2 (en) * 1995-11-08 1997-05-14 Fujitsu Limited Device having resin package and method of producing the same
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
JPH11195733A (en) * 1997-10-28 1999-07-21 Seiko Epson Corp Semiconductor device and manufacture thereof, and conductive board thereof

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 009, no. 069 (E - 305) 29 March 1985 (1985-03-29) *
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 12 29 October 1999 (1999-10-29) *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008059301A1 (en) * 2006-11-14 2008-05-22 Infineon Technologies Ag An electronic component and method for its production
US8049311B2 (en) 2006-11-14 2011-11-01 Infineon Technologies Ag Electronic component and method for its production

Also Published As

Publication number Publication date
AU6256601A (en) 2001-12-11

Similar Documents

Publication Publication Date Title
CN102067310B (en) Stacking of wafer-level chip scale packages having edge contacts and manufacture method thereof
TW384531B (en) Semiconductor device, method of manufacturing semiconductor device and a method of manufacturing lead frame
US8604348B2 (en) Method of making a connection component with posts and pads
EP1143509A2 (en) Method of manufacturing the circuit device and circuit device
EP0798780A2 (en) Semiconductor device, manufacturing method thereof and aggregate type semiconductor device
JP3007833B2 (en) Semiconductor device and its manufacturing method, lead frame and its manufacturing method
KR100989007B1 (en) Semiconductor device and method of manufacturing same
US20060202347A1 (en) Through electrode, package base having through electrode, and semiconductor chip having through electrode
WO1998052225A1 (en) An electronic component package with posts on the active surface
JP2008091852A (en) Stacked package, and method of manufacturing the same
US20120146199A1 (en) Substrate for integrated circuit package with selective exposure of bonding compound and method of making thereof
EP1109219A2 (en) Semiconductor device having a wiring layer
JP2003282787A (en) Chip package and its manufacturing method
US20050212107A1 (en) Circuit device and manufacturing method thereof
US20210210453A1 (en) Pre-Molded Leadframes in Semiconductor Devices
JP2001044357A (en) Semiconductor device and manufacture thereof
JP2007134697A (en) Method of fabricating vertically mountable ic package
KR100345166B1 (en) Wafer level stack package and method of fabricating the same
JP2008504696A (en) Parts with posts and pads
KR100717632B1 (en) Semiconductor device and process of producing same
KR100594827B1 (en) Production of semiconductor device
JP2005294443A (en) Semiconductor device and its manufacturing method
WO1998052222A1 (en) Integrated passive components and package with posts
JP4046568B2 (en) Semiconductor device, stacked semiconductor device, and manufacturing method thereof
WO2001093327A1 (en) Semiconductor component, electrically conductive structure therefor, and process for production thereof

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
RET De translation (de og part 6b)

Ref document number: 10196279

Country of ref document: DE

Date of ref document: 20030612

Kind code of ref document: P

WWE Wipo information: entry into national phase

Ref document number: 10196279

Country of ref document: DE

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP