WO2001093029A3 - Speculative program execution with value prediction - Google Patents

Speculative program execution with value prediction Download PDF

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Publication number
WO2001093029A3
WO2001093029A3 PCT/US2001/017646 US0117646W WO0193029A3 WO 2001093029 A3 WO2001093029 A3 WO 2001093029A3 US 0117646 W US0117646 W US 0117646W WO 0193029 A3 WO0193029 A3 WO 0193029A3
Authority
WO
WIPO (PCT)
Prior art keywords
result
thread
speculative
code
section
Prior art date
Application number
PCT/US2001/017646
Other languages
French (fr)
Other versions
WO2001093029A2 (en
Inventor
Shailender Chaudhry
Marc Tremblay
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Priority to AU2001268121A priority Critical patent/AU2001268121A1/en
Publication of WO2001093029A2 publication Critical patent/WO2001093029A2/en
Publication of WO2001093029A3 publication Critical patent/WO2001093029A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Devices For Executing Special Programs (AREA)

Abstract

One embodiment of the present invention provides a system that predicts a result produced by a section of code in order to support speculative program execution. The system begins by executing the section of code using a head thread in order to produce a result. Before the head thread produces the result, the system generates a predicted result to be used in place of the result. Next, the system allows a speculative thread to use the predicted result in speculatively executing subsequent code that follows the section of code. After the head thread finishes executing the section of code, the system determines if a difference between the predicted result and the result generated by the head thread has affected execution of the speculative thread. If so, the system executes the subsequent code again using the result generated by the head thread. If not, the system performs a join operation to merge state associated with the speculative thread with state associated with the head thread. In one embodiment of the present invention, executing the subsequent code again involves performing a rollback operation for the speculative thread to undo actions performed by the speculative thread.
PCT/US2001/017646 2000-05-31 2001-05-30 Speculative program execution with value prediction WO2001093029A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001268121A AU2001268121A1 (en) 2000-05-31 2001-05-30 Speculative program execution with value prediction

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US20842900P 2000-05-31 2000-05-31
US60/208,429 2000-05-31
US09/761,217 US7051192B2 (en) 2000-05-31 2001-01-16 Facilitating value prediction to support speculative program execution
US09/761,217 2001-01-16

Publications (2)

Publication Number Publication Date
WO2001093029A2 WO2001093029A2 (en) 2001-12-06
WO2001093029A3 true WO2001093029A3 (en) 2002-12-05

Family

ID=26903189

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/017646 WO2001093029A2 (en) 2000-05-31 2001-05-30 Speculative program execution with value prediction

Country Status (3)

Country Link
US (2) US7051192B2 (en)
AU (1) AU2001268121A1 (en)
WO (1) WO2001093029A2 (en)

Families Citing this family (20)

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Publication number Priority date Publication date Assignee Title
US6772321B2 (en) 2000-05-04 2004-08-03 Sun Microsystems, Inc. Method and apparatus for using an assist processor and value speculation to facilitate prefetching for a primary processor
WO2002057909A2 (en) * 2001-01-16 2002-07-25 Sun Microsystems, Inc. Value speculation on an assist processor to facilitate prefetching for a primary processor
US20050144604A1 (en) * 2003-12-30 2005-06-30 Li Xiao F. Methods and apparatus for software value prediction
US7124254B2 (en) * 2004-05-05 2006-10-17 Sun Microsystems, Inc. Method and structure for monitoring pollution and prefetches due to speculative accesses
US8595744B2 (en) * 2006-05-18 2013-11-26 Oracle America, Inc. Anticipatory helper thread based code execution
US20080141268A1 (en) * 2006-12-12 2008-06-12 Tirumalai Partha P Utility function execution using scout threads
US8561046B2 (en) * 2009-09-14 2013-10-15 Oracle America, Inc. Pipelined parallelization with localized self-helper threading
US8782434B1 (en) 2010-07-15 2014-07-15 The Research Foundation For The State University Of New York System and method for validating program execution at run-time
US9182991B2 (en) 2012-02-06 2015-11-10 International Business Machines Corporation Multi-threaded processor instruction balancing through instruction uncertainty
DE102012206497A1 (en) * 2012-04-19 2013-10-24 Siemens Aktiengesellschaft Data processing arrangement for accelerating processing of input data sets, has providing unit, which reads one intermediate result coinciding with another intermediate result with respect to typically known intermediate result
US9063721B2 (en) 2012-09-14 2015-06-23 The Research Foundation For The State University Of New York Continuous run-time validation of program execution: a practical approach
US9069782B2 (en) 2012-10-01 2015-06-30 The Research Foundation For The State University Of New York System and method for security and privacy aware virtual machine checkpointing
US9348599B2 (en) 2013-01-15 2016-05-24 International Business Machines Corporation Confidence threshold-based opposing branch path execution for branch prediction
CN103330935A (en) * 2013-06-17 2013-10-02 中山大学 Application of fructose as vaccine adjuvant
US9348595B1 (en) 2014-12-22 2016-05-24 Centipede Semi Ltd. Run-time code parallelization with continuous monitoring of repetitive instruction sequences
US9135015B1 (en) * 2014-12-25 2015-09-15 Centipede Semi Ltd. Run-time code parallelization with monitoring of repetitive instruction sequences during branch mis-prediction
US9208066B1 (en) 2015-03-04 2015-12-08 Centipede Semi Ltd. Run-time code parallelization with approximate monitoring of instruction sequences
US10296346B2 (en) 2015-03-31 2019-05-21 Centipede Semi Ltd. Parallelized execution of instruction sequences based on pre-monitoring
US10296350B2 (en) 2015-03-31 2019-05-21 Centipede Semi Ltd. Parallelized execution of instruction sequences
US9715390B2 (en) 2015-04-19 2017-07-25 Centipede Semi Ltd. Run-time parallelization of code execution based on an approximate register-access specification

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US4760520A (en) * 1984-10-31 1988-07-26 Hitachi, Ltd. Data processor capable of executing instructions under prediction
US5919256A (en) * 1996-03-26 1999-07-06 Advanced Micro Devices, Inc. Operand cache addressed by the instruction address for reducing latency of read instruction
US5996060A (en) * 1997-09-25 1999-11-30 Technion Research And Development Foundation Ltd. System and method for concurrent processing

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GB2292822A (en) * 1994-08-31 1996-03-06 Hewlett Packard Co Partitioned cache memory
US5860017A (en) * 1996-06-28 1999-01-12 Intel Corporation Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction
US5850543A (en) * 1996-10-30 1998-12-15 Texas Instruments Incorporated Microprocessor with speculative instruction pipelining storing a speculative register value within branch target buffer for use in speculatively executing instructions after a return
US6574725B1 (en) * 1999-11-01 2003-06-03 Advanced Micro Devices, Inc. Method and mechanism for speculatively executing threads of instructions
US6665708B1 (en) * 1999-11-12 2003-12-16 Telefonaktiebolaget Lm Ericsson (Publ) Coarse grained determination of data dependence between parallel executed jobs in an information processing system
US6345351B1 (en) * 1999-11-12 2002-02-05 Telefonaktiebolaget Lm Ericsson(Publ) Maintenance of speculative state of parallel executed jobs in an information processing system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4760520A (en) * 1984-10-31 1988-07-26 Hitachi, Ltd. Data processor capable of executing instructions under prediction
US5919256A (en) * 1996-03-26 1999-07-06 Advanced Micro Devices, Inc. Operand cache addressed by the instruction address for reducing latency of read instruction
US5996060A (en) * 1997-09-25 1999-11-30 Technion Research And Development Foundation Ltd. System and method for concurrent processing

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MARCUELLO ET AL: "Value prediction for speculative multithreaded architectures", MICRO-32. PROCEEDINGS OF THE 32ND. ANNUAL ACM/IEEE INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE. HAIFA, ISRAEL, NOV. 16 - 18, 1999, PROCEEDINGS OF THE ANNUAL ACM/IEEE INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, LOS ALAMITOS, CA: IEEE COMP. SOC, US, 16 November 1999 (1999-11-16), pages 230 - 236, XP010364932, ISBN: 0-7695-0437-X *
SATHE R ET AL: "AVAILABLE PARALLELISM WITH DATA VALUE PREDICTION", PROCEEDINGS. INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING, XX, XX, 17 December 1998 (1998-12-17), pages 194 - 201, XP001001139 *

Also Published As

Publication number Publication date
AU2001268121A1 (en) 2001-12-11
US20030079116A1 (en) 2003-04-24
US20060149945A1 (en) 2006-07-06
US7051192B2 (en) 2006-05-23
WO2001093029A2 (en) 2001-12-06
US7366880B2 (en) 2008-04-29

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