WO2001089091A3 - Method and apparatus for incorporating a multiplier into an fpga - Google Patents

Method and apparatus for incorporating a multiplier into an fpga Download PDF

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Publication number
WO2001089091A3
WO2001089091A3 PCT/US2001/014259 US0114259W WO0189091A3 WO 2001089091 A3 WO2001089091 A3 WO 2001089091A3 US 0114259 W US0114259 W US 0114259W WO 0189091 A3 WO0189091 A3 WO 0189091A3
Authority
WO
WIPO (PCT)
Prior art keywords
function
multiplier
product
ports coupled
output data
Prior art date
Application number
PCT/US2001/014259
Other languages
French (fr)
Other versions
WO2001089091A2 (en
Inventor
Bernard J New
Steven P Young
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Priority to CA2409161A priority Critical patent/CA2409161C/en
Priority to DE60140674T priority patent/DE60140674D1/en
Priority to EP01932925A priority patent/EP1303912B1/en
Priority to JP2001585404A priority patent/JP4593866B2/en
Publication of WO2001089091A2 publication Critical patent/WO2001089091A2/en
Publication of WO2001089091A3 publication Critical patent/WO2001089091A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17732—Macroblocks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only

Abstract

One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one embodiment, a multi-function tile includes a configurable, dual-ported RAM and a multiplier that share routing resources of the multi-function tile. The RAM includes first and second input ports coupled to first and second input data buses, respectively, and includes first and second output ports coupled to first and second output data buses, respectively. The multiplier includes first and second operand ports coupled to receive operands from the first and second input data buses, and in response thereto provides a product. In one embodiment, the most significant bits (MSBs) of the product are selectively provided to the first output data bus using bus multiplexer logic, and the least significant bits (LSBs) of the product are selectively provided to the second output data bus using bus multiplexer logic.
PCT/US2001/014259 2000-05-18 2001-05-02 Method and apparatus for incorporating a multiplier into an fpga WO2001089091A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CA2409161A CA2409161C (en) 2000-05-18 2001-05-02 Method and apparatus for incorporating a multiplier into an fpga
DE60140674T DE60140674D1 (en) 2000-05-18 2001-05-02 METHOD AND DEVICE FOR INSERTING A MULTIPLIER IN A USER PROGRAMMABLE GATE FRAME
EP01932925A EP1303912B1 (en) 2000-05-18 2001-05-02 Method and apparatus for incorporating a multiplier into an fpga
JP2001585404A JP4593866B2 (en) 2000-05-18 2001-05-02 Method and apparatus for incorporating a multiplier into an FPGA

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/574,714 US6362650B1 (en) 2000-05-18 2000-05-18 Method and apparatus for incorporating a multiplier into an FPGA
US09/574,714 2000-05-18

Publications (2)

Publication Number Publication Date
WO2001089091A2 WO2001089091A2 (en) 2001-11-22
WO2001089091A3 true WO2001089091A3 (en) 2002-09-26

Family

ID=24297308

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/014259 WO2001089091A2 (en) 2000-05-18 2001-05-02 Method and apparatus for incorporating a multiplier into an fpga

Country Status (6)

Country Link
US (2) US6362650B1 (en)
EP (1) EP1303912B1 (en)
JP (1) JP4593866B2 (en)
CA (1) CA2409161C (en)
DE (1) DE60140674D1 (en)
WO (1) WO2001089091A2 (en)

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US20020057104A1 (en) 2002-05-16
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CA2409161A1 (en) 2001-11-22
CA2409161C (en) 2010-07-13
WO2001089091A2 (en) 2001-11-22
JP2003533931A (en) 2003-11-11
US6362650B1 (en) 2002-03-26
JP4593866B2 (en) 2010-12-08
US6573749B2 (en) 2003-06-03
EP1303912A2 (en) 2003-04-23

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