WO2001081994A1 - Dispositif electro-optique, affichage par projection et procede de fabrication dudit dispositif electro-optique - Google Patents
Dispositif electro-optique, affichage par projection et procede de fabrication dudit dispositif electro-optique Download PDFInfo
- Publication number
- WO2001081994A1 WO2001081994A1 PCT/JP2001/003359 JP0103359W WO0181994A1 WO 2001081994 A1 WO2001081994 A1 WO 2001081994A1 JP 0103359 W JP0103359 W JP 0103359W WO 0181994 A1 WO0181994 A1 WO 0181994A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- light
- film
- shielding film
- shielding
- electro
- Prior art date
Links
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Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133345—Insulating layers
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133553—Reflecting elements
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
Definitions
- Electro-optical device projection display device, and method of manufacturing electro-optical device
- the present invention relates to an electro-optical device of an active matrix drive system, a projection display device including the same, and a technical field of a manufacturing method for manufacturing the same. More specifically, an electro-optical device in which a thin film transistor for pixel switching (hereinafter referred to as TFT as appropriate) is provided in a laminated structure on a substrate, and the electro-optical device is provided as a light valve.
- TFT thin film transistor for pixel switching
- the present invention relates to a technical field of a projection display device and a manufacturing method for manufacturing such an electro-optical device. Background art
- an electro-optical device of the TFT active matrix drive type when incident light is applied to the channel region of the pixel switching TFT provided for each pixel, light leakage current is generated by excitation by light, and the characteristics of the TFT change. I do.
- a light-shielding film that defines an opening area of each pixel provided on a counter substrate or a device that passes over a TFT on a TFT array substrate and is made of a metal film such as A1 (aluminum) is used.
- the line is configured to shield the relevant channel region and its peripheral region from light.
- a light-shielding film made of, for example, a refractory metal may be provided at a position on the TFT array substrate facing the TFT below the TFT. If a light-shielding film is also provided below the TFT as described above, the light reflected on the back surface from the TFT array substrate side or a combination of a plurality of electro-optical devices via a prism or the like constitutes one optical system. It is possible to prevent return light such as projection light that penetrates a prism or the like from another electro-optical device from being incident on the TFT of the electro-optical device.
- Such an electro-optical device has a high light-shielding performance, and is therefore used as, for example, a light valve of a projection display device to which relatively strong projection light is incident. Disclosure of the invention
- a space between the light-shielding film and the channel region is three-dimensionally viewed, for example, via a liquid crystal layer, an electrode, an interlayer insulating film, or the like. They are far apart from each other, and the light obliquely incident between them is not sufficiently shielded.
- the incident light is a light beam obtained by focusing light from a light source with a lens, and components obliquely incident cannot be neglected (for example, when the light is applied to a substrate). (Approximately 10% includes a component tilted by about 10 to 15 degrees from the vertical direction.) It is a practical problem that the shading for such obliquely incident light is not sufficient.
- the reflected light or the multiple reflected light that is further reflected on the upper surface of the substrate or the inner surface of the light-shielding film may eventually reach the channel region of the TFT.
- the electro-optical device becomes more precise or the pixel pitch becomes finer in line with the general demand for higher quality display images in recent years, the light intensity of incident light is increased to display brighter images. Accordingly, according to the above-described conventional various light-shielding technologies, it becomes more difficult to provide sufficient light-shielding, and a change in the transistor characteristics of the TFT causes fringe force and the like, thereby degrading the quality of the displayed image. There is a problem that it decreases.
- the light-shielding film In order to improve such light resistance, it may be possible to increase the area in which the light-shielding film is formed. However, if the area in which the light-shielding film is formed is increased, the brightness of the displayed image is improved. This raises a problem that it is fundamentally difficult to increase the aperture ratio of each pixel. Furthermore, as described above, the presence of the light-shielding film on the lower side of the TFT and the light-shielding film on the upper side of the TFT, which consists of the light-shielding line, etc., as described above, causes internal reflection and multiple reflected light due to oblique light. If the area where the light-shielding film is formed is widened, there is a problem that it is difficult to solve such an increase in the internal reflected light and the multiple reflected light.
- An object of the present invention is to provide an electro-optical device capable of displaying a bright and high-quality image, a projection display device having the same, and a manufacturing method for manufacturing the electro-optical device.
- the first light-shielding film is formed as a light-shielding sidewall up to a position surrounding the channel region on the side.
- the first light shielding film formed on the upper layer side of the TFT channel region prevents light incident from the upper layer side of the first substrate from entering the channel region. . Further, since the first light-shielding film is formed as a light-shielding side wall to a position surrounding the channel region on the side, it is necessary to prevent light from entering the channel region from an oblique direction or a lateral direction. Can be. Therefore, according to the present invention, it is possible to reliably prevent light incident from the upper layer side of the first substrate from entering the channel region of the TFT, and to prevent malfunction of the TFT caused by such light. A decrease in reliability can be reliably prevented. In one embodiment of the first electro-optical device of the present invention, the electro-optical device further includes: a second ′ substrate opposed to the first substrate; and an electro-optical material sandwiched between the first and second substrates. Prepare.
- an electro-optical device such as a liquid crystal device having excellent light resistance and having an electro-optical material such as a liquid crystal sandwiched between a pair of substrates.
- the pixel electrodes and the thin film transistors are arranged in a matrix on the first substrate. According to this aspect, it is possible to construct an electro-optical device such as a liquid crystal device which is excellent in light resistance and is driven by an active matrix.
- the light-shielding side wall is formed, for example, in a sidewall-forming groove formed in an insulating film located below the first light-shielding film.
- the first light-shielding film is formed.
- the first electro-optical device having such a configuration can be manufactured by the following method. That is, an electro-optical device including a first substrate, a pixel electrode disposed on the first substrate, and a TFT disposed on the first substrate and connected to the pixel electrode.
- an electro-optical device for manufacturing a device after forming the TFT on a surface side of the first substrate on which a gate electrode is opposed via a gate insulating film on an upper layer side of a channel region, Forming at least one interlayer insulating film covering the TFT, forming a sidewall forming groove in the interlayer insulating film that passes through a side of the channel region of the TFT, and then forming at least one TFT of the TFT.
- a first light-shielding film that covers the channel region is formed, and when the first light-shielding film is formed, the first light-shielding film is also formed as a light-shielding sidewall in the sidewall forming groove.
- a drain electrode formed on an upper layer side of the drain region is electrically connected to a drain region of the TFT, and the drain electrode is connected to the drain electrode.
- the pixel electrode formed on the upper layer side is electrically connected, and the drain electrode is formed of a light-shielding conductive film formed so as to cover the channel region on the upper layer side.
- the drain electrode and the first light-shielding film may form a storage capacitor by using an insulating film formed between the drain electrode and the first light-shielding film as a dielectric film. preferable.
- both the drain electrode and the first light-shielding film are formed in a wide area covering the channel region. Therefore, if the insulating film formed between them is used as a dielectric film. A storage capacity can be configured. Therefore, since it is not necessary to separately pass a capacitor line to each pixel, the pixel aperture ratio can be improved.
- the source region of the TFT is
- a data line formed on an upper layer side of the source region is electrically connected to the data line;
- the line is formed of a light-shielding conductive film formed so as to cover the channel region on the upper layer side.
- the TFT active layer is formed of a semiconductor film formed below the data line and inside the formation region of the data line.
- the entire semiconductor film forming the TFT can be shielded from light by a light-shielding data line, and the TFT can be formed in the data line formation region, so that the pixel drop rate can be increased. .
- the data lines are linearly extended with equal width dimensions.
- a second light-shielding film overlapping the channel region is formed below the channel region.
- the first light-shielding film is electrically connected to the second light-shielding film via the sidewall-forming groove.
- the TT channel region can be entirely surrounded by the first light-shielding film, the light-shielding side wall, and the second light-shielding film, so that light from any direction can be surely shielded.
- the first light-shielding film and the second light-shielding film are electrically connected, for example, if the potential of the second light-shielding film is fixed, the potential of the first light-shielding film can be fixed. . Therefore, the first light-shielding film can be easily used as the fixed potential side capacitor electrode of the storage capacitor.
- the first light shielding film may be directly connected to the second light shielding film, or may be connected to the second light shielding film via another light shielding conductive film. You may.
- the gate electrode is formed on the bottom side in the side wall forming groove.
- a conductive film made of the same material as the conductive film may be formed, and the light-shielding side wall may be formed on the conductive film.
- a conductive film for forming a gate electrode is also formed in the connection groove.
- the side wall forming groove is formed in communication with the connection groove and integrated with the connection groove, Thereafter, when forming the first light-shielding film and forming the first light-shielding film, the first light-shielding film is also formed in the sidewall forming groove, and the first light-shielding film is formed in the sidewall forming groove.
- the light shielding side wall connected to the conductive film is formed.
- the first light-shielding film may be formed up to the bottom in the sidewall forming groove.
- a second light-shielding film is formed on the surface side of the first substrate.
- the second light shielding film reaches the second light shielding film through a side of the channel region of the thin film transistor with respect to the interlayer insulating film, the gate insulating film, and the base insulating film.
- the side wall forming groove Forming the side wall forming groove Thereafter, when forming the first light-shielding film and forming the first light-shielding film, the first light-shielding film is also formed in the sidewall-forming groove, and the first light-shielding film is formed in the sidewall-forming groove.
- the light-shielding side wall connected to the second light-shielding film is formed.
- the second electro-optical device of the present invention includes, on a substrate, a pixel electrode, a thin film transistor connected to the pixel electrode, a wiring connected to the thin film transistor, and the thin film transistor and the wiring. And a light shielding member for covering three-dimensionally.
- the second electro-optical device of the present invention by performing switching control of the pixel electrode by the thin film transistor connected thereto, it is possible to drive the pixel electrode by the active matrix driving method. Then, the light shielding member three-dimensionally covers the thin film transistor. Therefore, incident light traveling vertically or obliquely from above with respect to the substrate surface, return light incident perpendicularly or obliquely from below with respect to the substrate surface, and internally reflected light and multi-reflected light based on these light beams.
- the light blocking member can prevent the light from entering the channel region and the channel adjacent region of the thin film transistor.
- the non-opening area of each pixel can be precisely defined in a lattice shape by the light shielding member.
- the second electro-optical device of the present invention the light resistance can be improved, and the light leakage current can be reduced even under severe conditions where strong incident light or return light is incident.
- the pixel electrode can be satisfactorily switched by the thin film transistor thus formed, and finally, a bright and high-contrast image can be displayed by the present invention.
- the term “light-shielding member that three-dimensionally covers the thin film transistor and the wiring” in the present invention refers to a space in which the thin film transistor and the wiring are three-dimensionally closed in a narrow sense. In a broader sense, it means that the thin film transistor and the wiring are slightly interrupted inside, as long as the light coming from different directions in three dimensions is shielded (reflected or absorbed) to some extent. Or, it means a light shielding member that intermittently defines a three-dimensionally closed space.
- the light-shielding member is formed on a bottom surface of a groove dug on the substrate and accommodating the thin film transistor and the wiring therein. And one light-shielding film formed on the side wall, and another light-shielding film covering the groove from above.
- the groove is dug in the substrate, and one light-shielding film is formed on the bottom surface and the side wall of the groove.
- the thin film transistor and the wiring are accommodated in the groove while being mutually insulated from each other or from one light shielding film by, for example, an interlayer insulating film or the like.
- This groove is covered from above with another light-shielding film. Therefore, the thin film transistor and the wiring can be three-dimensionally shielded with certainty while employing a relatively simple configuration and manufacturing process.
- the light-shielding member includes a lower light-shielding film formed on the substrate, the thin-film transistor formed on the lower light-shielding film, and the light-shielding member.
- the thin film transistor and the wiring are arranged between the lower light-shielding film and the upper light-shielding film while being mutually insulated from each other by, for example, an interlayer insulating film or the like and from the lower and upper light-shielding films. .
- a moat from the upper light-shielding film to the lower light-shielding film is dug on the outer side of the thin film transistor and the wiring, for example, in an interlayer insulating film, and the moat is filled with a sidewall light-shielding film. Therefore, the thin-film transistor and the wiring can be reliably three-dimensionally shielded while employing a relatively simple configuration and manufacturing process.
- the light-shielding member may be formed in one plane region, wherein the light-shielding member is formed on the substrate and has a bottom surface of a groove in which the thin-film transistor and the wiring are accommodated.
- a relatively wide groove is dug in the substrate,
- One light shielding film is formed on the bottom and side walls of the groove.
- the thin film transistor and the wiring are accommodated in the groove while being mutually insulated from each other by, for example, an interlayer insulating film or the like from one light shielding film.
- This groove is covered from above with another light-shielding film.
- the thin film transistor and the wiring are arranged between the lower light-shielding film and the upper light-shielding film while being mutually insulated by, for example, an interlayer insulating film or the like, or interlayer-insulated from the lower and upper light-shielding films. ing.
- a relatively narrow moat from the upper light-shielding film to the lower light-shielding film is dug in, for example, an interlayer insulating film, and a side wall light-shielding film is formed in the moat. Is filled. Therefore, the thin film transistor and the wiring can be reliably three-dimensionally shielded while employing a relatively simple configuration and manufacturing process. In particular, by changing the configuration of the light shielding member for each region, the degree of freedom in device design is increased.
- the light shielding member is dug on the substrate and the thin film transistor A light-shielding film formed on the bottom and side walls of the trench in which the wiring and the wiring are partially accommodated, and a thin-film transistor formed on the one light-shielding film and formed on the wiring.
- the thin film transistor and the wiring are partially accommodated in the groove. That is, the thin film transistors and the wirings are mutually separated by, for example, an interlayer insulating film or the like, so that a part of the thin film transistor and the wiring are higher than the height of the edge of the groove with respect to the substrate. While being arranged in the groove. Further, an upper light-shielding film is arranged above the thin film transistors and the wiring partially accommodated in the groove. Outside the thin film transistor and the wiring, a relatively narrow moat from the upper light-shielding film to one light-shielding film is dug, and the inside of the moat is filled with a side wall light-shielding film.
- the thin film transistor and the wiring can be reliably three-dimensionally shielded from light.
- a light shielding member by combining a plurality of light shielding films, the degree of freedom in device design is increased.
- a third electro-optical device includes an electro-optical material sandwiched between a pair of first and second substrates, and the first electro-optical device is inverted on the first substrate in a first period.
- a light-shielding member that protrudes a portion of a region located between adjacent pixel electrodes included in different pixel electrode groups in a region serving as the gap into a convex shape, and the plurality of pixel electrodes are provided on the second substrate. And a counter electrode facing the counter electrode.
- the pixel electrode can be driven by the active matrix driving method by controlling the switching by the thin film transistor connected to the pixel electrode.
- the driving voltage in each pixel is increased.
- a so-called line inversion driving method such as a scanning line inversion driving method in which the polarity of each pixel is inverted for each scanning line, a data line inversion driving method in which each data line is inverted, and a dot inversion driving method in which each pixel is inverted. The method can be performed.
- Adopting the line inversion drive method in this way helps to prevent the deterioration of the electro-optical material due to the application of a DC voltage, and also prevents crosstalk and free force in the displayed image.
- the light-blocking member three-dimensionally covers the thin film transistor and the wiring in a region serving as a gap between the pixel electrodes adjacent to each other when viewed two-dimensionally. Therefore, incident light traveling vertically or obliquely from above with respect to the substrate surface, return light incident perpendicularly or obliquely from below with respect to the substrate surface, and internally reflected light and multiple reflected light based on these. Can be prevented from entering the channel region and the channel adjacent region of the thin film transistor by the light shielding member.
- a light-blocking member allows the non-opening area of each pixel Can be specified.
- the light-shielding member protrudes a portion of a region located between adjacent pixel electrodes included in different pixel electrode groups in a convex shape. Therefore, when the above-described line inversion driving is performed, the horizontal electric field generated between adjacent pixel electrodes having different driving potential polarities can be relatively weakened. That is, in an electro-optical device that is generally assumed to be driven by a vertical electric field generated between each pixel electrode and a counter electrode, when a horizontal electric field is generated between adjacent pixel electrodes, for example, the alignment of liquid crystal An abnormal operation of the electro-optical material, such as a defect, is caused.
- the vertical electric field in this region can be strengthened. Therefore, the adverse effect of the lateral electric field can be reduced.
- the light resistance can be improved, and the light leakage current can be reduced even under severe conditions where strong incident light or return light is incident.
- the pixel electrode can be satisfactorily controlled by the thin film transistor, and the lifetime of the electro-optical material can be increased. Thus, a bright and high contrast image can be displayed.
- the light shielding member is included in the same pixel electrode group, and is dug on the substrate in a region located between adjacent pixel electrodes. And a light-shielding film formed on a bottom surface and a side wall of the groove in which the thin film transistor and the wiring are housed, and another light-shielding film covering the groove from above, and are included in the different pixel electrode group.
- a wide groove is dug in the first substrate, and a light shielding film is formed on the bottom and side walls of the groove.
- the thin film transistor and the wiring are accommodated in the groove while being insulated from each other or from one light shielding film by, for example, an interlayer insulating film.
- the groove is covered from above with another light-shielding film.
- a thin film transistor and a wiring are provided between the lower light-shielding film and the upper light-shielding film, for example, by an interlayer insulating film, etc. It is arranged while being insulated from the interlayer.
- it may be configured such that a flattening process is performed on a base of the pixel electrode in a region portion located between adjacent pixel electrodes included in the same pixel electrode group.
- the flattening process is performed on the base of the pixel electrode.
- a planarization process is performed by a CMP (Chemical Mechanical Polishing) process, a spin coating process, or by adjusting a depth of a groove for accommodating a thin film transistor and a wiring. I have.
- operation failure of the electro-optical material such as poor alignment of liquid crystal due to a step on the underlying surface of the pixel electrode in contact with the electro-optical material can be reduced as much as possible.
- the light-shielding member in the second or third electro-optical device of the present invention includes a side wall light-shielding film
- the upper light-shielding film and the side wall light-shielding film may be formed integrally.
- a highly reliable light shielding member can be constructed.
- a moat may be dug in an interlayer insulating film formed before and after a thin film transistor and a wiring, and then an upper light-shielding film may be formed thereon.
- the pixel electrode and the thin film transistor are connected via a light-shielding conductive film.
- a contact hole is opened, and the inside is surrounded by a light-blocking member.
- the pixel electrode and the thin-film transistor are apt to leak light from the outside to the space. Leakage can be reliably prevented.
- a connecting portion between the pixel electrode and the thin film transistor is located at the center of the thin film transistor adjacent to each other when viewed two-dimensionally.
- the electro-optical device further includes a light-shielding film formed facing the substrate and facing a connection portion between the pixel electrode and the thin film transistor.
- a contact hole is formed, and light leakage at a connection point between the pixel electrode and the thin film transistor that easily causes light leakage from the outside to an internal space surrounded by the light shielding member is prevented. Can be reliably prevented.
- the light shielding member is made of a film containing a high melting point metal.
- the light-shielding member has a high melting point such as, for example, Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), Mo (molybdenum), and Pb (lead). It is composed of a film containing a high melting point metal such as a simple substance of a metal, an alloy, a metal silicide, a polysilicide, or a laminate of at least one of the metals. Therefore, good high light shielding performance can be obtained by the light shielding member.
- the wiring includes scanning lines and data lines that intersect with each other, and the light blocking member is formed in a lattice shape when viewed in plan.
- the scanning lines and the data lines intersect and are wired in a grid, but these are completely three-dimensionally formed by the grid-shaped light shielding member. Covered. For this reason, it is possible to reduce the possibility that light leaks into the thin film transistor connected to the scanning line and the data line near the data line.
- the storage device is disposed on the first substrate in a space three-dimensionally covered by the light shielding member and connected to the pixel electrode. Further comprising a capacity.
- the storage capacitor is constructed in the space three-dimensionally covered by the light blocking member, the storage capacitor is added to the pixel electrode while preventing the light blocking performance from being reduced due to the presence of the storage capacitor. As a result, the potential holding characteristics of the pixel electrode can be significantly improved.
- a projection display device of the present invention includes a light valve including the above-described first, second, or third electro-optical device of the present invention (including its various aspects); A light source for irradiating the projection valve with projection light; and an optical system for projecting projection light emitted from the light valve.
- the light source irradiates the projection light to the light valve, and the projection light emitted from the light valve is projected on a screen or the like by the optical system.
- the light valve includes the first, second, or third electro-optical device of the present invention described above, even if the intensity of the projected light is increased, the light leakage current is reduced by the excellent light shielding performance as described above.
- the pixel electrodes can be satisfactorily controlled by the thin film transistors thus formed. As a result, a bright, high-contrast image can be finally displayed.
- FIG. 1 is an equivalent circuit diagram of various elements and wirings arranged in a matrix and formed in a plurality of pixels in the electro-optical device according to the first embodiment of the present invention.
- FIG. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which a data line, a scanning line, a pixel electrode, a light-shielding film, and the like are formed in the electro-optical device shown in FIG.
- FIG. 3 is an enlarged view showing a pixel electrode formation region on the TT array substrate shown in FIG.
- FIG. 4 is an enlarged view showing a region where a scanning line is formed on the TFT array substrate shown in FIG.
- FIG. 5 is an enlarged view showing a formation region of a semiconductor film for TFT formation on the TFT array substrate shown in FIG.
- FIG. 6 is a cross-sectional view at a position corresponding to the line A— ⁇ ′, line B—B ′, and line C—C ′ in FIG.
- FIG. 7 is an enlarged view showing a drain electrode formation region in the TF array substrate shown in FIG.
- FIG. 8 is an enlarged view showing a region where a first light-shielding film and a sidewall forming groove are formed in the TF array substrate shown in FIG.
- FIG. 9 is an enlarged view showing a region where a first light-shielding film and a sidewall forming groove are formed in the TF array substrate shown in FIG.
- FIG. 10 is a process sectional view illustrating the method for manufacturing the TFT array shown in FIG.
- FIG. 11 is a process cross-sectional view of each process performed after the process shown in FIG. 10 in the method of manufacturing the TFT array shown in FIG.
- FIG. 12 is a process cross-sectional view of each process performed after the process shown in FIG. 11 in the method of manufacturing the TF array shown in FIG.
- FIG. 13 is a process cross-sectional view of each process performed after the process shown in FIG. 12 in the method of manufacturing the TFT array shown in FIG.
- FIG. 14 is a cross-sectional view of each step performed after the step shown in FIG. 13 in the method of manufacturing the TF array shown in FIG.
- FIG. 15 is a cross-sectional view of each step performed after the step shown in FIG. 14 in the method of manufacturing the TFT array shown in FIG.
- FIG. 16 is a cross-sectional view of each step performed after the step shown in FIG. 15 in the method of manufacturing the TF array shown in FIG.
- FIG. 17 is a sectional view of an electro-optical device according to a second embodiment of the present invention.
- FIG. 18 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which a data line, a scanning line, a pixel electrode, and the like are formed in the electro-optical device according to the third embodiment.
- FIG. 19 is a sectional view taken along line DD of FIG.
- FIG. 20 is a sectional view taken along the line E--E of FIG.
- FIG. 21 is a sectional view of a portion corresponding to E—E in FIG. 18 in the fourth embodiment of the present invention.
- FIG. 22 is a cross-sectional view of a portion corresponding to E_E ′ in FIG. 18 in the fifth embodiment of the present invention.
- FIG. 23 is a schematic diagram of a plurality of pixel electrodes showing the relationship between the polarity of the driving voltage at each pixel electrode and the region where a lateral electric field is generated during scanning line inversion driving in the electro-optical device according to the sixth embodiment of the present invention.
- FIG. 23 is a schematic diagram of a plurality of pixel electrodes showing the relationship between the polarity of the driving voltage at each pixel electrode and the region where a lateral electric field is generated during scanning line inversion driving in the electro-optical device according to the sixth embodiment of the present invention.
- FIG. 24 is a plan view of the electro-optical device when viewed from the side of the opposing board.
- FIG. 25 is a sectional view taken along the line H—H ′ of FIG.
- FIG. 26 is a block diagram showing a circuit configuration of a projection display device as an example of an electronic apparatus using the electro-optical device according to the present invention as a display device.
- FIG. 27 is a cross-sectional view illustrating a configuration of an optical system of a projection electro-optical device as an example of an electronic apparatus using the electro-optical device according to the invention.
- the electro-optical device of the present invention is applied to a liquid crystal device.
- FIG. 1 is an equivalent circuit diagram of various elements, wiring, and the like in a plurality of pixels formed in a matrix, which form an image display area of an electro-optical device.
- FIG. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, light shielding films, and the like are formed.
- FIG. 3 is an enlarged view showing a pixel electrode formation region on the TFT array substrate.
- FIG. 4 is an enlarged view showing an area where the scanning lines and data lines are formed on the TFT array substrate.
- FIG. 5 is an enlarged view showing a formation region of a semiconductor film for forming a TFT on the TFT array substrate.
- FIG. 6 is a cross-sectional view at a position corresponding to the line AA ′, the line BB ′, and the line C-C ′ in FIG.
- FIG. 7 is an enlarged view showing a region where a drain electrode is formed in the TFT array substrate.
- Figure 8 shows this! It is expanding the large diagram showing the formation region of the first light-blocking film and the side wall forming grooves in 1 T array substrate.
- FIG. 9 is an enlarged view showing a region where the first light-shielding film and the side wall forming groove are formed in the TFT array substrate.
- each layer and each member are made to have a size that can be recognized on the drawing. However, the scale is different for each layer and each member.
- a TFT 30 for pixel switching for controlling the pixel electrode 9a is formed in each of a plurality of pixels formed in a matrix.
- the pixel line 6a for supplying pixel signals is electrically connected to the source of the TFT 30.
- the pixel signals S l, S 2, S n to be written to the data line 6 a may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 6 a. Then, the supply may be made for each group.
- the scanning line 3 a is electrically connected to the gate of the TFT 30, and the scanning signals G 1, G 2-Gm are pulsed to the scanning line 3 a at a predetermined timing.
- the pixel electrode 9a is electrically connected to the drain of the TFT 3, and by turning on the TFT 30 as a switching element for a certain period of time, Write the pixel signals S1, S2,..., Sn supplied from the data line 6a to each pixel at a predetermined timing.
- the predetermined-level pixel signals S l, S 2,... * S n written to the electro-optical material via the pixel electrode 9 a in this manner are supplied to a counter electrode formed on a counter substrate to be described later. For a certain period.
- the electro-optic material modulates the light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling a gradation display.
- the transmittance for the incident light decreases according to the applied voltage.
- the transmittance for the incident light increases according to the applied voltage.
- Light having a contrast corresponding to the pixel signal is emitted from the electro-optical device.
- a storage capacitor 70 may be added in parallel with the liquid crystal capacitor formed between the pixel electrode 9 and the counter electrode.
- the voltage of the pixel electrode 9a is held by the storage capacitor 70 for a time that is three orders of magnitude longer than the time when the source voltage is applied.
- the charge retention characteristics are improved, and an electro-optical device 100 having a high contrast ratio can be realized.
- a plurality of transparent pixel electrodes 9a are formed in a matrix on the TFT array substrate of the electro-optical device for each pixel.
- the area where the pixel electrode 9a is formed is a rectangular area hatched to the right in the enlarged view shown in FIG.
- a data line 6a and a scanning line 3a are formed along the vertical and horizontal boundary regions of the pixel electrode 9a, but unlike a conventional electro-optical device, a dedicated capacitance line is formed. Not.
- the formation region of the data line 6a is a region indicated by diagonally downward slanted lines in the enlarged view shown in FIG. 4, and both end portions of the data line 6a overlap the end portions of the pixel electrode 9a.
- the region where the scanning line 3a is formed is a region which is hatched in the enlarged view in FIG. 4, and both ends of the scanning line 3a also overlap with the end of the pixel electrode 9a.
- the policy line 6a is connected to the policy via the contact hole 5.
- the pixel electrode 9a is electrically connected to a source region described later in the semiconductor film 1a made of a recon film, and is connected to a drain region described later in the semiconductor film 1a through the contact holes 81 and 82. It is electrically connected to the area.
- the scanning line 3a (gate electrode) passes through the semiconductor film la so as to face a channel formation region described later.
- the formation region of the semiconductor film 1a is a region indicated by an oblique line rising to the right in the enlarged view shown in FIG.
- the data line 6a is made of a conductive film having a light shielding property, such as a metal film of aluminum or the like or an alloy film of metal silicide or the like linearly extended with the same width.
- the film la is formed on the lower layer side of the data line 6a and inside the formation region of the data line 6a. That is, the semiconductor film 1a is formed using the vertical and horizontal boundary regions of each pixel electrode 9a.
- the electro-optical device 100 includes a TFT array substrate 10 (first substrate) and an opposing substrate 20 (second substrate) that is arranged to face the TFT array substrate 10.
- the TFT array substrate 10 is made of, for example, a quartz substrate
- the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate.
- a pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film (not shown) on which a predetermined alignment process such as a rubbing process is performed is formed above the pixel electrode 9a.
- the pixel electrode 9a is made of, for example, a transparent conductive thin film such as an ITO film (indium tin oxide film).
- the alignment film is made of, for example, an organic thin film such as a polyimide thin film.
- a TFT 30 for pixel switching for controlling switching of each pixel electrode 9a is formed directly below the data line 6a.
- the TFT 30 has an LDD (Lightly Drained Drain) structure, and a channel is formed by a scanning line 3a (gate electrode) and an electric field of a scanning signal supplied from the scanning line 3a.
- a corresponding one of the plurality of pixel electrodes 9a is electrically connected to the high-level drain region 1e.
- the source regions 1b and 1d and the drain regions 1c and 1e are determined according to whether an n-type channel or a p-type channel is formed in the semiconductor film 1a, as described later. It is formed by doping an n-type or p-type dopant at a concentration.
- the TFT of the n-type channel has an advantage of a high operation speed, and is often used as a TFT for pixel switching. ,
- the TFT 30 preferably has an LDD structure as described above, but has an offset structure in which impurity ions are not implanted into regions corresponding to the low-concentration source region 1b and the low-concentration drain region 1c. It may be.
- the TFT 30 may be a self-aligned TFT in which impurity ions are implanted at a high concentration using the gate electrode 3a as a mask to form a high-concentration source and drain region in a self-aligned manner.
- the TFT 30 has a single-gate structure in which only one gate electrode (delay line 3a) is arranged between the source-drain regions 1b and 1e. Even if two or more gate electrodes are arranged in the ⁇ .
- the same signal is applied to each gate electrode.
- the TFT With configuring the TFT with a dual gate (double gate) or triple gate or more as described above, it is possible to prevent a leakage current at the junction between the channel and the source-drain region, and to reduce a current when the transistor is off. If at least one of these gate electrodes has an LDD structure or an offset structure, the off current can be further reduced, and a stable switching element can be obtained.
- the data line 6a (source electrode) is composed of a metal film of aluminum or the like / an alloy film of metal silicide or the like.
- the contact hole 5 leading to the high-concentration source region .. 1 d and the contact hole 8 leading to the high-concentration drain region 1 e are provided above the scanning line 3 a (gate electrode) and the gate insulating film 2.
- the first interlayer insulating film 4 on which each 1 is formed is formed.
- a second interlayer insulating film 7a is formed, and on the second interlayer insulating film 7a, a third interlayer insulating film 7b is formed.
- the data line 6 a (source electrode) is formed on the second interlayer insulating film 7 a through the contact hole 5 to the source region I d until the data line 6 a (source electrode) reaches the high concentration g source region 1 d. Is electrically connected to
- the pixel electrode 9a is formed on the third interlayer insulating film 7b. Therefore, in the present embodiment, in electrically connecting the pixel electrode 9a to the high-concentration drain region 1e of the TFT 30, the drain electrode 11 is formed on the surface of the first interlayer insulating film 4.
- the drain electrode 11 is electrically connected to the high-concentration drain region 1 e of the TFT 30 via the contact hole 81 of the first interlayer insulating film 4, and the second interlayer insulating film 7 A contact hole 82 is formed in a and the third interlayer insulating film 7b, and the pixel electrode 9a is electrically connected to the drain electrode 11 through the contact hole 82. Therefore, the pixel electrode 9 a is electrically connected to the high-concentration drain region 1 e of TFT 30 via the drain electrode 11.
- the drain electrode 11 is formed of a doped silicon film (polysilicon relay electrode) formed so as to completely cover the channel region 1a from the upper layer side of the high-concentration drain region 1e.
- the drain electrode 11 is formed of a light-shielding conductive film (see FIG. 2). As shown in FIG. In each of the pixels, a cross is formed for each pixel along the data line 6a and the scanning line 3a from the intersection of the data line 6a and the scanning line 3a.
- a thin insulating film 12 is formed on the surface side of the drain electrode 11, and an interlayer between the thin insulating film 12 and the second interlayer insulating film 7 a is formed.
- the first light-shielding film 13 is made of a light-shielding material such as titanium, chromium, tungsten, tantalum, molybdenum, palladium, aluminum, an alloy of these metals, a silicide film of these metals, or silicon dioxide. It is composed of a conductive film having a property.
- the formation region of the first light-shielding film 13 is shown by a hatched region falling to the right in FIG. 8, and the first light-shielding film 13 is formed by a grid along the vertical and horizontal boundary regions of each pixel electrode 9a. And is maintained at a common potential between the pixels.
- a drain electrode 11 is formed below the first light-shielding film 13, and the first light-shielding film 13 and the drain electrode 11 are interposed via a thin insulating film 12. They are opposed over a wide area. Therefore, in the present embodiment, a storage capacitor 70 is configured in which the thin insulating film 12 is used as a dielectric film, the first light-shielding film 13 and the drain electrode 11 are used as electrodes.
- a second light-shielding film is formed on the surface of the base so as to cover the channel region 1 a ′ of the TFT 30 from below. 14 is formed, and a base insulating film 15 is formed on the surface of the second light shielding film 14.
- the formation region of the second light-shielding film 14 is indicated by a hatched region on the lower right in FIG.
- a side wall forming groove 16 penetrating the thin insulating film 12 and the first interlayer insulating film 4 is formed so as to surround the channel region 1 a ′ of the TFT 30 on the side. .
- the side wall forming groove 16 is formed along the outer peripheral edge inside the region where the first light shielding film 13 is formed, and the side wall forming groove 16 is formed as shown in FIG.
- the first light-shielding film 13 is formed in an area with a lower right diagonal line with a smaller pitch than that of the first light-shielding film 13. I have.
- the side wall forming groove 16 communicates with a connection groove 16 1 penetrating the gate insulating film 2 and the base insulating film 15.
- the connection groove 16 1 is filled with a light-shielding conductive film 16 2 formed simultaneously with the scanning line 3 a (gate electrode), and the side wall formation groove 16 is formed simultaneously with the first light-shielding film 13.
- the light-shielding side wall 13 1 made of the formed light-shielding conductive film is filled.
- the upper part of the channel region 1a 'of the TFT 30 is shielded from light by the scanning line 3a, the drain electrode 11, the first light shielding film 13 and the data line 6a, and the lower part is formed by the second light shielding film.
- the light is shielded by 14 and the side is shielded by the light-shielding side wall 13 1 in the side wall forming groove 16 and the conductive film 16 2 in the connection groove 16 1.
- a counter electrode (common electrode) 21 is provided on the entire surface of the counter substrate 20, and a predetermined alignment process such as a rubbing process is performed below the counter electrode 20.
- An alignment film (not shown) is formed.
- Counter electrode 2 1 Also, for example, it is made of a transparent conductive thin film such as an IT0 film.
- the alignment film of the counter substrate 20 is also made of an organic thin film such as a polyimide thin film.
- the counter substrate-side light-shielding film 23 may be formed in a matrix shape in a region other than the opening region of each pixel.
- the incident light L1 from the side of the counter substrate 20 does not reach the channel region 1a 'and the LDD regions 1b and 1c of the semiconductor film 1a having a TF of 30.
- the opposing substrate-side light-shielding film 23 has functions such as improvement of contrast and prevention of color mixture of color materials.
- the TFT array substrate 10 and the opposing substrate 20 configured as described above are arranged so that the pixel electrode 9a and the opposing electrode 21 face each other, and a sealing material described later is provided between these substrates.
- the liquid crystal 50 as an electro-optical material is sealed in the space surrounded by and enclosed.
- the liquid crystal 50 assumes a predetermined alignment state by the alignment film in a state where no electric field is applied from the pixel electrode 9a.
- the liquid crystal 50 is made of, for example, a mixture of one or several kinds of nematic electro-optical materials.
- the sealing material is an adhesive made of a photo-curing resin or a thermosetting resin for bonding the TFT array substrate 10 and the opposing substrate 20 around the periphery thereof.
- a spacer such as glass fiber or glass beads for obtaining a predetermined value is mixed with a gap material.
- the scanning line 3 a and the drain electrode are disposed on the upper layer side of the channel region 1 a ′ and the LDD regions 1 b and 1 c of the TFT 30. Since the first light-shielding film 13 and the data line 6a are formed, strong light incident from the counter substrate 20 does not directly enter the channel region 1a.
- the second light-shielding film 14 since light is shielded by the second light-shielding film 14 below the channel region 1 a ′ and the LDD regions 1 b and 1 c of the TFT 30, the light reflected by the TFT array substrate 10 Alternatively, even if light reflected from optical components disposed outside the light enters the TFT array substrate 10 from the rear surface side, such light does not enter the channel region 1a.
- the electro-optical device 100 of the present embodiment is capable of transmitting light even when strong light is incident from the side of the counter substrate 20 as in a projection display device described later. It is possible to completely prevent the malfunction of the TFT 30 and a decrease in the reliability caused by the incidence on 1a '.
- the drain electrode 11 electrically connected to the pixel electrode 9a for each pixel and the first light-shielding film 13 common to the pixels are formed by a thin insulating film 12 They face each other over a wide area.
- the first light-shielding film 13 and the second light-shielding film 14 are electrically connected to each other via the light-shielding side wall 13 1 in the side wall forming groove 16 and the conductive film 16 2 in the connection groove 16 1.
- the storage capacitor 70 is constructed by using the domain electrode 11 and the first light shielding film 13 as a capacitor electrode and using the thin insulating film 12 as a dielectric film. Has formed. Therefore, it is not necessary to pass a dedicated capacitance line to each pixel, so that the pixel opening ratio can be improved.
- FIGS. 10 to 16 are process cross-sectional views illustrating a method of manufacturing the TFT array substrate 10 of the present embodiment.
- FIGS. 10 to 16 show the cross section at the position corresponding to the line A— ⁇ ′ in FIG. 2, the cross section at the position corresponding to the line ⁇ —B ′, and the line C—C ′ in FIG. The cross section at the corresponding position is shown.
- a TF array substrate 10 such as a quartz substrate or hard glass is prepared.
- TF ⁇ The array substrate 10 is annealed in an inert gas atmosphere such as ⁇ 2 (nitrogen) and at a high temperature of about 900 ° C. to about 130 ° C.
- ⁇ 2 nitrogen
- this tungsten silicide film 140 is formed. Then, patterning is performed as shown in FIG. 10B to form a second light-shielding film 14.
- TEOS tetraethyl orthosilicate
- TEB tetraethyl 'portrait
- TMOP Tetra'methyl.oxy.phosphate
- NSG non-silicate glass
- PSG lain silicate glass
- BSG boron silicate glass
- BPSG poly silicate glass
- a base insulating film 15 made of a silicate glass film, a silicon nitride film, a silicon oxide film, or the like is formed.
- the layer thickness of the base insulating film 15 is, for example, about 500 nm to about 2000 nm.
- a relatively low temperature environment of about 450 ° C. to about 550 ° C., preferably about 500 ° C. is formed on the base insulating film 15.
- amorphous silicon is obtained by decompression CVD (for example, CVD at a pressure of about 20 to 40 Pa) using monosilane gas, disilane gas, etc. at a flow rate of about 40 cc / min to about 600 cc / min.
- a film 1 a ⁇ is formed.
- annealing is performed in a nitrogen atmosphere at about 600 ° C. to about 700 ° C. for about 1 hour to about 10 hours, preferably for about 4 hours to about 6 hours.
- the polysilicon film 1 is solid-phase grown to a thickness of about 50 nm to about 200 nm, preferably about 100 nm, and the TFT 30 for pixel switching is a P-channel type.
- a dopant of a group V element such as Sb (antimony), As (arsenic), or P (phosphorus) may be slightly doped into the channel forming region by ion implantation or the like.
- a group III element dopant such as B (boron), Ga (gallium), and In (indium) is used. May be slightly doped by ion injection or the like.
- the polysilicon film 1 may be directly formed by a low-pressure CVD method or the like without passing through the amorphous silicon film.
- the polysilicon film 1 may be formed by implanting silicon ions into a polysilicon layer deposited by a low-pressure CVD method or the like to make the polysilicon film amorphous once (amorphization), and then recrystallize by annealing or the like. .
- a semiconductor film 1a having the pattern shown in FIGS. 2 and 5 is formed by photolithography, an etching process, and the like.
- the semiconductor film 1a constituting the TFT 30 is thermally oxidized by a temperature of about 900 ° C. to about 130 ° C., preferably about 100 ° C.
- a relatively thin thermal silicon oxide film 201 of about 30 nm is formed, and a high-temperature silicon oxide film 202 (HTO film) ⁇ silicon nitride film of about 50
- the gate insulating film 2 having a multilayer structure is formed by depositing a relatively thin thickness of nm.
- the gate insulating film 2 having a single-layer structure may be formed only by thermal oxidation. Note that the above-described ion implantation step may be performed after the gate insulating film 2 is formed.
- connection groove 16 1 reaching the second light-shielding film 14 is formed in the gate insulating film 2 and the base insulating film 15.
- phosphorus (P) is thermally diffused to make the polysilicon film 3 conductive.
- a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film 3 may be used.
- a scanning line 3a (gate electrode) having a pattern shown in FIGS. 2 and 4 is formed by a photolithography process using a resist mask, an etching process, and the like.
- the layer thickness of the scanning line 3a is, for example, about 350 nm.
- the connection groove 161 is filled with a conductive film 162 of the same material as the scanning line 3a.
- the TFT 30 shown in FIG. 6 is an n-channel TFT having an LDD structure
- a low-concentration source is formed on the semiconductor film la.
- the scan line 3a (gate electrode) is used as a diffusion mask, and the V-group element dopant 200 such as P is doped at a low concentration (for example, At a dose of 1 ⁇ 10 13 / c ⁇ ! 2 to 3 ⁇ 10 13 / cm 2 ).
- the semiconductor film la below the scanning line 3a (gate electrode) becomes a channel forming region la '.
- the resistance of the scanning line 3a is also reduced by the doping of the impurity.
- the width is wider than the scanning line 3a (gate electrode).
- a dopant 201 of a group V element such as P is also concentrated at a high concentration (for example, P ions are 3 in X 1 0 1 5 / cm 2 of dose of) de are backing up.
- the above-mentioned n-channel TFT may have an offset structure without implanting a low concentration of impurities.
- a low-concentration source region 1b, a low-concentration drain region 1c, a high-concentration source region 1d, and a high-concentration drain region 1e are formed on the semiconductor film 1a.
- Doping is performed using a group III element such as B for forming.
- the TFT may have an offset structure without doping at a low concentration.
- the self-aligned TFT may be formed by an ion implantation technique using P ions, B ions, etc., using the scanning line 3a (gate electrode) as a mask. It is good. The resistance of the scanning line 3a is further reduced by the doping of the impurity.
- peripheral circuits such as a data line driving circuit and a scanning line driving circuit having a complementary structure composed of an n-channel TFT and a p-channel TT are mounted on the TFT array substrate 10. Formed in the periphery of.
- the pixel switching TFT 30 in this embodiment is a polysilicon TFT, the pixel switching TFT 30 is formed in substantially the same process when forming the pixel switching TFT 30 and the like. Peripheral circuits can be formed, which is advantageous in manufacturing.
- the scanning line 3a Silicate glass film of NSG, PSG, BSG, BPSG, etc., silicon nitride film, silicon oxide film, etc. using normal pressure or reduced pressure CVD method, TEOS gas, etc.
- a first interlayer insulating film 4 made of is formed.
- the layer thickness of the first interlayer insulating film 4 is preferably from about 500 nm to about 1500 nm.
- a contact hole 81 for connecting the high-concentration drain region 1 e of the TFT 30 to the drain electrode 11 is formed by reactive etching and reactive ion. It is formed by dry etching such as beam etching or by gateway etching.
- a polysilicon layer 110 for forming a drain electrode 11 is deposited on the surface of the first interlayer insulating film 4 by a low pressure CVD method or the like, the phosphorous is deposited.
- P is thermally diffused to make the polysilicon film 110 conductive.
- a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film 110 may be used.
- a drain electrode 11 having a pattern shown in FIGS. 2 and 7 is formed by a photolithography process using a resist mask, an etching step, and the like.
- a thin insulating film 12 is formed on the surface of the drain electrode 11.
- a light-shielding side wall 13 1 using the first light-shielding film 13 is formed on the insulating film 12 and the first interlayer insulating film 4.
- the side wall forming groove 16 is formed by dry etching such as reactive etching or reactive ion beam etching so as to communicate with the connecting groove 16 1, and includes the connecting groove 16 1 for forming an integral side wall.
- a groove 16 is formed.
- an evening-stencil film 130 for forming a first light-shielding film 13 on the surface of the insulating film 12 is, for example, 200 nm thick.
- the tungsten silicide film 130 is patterned as shown in FIG. 14B to form a first light-shielding film 13.
- the first light shielding film 13 is formed simultaneously with the first light shielding film 13.
- the light shielding side wall 13 1 is electrically connected to the bottom conductive film 16 2.
- a second interlayer insulating film 7a made of a film or the like is formed.
- the second interlayer insulating film ⁇ a preferably has a thickness of about 500, nm to about 150 O nm.
- the contact hole 5 with respect to the data line 3a is formed by dry etching such as reactive etching or reactive ion beam etching or by gate etching.
- a metal film 6 such as a low-resistance metal such as A1 or a metal silicide is formed on the second interlayer insulating layer 7a by sputtering or the like. Deposit to a thickness of about 100 nm to about 500 nm, preferably about 300 nm.
- a data line 6a (source electrode) is formed by a photolithographic process, an etching process and the like.
- the NSG is applied to cover the data line 6a (source electrode) using, for example, a normal pressure or reduced pressure CVD method or TEOS gas.
- a third interlayer insulating film 7b made of a silicate glass film such as PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed.
- the layer thickness of the third interlayer insulating film 7b is preferably about 50 O nm to about 150 O nm.
- a contact hole 82 for electrically connecting the pixel electrode 9a and the drain electrode 11 is formed by reactive etching, reactive ion beam etching, or the like. It is formed by dry etching.
- a transparent conductive thin film 9 such as an IT0 film is formed on the third interlayer insulating film 7b by a sputtering process or the like to a thickness of about 50 nm to about 2 nm. Deposit to a thickness of 0 0 ⁇ m. '
- the transparent conductive thin film 9 is patterned by an etching process or the like as in photolithography, thereby forming a pixel electrode 9a as shown in FIG.
- a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction. Thereby, an alignment film is formed.
- a glass substrate or the like is first prepared, and the counter substrate-side light shielding film 23 and the light shielding film 53 serving as a frame for separating the display area from the non-display area are provided.
- a metal chromium is sputtered, a photolithography is performed and an etching process is performed.
- the opposing substrate-side light-shielding film 23 and the light-shielding film 53 as a frame of the display screen are made of resin black in which carbon or Ti is dispersed in a photoresist in addition to metal materials such as Cr, Ni, and A1. And other materials.
- a transparent conductive thin film of ITO or the like is deposited on the entire surface of the opposing substrate 20 by a sputtering process or the like to a thickness of about 5 O nm to about 20 O nm, thereby forming the opposing electrode 21.
- a coating solution of a polyimide-based alignment film is applied to the entire surface of the counter electrode 21
- a rubbing process is performed in a predetermined direction so as to have a predetermined tilt angle and the like, so that the alignment film is formed. It is formed. 'As described above, the configuration of the opposing substrate 20 side of the electro-optical device 100 is completed. As can be seen from FIG.
- the TFT array substrate 10 and the opposing substrate 20 manufactured as described above have an alignment film. Are bonded to each other with a sealing material (not shown) so that they face each other, and an electro-optical material formed by mixing a plurality of types of nematic electro-optical materials, for example, is mixed in a space between both substrates by vacuum suction or the like.
- the liquid crystal 50 having a predetermined thickness is formed by suction.
- FIG. 17 is a sectional view of the electro-optical device 100 ′ of the second embodiment.
- the electro-optical device 100 ′ of the second embodiment is the same as the electro-optical device of the first embodiment.
- the step of forming the connection groove 16 1 described with reference to FIG. 11B is omitted, and the side wall forming groove 1 described with reference to FIG. 13D is omitted.
- the side wall forming groove 16 is formed so as to reach the second light shielding film 14.
- the other manufacturing steps are the same as in the first embodiment.
- the electro-optical device 100 of the second embodiment is another configuration example of the TFT array substrate 10 in the electro-optical device 100 of the first embodiment shown in FIG. Since it is as described with reference to FIG. 6, the corresponding parts are denoted by the same reference numerals and description thereof will be omitted.
- FIG. 18 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in the third embodiment.
- FIG. 19 is a cross-sectional view taken along the line DD ′ of FIG. 18, and
- FIG. 20 is a cross-sectional view taken along the line E-E ′ of FIG. 18 relating to the laminated body formed on the TFT array substrate 10.
- the scale of each layer and each member is different so that each layer and each member have a size recognizable in the drawings.
- FIGS. 18 to 20 according to the third embodiment the same components as those in the first embodiment shown in FIGS. 1 to 9 are denoted by the same reference numerals, and the description thereof will be appropriately omitted. .
- the electro-optical device of the third embodiment has the same basic circuit configuration as the electro-optical device of the first embodiment shown in FIG.
- the second light-shielding film 14 has a function as a phantom line for lowering the fixed-potential-side capacitance electrode of the storage capacitor 70 to a fixed potential.
- a capacitor line is provided so as to overlap with the scanning line 3a and along the scanning line 3a.
- a capacitance line 300 is provided. More specifically, the capacitance line 300 extends in a stripe shape along the scanning line 3a in a plan view, and the portion overlapping the TFT 30 projects vertically in FIG. As a result, the area where the storage capacitor 70 is formed is increased by using the area above the scanning line 3a and the area below the data line 6a.
- the storage capacitor 70 serves as a pixel potential side capacitor electrode connected to the high-concentration drain region 1 e and the pixel electrode 9 a of the TFT 30.
- the relay layer 71 and a part of the capacitance line 300 as the fixed-potential-side capacitance electrode are formed so as to face each other with the dielectric film 75 interposed therebetween.
- the capacitance line 300 is made of, for example, a conductive film containing a metal or an alloy, and also functions as a fixed potential side capacitance electrode.
- the capacitance line 300 includes, for example, at least one of refractory metals such as Ti, Cr, W, Ta, ⁇ , ⁇ b, etc. , Polysilicide, and a laminate of these.
- the capacitance line 300 may have a multilayer structure in which, for example, a first film made of a conductive polysilicon film or the like and a second film made of a metal silicide film containing a refractory metal are stacked. Good.
- the relay layer 71 is made of, for example, a conductive polysilicon film and functions as a pixel potential side capacitance electrode.
- the relay layer 71 has a function of relay connection between the pixel electrode 9a and the high-concentration drain region 1e of the TFT 30 in addition to a function as a pixel potential side capacitor electrode.
- the relay layer 71 may be formed of a single-layer film or a multi-layer film containing a metal or an alloy, similarly to the capacitance line 300.
- a groove 10 cV is dug in the TT array substrate 10 in the lattice-shaped region indicated by the coarsely hatched region falling to the right in FIG.
- a lower light-shielding film 400 is provided in a lattice shape in the groove 100 cV.
- the lower light-shielding film 400 like the capacitance line 300, includes at least one of refractory metals such as, for example, Ti, CrW, Ta, Mo, and Pb. It consists of a metal alone, an alloy, a metal silicide, a polysilicide, and a laminate of these.
- the upper light-shielding film 401 is the same as the lower light-shielding film 400, for example, Ti, Cr, W, Ta, M o It is formed from a single metal, an alloy, a metal silicide, a polysilicide, or a laminate of these, including at least one of the high melting point metals such as Pb and Pb.
- a narrow moat is formed along the contour of the upper light-shielding film 401 and from the upper light-shielding film 401 to the fourth interlayer insulating film 44, the third interlayer insulating film 43, the dielectric film 75,
- a side wall light-shielding film 402 is formed so as to fill the dug through the two-layer insulating film 42, the first interlayer insulating film 41, and the base insulating film 40 to the lower light-shielding film 400.
- Side wall light shielding film 402 for example, a simple metal, alloy, metal silicide containing at least one of high melting point metals such as Ti, Cr, W, Ta, Mo, and Pb , And polysilicide.
- the lower light-shielding film 400, the upper light-shielding film 401, and the side wall light-shielding film 402 may be formed of the same light-shielding film, or may be formed of different light-shielding films.
- the wirings and elements formed on the TFT array substrate 10 are three-dimensionally shielded by the lower light shielding film 400, the upper light shielding film 401, and the side wall light shielding film 402.
- a conductive light shielding film 403 is disposed in a contact hole 85 connecting the pixel electrode 9 a and the relay layer 71, and a lower light shielding film is provided. Light is shielded so that light does not enter from the vicinity of the contact hole 85 into the space defined by 400, the upper light-shielding film 410, and the side wall light-shielding film 402 '.
- the dielectric film 75 disposed between the relay layer 71 as a capacitance electrode and the capacitance line 300 has a thickness of, for example, about 5 to 20.0 nm. It is composed of a silicon oxide film such as an extremely thin HTO (High Temperature Oxide) film, LT0 (Low Temperature Oxide) film, or a silicon nitride film. From the viewpoint of increasing the storage capacity 70, the thinner the dielectric film 75 is, the better the reliability of the film can be obtained.
- HTO High Temperature Oxide
- LT0 Low Temperature Oxide
- the capacitance line 300 extends from the image display area where the pixel electrode 9a is arranged to the periphery thereof, is electrically connected to a constant potential source, and has a fixed potential.
- a constant potential source includes a scanning line driving circuit described later for supplying a scanning signal for driving the TFT 30 to the scanning line 3a and a sampler for supplying an image signal to the data line 6a. It may be a constant potential source such as a positive power supply or a negative power supply supplied to a data line driving circuit described later for controlling the switching circuit, or a constant potential supplied to the counter electrode 21 of the counter substrate 20.
- the lower light shielding film 400, the upper light shielding film 401, and the side wall light shielding film 402 also have a capacity line 30 to prevent the potential fluctuation from adversely affecting the TFT 30. As in the case of 0, it is preferable to extend from the image display area to the periphery and connect to the constant potential source.
- the pixel electrode 9a is electrically connected to the high-concentration drain region 1e of the semiconductor layer 1a via the contact holes 83 and 85 by relaying the relay layer 71. That is, in the present embodiment, the relay layer 71 has a function of relay-connecting the pixel electrode 9a to the TFT 30 in addition to the function of the storage capacitor 70 as the pixel potential side capacitance electrode.
- the data line 6a is connected to the relay layer 72 formed of the same conductive film as the relay layer 71, so that the data line 6a is connected to the semiconductor layer 1a via the contact holes 181 and 182. Are connected to the high-concentration source region 1d.
- a pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 19 on which a predetermined alignment process such as rubbing is performed is provided above the pixel electrode 9a.
- the pixel electrode 9a is made of, for example, a transparent conductive film such as an ITO (Indium Tin Oxide) film.
- the alignment film 19 is made of, for example, an organic film such as a polyimide film.
- a counter electrode 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 on which a predetermined alignment process such as a rubbing process is performed is provided below the counter electrode 21.
- the counter electrode 21 is made of, for example, a transparent conductive film such as an ITO film.
- the alignment film 22 is made of an organic film such as a polyimide film.
- a base insulating film 40 is provided under the TFT 30 for pixel switching.
- the base insulating film 40 has a function of interlayer insulation of the TFT 30 from the lower light-shielding film 400 and is formed on the entire surface of the TFT array substrate 10 so that it can be used for polishing the surface of the TFT array substrate 10. It has the function of preventing the deterioration of the characteristics of the pixel switching TFT 30 due to the roughness of the TFT and the dirt remaining after the cleaning.
- a contact hole 18 2 leading to the high-concentration source region 1 d and a contact hole 83 leading to the high-concentration drain region 1 e are respectively opened. Are formed.
- a relay layer 71, a relay layer 72, and a capacitance line 300 are formed on the first interlayer insulating film 41, and the relay layer 72 and the relay layer 71 are respectively formed on these.
- a second interlayer insulating film 42 having contact holes 18 1 and contact holes 85 formed therein is formed.
- a data line 6a is formed, and a third interlayer insulating film 43 having a contact hole 85 leading to the relay layer 71 is formed thereon. Is formed.
- An upper light-shielding film 401 is formed on the third interlayer insulating film 43.
- a fourth interlayer insulating film 44 having a contact hole 85 formed thereon is formed on the upper light-shielding film 401, and the pixel electrode 9a is formed as described above. It is provided on the upper surface.
- the formed wires and elements are three-dimensionally shielded by the lower light-shielding film 400, the upper light-shielding film 401, and the side wall light-shielding film 402. For this reason, incident light that travels vertically or obliquely from above the substrate surface, return light that vertically or obliquely enters from below the substrate surface, and internally reflected light and multiple reflected light based on these lights. Is incident on the channel region 1 a ′, the low-concentration source region 1 b and the low-concentration drain region 1 c of the TFT 30. Blocked by membrane 402. In addition, as shown in FIG. 18, these light-shielding films allow the non-uniform regions of each pixel to be accurately defined in a grid pattern.
- a light shielding film 400 is formed in the contact hole 85.
- the contact hole 85 is located at the center of the laterally adjacent TFT 30, so that a small amount of light leakage occurs through the contact hole 85.
- the leaked light hardly reaches the TFT 30.
- the switching control of the pixel electrode 9a can be satisfactorily performed by the TFT 30, and finally a bright and high-contrast image can be displayed.
- the lower light-shielding film 400 is formed on the bottom surface of the groove 10 cV dug in the substrate 10, and the TFT 3 accommodated in the groove 10 cv is formed.
- An upper light-shielding film 401 is arranged above 0 and the like. Outside the TFT 30 and the like, the moat from the upper light-shielding film 401 to the first light-shielding film 400 is filled with a sidewall light-shielding film 402.
- the TFT 30 and the like can be three-dimensionally shielded with certainty while adopting a relatively simple manufacturing process and configuration such as an etching process and a film forming process similar to the manufacturing method of the first embodiment described above.
- the upper light-shielding film 401 and the side wall light-shielding film 402 may be integrally formed as in the case of the first or second embodiment.
- the upper moat may be laminated so as to fill it with an upper light-shielding film 401.
- a light-shielding layer may be provided at a position facing the contact hole 85 on the counter substrate 20.
- the semiconductor layer la constituting the TFT 30 for the pixel switch of the third embodiment may be a non-single-crystal layer or a single-crystal layer.
- a known method such as a bonding method can be used for forming the single crystal layer.
- the semiconductor layer 1a is a single crystal layer, the performance of the peripheral circuit can be particularly improved.
- FIG. 21 shows E_E, E_E, and FIG. 18 in the electro-optical device according to the fourth embodiment. It is a sectional view of a place corresponding to a section.
- the depth of the trench 10 cv, dug in the TFT array substrate 10 is deeper, and the lower light-shielding film 400, And the upper light-shielding film 401 'is formed so as to cover this large groove 100c', and the point where there is no side-wall light-shielding film.
- the third embodiment is different from the third embodiment, and other configurations are substantially the same as those of the third embodiment.
- the fourth embodiment it is possible to three-dimensionally shield the TFT 30 and various wirings reliably while employing a relatively simple configuration and manufacturing process.
- the depth of the groove 10 c V ′ by adjusting the depth of the groove 10 c V ′, the surface of the pixel electrode 9 a in the plane area where the TFT 30 and various wirings are formed, that is, the surface of the fourth interlayer insulating film 44 ′ is flattened. It is also possible to achieve the conversion. As a result, it is possible to reduce the alignment defect of the liquid crystal caused by the step on the surface.
- FIG. 22 is a sectional view of a place corresponding to a section.
- a sidewall light-shielding film 402 ′ ′′ is formed at a point where no groove is formed in the TFT array substrate 10, and in a moat deepened by that much. This is different from the third embodiment.
- the third embodiment is different from the third embodiment in that the third interlayer insulating film 4 4 ′ ′ is raised in accordance with the presence of 6 a and finally the surface of the fourth interlayer insulating film 4 4 ′ ′ is raised in a convex shape along the data line 6 a.
- the configuration is almost the same as that of the third embodiment.
- the fourth interlayer insulating film 44 ′ is protruding like a bank along the scanning line 3 a.
- the TFT 30 and various wirings can be reliably three-dimensionally shielded while employing a relatively simple configuration and manufacturing process.
- FIG. 23 shows a driving voltage at each pixel electrode when driven by a scanning line inversion driving method.
- FIG. 5 is a schematic plan view of a plurality of pixel electrodes, showing a relationship between the polarity of a pixel electrode and a region where a horizontal electric field is generated.
- the polarity of the liquid crystal drive voltage indicated by + or 1 is not inverted for each pixel electrode 9a, and is the same for each row.
- the pixel electrode 9a is driven.
- the states shown in FIGS. 23 (a) and 23 (b) are repeated at a cycle of one field or one frame, and the driving by the scanning line inversion driving method in this embodiment is performed.
- the scanning line inversion driving method is advantageous in that there is almost no vertical crosstalk as compared with the data line inversion driving method, and has an area where a horizontal electric field is generated as compared with the dot inversion driving method. This is advantageous in that it is fundamentally small.
- the horizontal electric field generation region C 1 is always adjacent to the pixel electrode 9 a in the vertical direction (Y direction). It is near the gap between them.
- a configuration in which no groove is dug in the TFT array substrate 10 as in the fifth embodiment is employed in the horizontal electric field generation region C1, which is a gap region between pixels along the scanning line 3a.
- a convex portion is formed on the base of the pixel electrode 9a along the scanning line 3a.
- a configuration in which a groove is dug deep into the TFT array substrate 10 as in the fourth embodiment is employed. Pixel along data line 6a The base of the electrode 9a is flattened.
- the adoption of the scanning line inversion driving method can prevent the deterioration of the electro-optical material due to the application of the DC voltage, and can prevent the cross flicker in the displayed image.
- the horizontal electric field can be relatively weakened by raising the vertical electric field by raising the base of the pixel electrode 9a in a convex shape in the horizontal electric field generation region C1. In other words, poor alignment of the liquid crystal due to the lateral electric field can be reduced.
- the base of the pixel electrode 9a is flattened by forming a deep groove, so that the step of the base of the pixel electrode 9a is reduced. Liquid crystal alignment failure based on the above.
- the vertical electric field should be strengthened in the horizontal electric field generation area, which is the gap area between pixels along the data line 6a.
- the base of the pixel electrode 9a may be raised in the region along the data line 6a in a convex shape, and the base of the pixel electrode 9a may be flattened in the region along the scanning line 3a.
- the dot inversion driving method is adopted, the scanning is performed so as to strengthen the vertical electric field in the horizontal electric field generation region, which is the gap region between the pixels along the scanning line 3a and the de-line 6a.
- the base of the pixel electrode may be raised in a convex shape in the region along the line 3a and the line 6a.
- the polarity of the driving voltage may be inverted for each row, or may be inverted for every two adjacent rows or for every plural rows.
- the polarity of the driving voltage may be inverted for each column, or may be inverted for every two adjacent columns or for a plurality of columns.
- the polarity of the driving voltage may be inverted for each block including a plurality of pixel electrodes.
- FIG. 24 shows the electro-optical device 100 as an example.
- FIG. 25 is a plan view of the components formed thereon as viewed from the counter substrate 20 side, and
- FIG. 25 is a cross-sectional view taken along the line HH ′ of FIG. 24 including the counter substrate 20.
- a sealing material 52 is provided along the edge on the TFT array substrate 10
- a light-shielding film 53 as a frame made of a light-shielding material is provided inside the sealing material 52. Is formed.
- a data line driving circuit 101 and mounting terminals 102 are provided along one side of the TFT array substrate 10, and a scanning line driving circuit 104 is provided. It is formed along two sides adjacent to this one side. If the delay of the scanning signal supplied to the scanning line does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. Further, the data line driving circuit 101 may be arranged on both sides along the side of the image display area. For example, the odd-numbered data lines supply image signals from a data line driving circuit disposed along one side of the image display area, and the even-numbered data lines are provided on the opposite side of the image display area. An image signal may be supplied from a data line driving circuit arranged along the side.
- the formation area of the data line driving circuit 101 can be expanded, so that a complicated circuit can be configured.
- a plurality of wirings 105 for connecting between the scanning line driving circuits 104 provided on both sides of the image display area are provided.
- a vertical conductive material 106 for establishing electric conduction between the TFT array substrate 10 and the opposing substrate 20 is formed. I have.
- a counter substrate 20 having substantially the same contour as the seal material 52 shown in FIG. 24 is fixed to the TFT array substrate 10 by the seal material 52. ing.
- an image signal is applied to a plurality of data lines 6a at a predetermined timing.
- Sampling circuit a precharge circuit that supplies a precharge signal of a predetermined voltage level to a plurality of data lines 6a in advance of an image signal, quality, defects, etc. of the electro-optical device during manufacturing or shipping.
- An inspection circuit or the like for inspecting the information may be formed. Furthermore, such sampling circuit, precharge The circuit, the inspection circuit, and the like may be provided using a region below the light shielding film 53.
- a driving circuit mounted on a TAB (Tape Automated bonding) substrate It may be electrically and mechanically connected to the LSI for use via an anisotropic conductive film provided on the periphery of the TFT array substrate 10.
- the type of liquid crystal 50 to be used that is, for example, TN (Twisted Nematic) mode, VA (Vertically Aligned), is provided on the light incident side or light exit side of the opposing substrate 20 and the TFT array substrate 10.
- Mode operation mode such as PDLC (Polymer Dispersed Liquid Crystal) mode, normally white mode / normal black mode, the polarizing film, retardation film, Arranged in the direction.
- the electro-optical device formed as described above is used, for example, in a projection display device (liquid crystal projector).
- a projection display device liquid crystal projector
- three electro-optical devices 100 are used as light valves for the R GB, respectively, and each of the electro-optical devices 100 is provided with a dichroic mirror for R GB color separation. The light of each of the colors is incident as projection light. Therefore, no color filter is formed in the electro-optical device 100 of each of the above-described embodiments.
- an RGB color filter may be formed on the opposing substrate 20 in a predetermined area facing the pixel electrode 9a together with its protective film. In this way, the electro-optical device according to each embodiment can be applied to a direct-view or reflective color electro-optical device other than the projector.
- a microlens may be formed on the opposing substrate 20 so as to correspond to one pixel.
- a color fill layer with a color register or the like below the pixel electrode 9a facing the RGB on the TFT array substrate 10.
- a dichroic fill film that creates RGB colors using light interference may be formed by depositing many interference layers having different refractive indices on the opposing substrate 20. According to the counter substrate with the dichroic fill filter, a brighter color electro-optical device can be realized.
- the TFT for pixel switching formed in each pixel a description has been given of an example in which a regular or cobra-shaped polysilicon TF ⁇ is used. For example, other types of TFTs may be used for pixel switching.
- FIG. 26 An embodiment of a projection type color display device as an example of an electronic apparatus using the electro-optical device described above in detail as a light valve will be described with reference to FIGS. 26 and 27.
- FIG. 26 An embodiment of a projection type color display device as an example of an electronic apparatus using the electro-optical device described above in detail as a light valve will be described with reference to FIGS. 26 and 27.
- FIG. 26 shows a circuit configuration of one of the three light valves in the projection type color display device. Since all three light valves have basically the same configuration, the part related to one circuit configuration is added here. Strictly speaking, the input signals of the three light valves are different from each other (that is, they are driven by signals for R, G, and ⁇ , respectively). The difference is that the order of the image signal is reversed in each field or frame or the horizontal or vertical scanning direction is reversed so that the image is displayed in an inverted manner, as compared with the cases of (1) and (2).
- the projection type color display device has a display information output source 100, a display information processing circuit 1002, a driving circuit 1004, a liquid crystal device 100, a clock generation circuit 1. 008 and a power supply circuit 110.
- the display information output source 10000 includes a ROM (Read Only Memory), a RAM (Random Access Memory), a memory such as an optical disk device, a tuning circuit for synchronizing and outputting image signals, and the like. Based on the clock signal from 08, display information such as an image signal of a predetermined format is output to the display information processing circuit 1002.
- the display information processing circuit 1002 includes well-known various processing circuits such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit, and is configured based on a clock signal. A digital signal is sequentially generated from the input display information and output to the driving circuit 104 together with the clock signal CLK. You.
- the drive circuit 1004 drives the liquid crystal device 100'0.
- the power supply circuit 110 supplies a predetermined power to each of the above-described circuits.
- the driving circuit 1004 may be mounted on the TFT array substrate constituting the liquid crystal device 100, and in addition, the display information processing circuit 1002 may be mounted. .
- FIG. 27 is a schematic sectional view of a projection type color display device.
- a liquid crystal projector 110 which is an example of a projection type color display device in the present embodiment, includes a liquid crystal device 100 including the liquid crystal device 100 in which the above-described drive circuit 104 is mounted on a TFT array substrate. Three modules are prepared and configured as projectors used as light pulp 100R, 100G and 100B for RGB, respectively.
- a lamp unit 1102 of a white light source such as a metal halide lamp
- three mirrors 1106 and two dichroic mirrors 110 Light components R, G, and B corresponding to the three primary colors of RGB are separated, and guided to light valves 100 R, 100 G, and 100 B corresponding to the respective colors.
- the B light passes through a relay lens system 1. 1 2 1 consisting of an input lens 1 1 2 2, a relay lens 1 1 2 3, and an output lens 1 1 2 4 to prevent light loss due to a long optical path Be guided. Then, the light components corresponding to the three primary colors modulated by the light levels of 100 R, 100 0, and 100 0 are recombined by the dichroic prism 111, and then The image is projected as a color image on the screen 1120 via the projection lens 1114.
- the electro-optical device according to the present invention has excellent light resistance, and is bright and of high quality. It can be used as various types of display devices capable of displaying images.In addition to projection display devices, LCD TVs, viewfinder type or monitor direct view type video tape recorders, car navigation systems It can be used as a display device that configures the display unit of various electronic devices such as devices, electronic organizers, calculators, word processors, workstations, mobile phones, TV phones, POS terminals, and touch panels. .
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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JP2001579024A JP3736461B2 (ja) | 2000-04-21 | 2001-04-19 | 電気光学装置、投射型表示装置及び電気光学装置の製造方法 |
US09/985,907 US6583830B2 (en) | 2000-04-21 | 2001-11-06 | Electrooptical device, projection-type display apparatus, and method for manufacturing the electrooptical device |
US10/428,987 US6768535B2 (en) | 2000-04-21 | 2003-05-05 | Electrooptical device, projection-type display apparatus, and method for manufacturing the electrooptical device |
US10/428,988 US6768522B2 (en) | 2000-04-21 | 2003-05-05 | Electrooptical device, prejection-type display apparatus, and method for manufacturing the electrooptical device |
Applications Claiming Priority (4)
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JP2000-121454 | 2000-04-21 | ||
JP2000121454 | 2000-04-21 | ||
JP2001003029 | 2001-01-10 | ||
JP2001-3029 | 2001-01-10 |
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US09/985,907 Continuation US6583830B2 (en) | 2000-04-21 | 2001-11-06 | Electrooptical device, projection-type display apparatus, and method for manufacturing the electrooptical device |
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WO2001081994A1 true WO2001081994A1 (fr) | 2001-11-01 |
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PCT/JP2001/003359 WO2001081994A1 (fr) | 2000-04-21 | 2001-04-19 | Dispositif electro-optique, affichage par projection et procede de fabrication dudit dispositif electro-optique |
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US (3) | US6583830B2 (ja) |
JP (1) | JP3736461B2 (ja) |
KR (1) | KR100481590B1 (ja) |
CN (1) | CN1203360C (ja) |
TW (1) | TWI247946B (ja) |
WO (1) | WO2001081994A1 (ja) |
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JP2019117264A (ja) * | 2017-12-27 | 2019-07-18 | セイコーエプソン株式会社 | 電気光学装置および電子機器 |
US10620494B2 (en) | 2017-12-27 | 2020-04-14 | Seiko Epson Corporation | Electro-optical device and electronic apparatus |
JP7327184B2 (ja) | 2020-01-30 | 2023-08-16 | セイコーエプソン株式会社 | 電気光学装置、および電子機器 |
Also Published As
Publication number | Publication date |
---|---|
JP3736461B2 (ja) | 2006-01-18 |
KR20020026192A (ko) | 2002-04-06 |
US6768522B2 (en) | 2004-07-27 |
US20030210363A1 (en) | 2003-11-13 |
TWI247946B (en) | 2006-01-21 |
US20030206265A1 (en) | 2003-11-06 |
CN1366626A (zh) | 2002-08-28 |
CN1203360C (zh) | 2005-05-25 |
US6768535B2 (en) | 2004-07-27 |
US20020057403A1 (en) | 2002-05-16 |
US6583830B2 (en) | 2003-06-24 |
KR100481590B1 (ko) | 2005-04-08 |
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