WO2001069872A3 - Architecture for high-speed decision feedback sequence estimation - Google Patents

Architecture for high-speed decision feedback sequence estimation Download PDF

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Publication number
WO2001069872A3
WO2001069872A3 PCT/US2001/007719 US0107719W WO0169872A3 WO 2001069872 A3 WO2001069872 A3 WO 2001069872A3 US 0107719 W US0107719 W US 0107719W WO 0169872 A3 WO0169872 A3 WO 0169872A3
Authority
WO
WIPO (PCT)
Prior art keywords
decision feedback
architecture
sequence estimation
input sample
feedback sequence
Prior art date
Application number
PCT/US2001/007719
Other languages
French (fr)
Other versions
WO2001069872A2 (en
Inventor
Arthur Abnous
Avanindra Madisetti
Christian Lutkemeyer
Original Assignee
Broadcom Corp
Arthur Abnous
Avanindra Madisetti
Christian Lutkemeyer
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp, Arthur Abnous, Avanindra Madisetti, Christian Lutkemeyer filed Critical Broadcom Corp
Priority to AU2001243566A priority Critical patent/AU2001243566A1/en
Priority to EP01916553A priority patent/EP1264455A2/en
Publication of WO2001069872A2 publication Critical patent/WO2001069872A2/en
Publication of WO2001069872A3 publication Critical patent/WO2001069872A3/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H04L25/03248—Arrangements for operating in conjunction with other apparatus
    • H04L25/03254—Operation with other circuitry for removing intersymbol interference
    • H04L25/03267—Operation with other circuitry for removing intersymbol interference with decision feedback equalisers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H04L25/03184—Details concerning the metric
    • H04L25/03197—Details concerning the metric methods of calculation involving metrics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/497—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H04L25/03203—Trellis search techniques
    • H04L25/03235—Trellis search techniques with state-reduction using feedback filtering

Abstract

A method for providing a next-cycle input sample from a decision feedback equalizer to a symbol decoder using look-ahead computations such that timing contention between the decision feedback equalizer and the symbol decoder is reduced. During a symbol period, a set of possible values is computed in the decision feedback equalizer and a set of path memory symbols is computed in the symbol decoder, the set of path memory symbols being based on a current input sample. During the same symbol period, one of the possible values is selected as the next-cycle input sample based on at least one of the next-cycle path memory symbols produced from the symbol decoder.
PCT/US2001/007719 2000-03-10 2001-03-12 Architecture for high-speed decision feedback sequence estimation WO2001069872A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2001243566A AU2001243566A1 (en) 2000-03-10 2001-03-12 Architecture for very high-speed decision feedback sequence estimation
EP01916553A EP1264455A2 (en) 2000-03-10 2001-03-12 Architecture for high-speed decision feedback sequence estimation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US18856000P 2000-03-10 2000-03-10
US60/188,560 2000-03-10

Publications (2)

Publication Number Publication Date
WO2001069872A2 WO2001069872A2 (en) 2001-09-20
WO2001069872A3 true WO2001069872A3 (en) 2002-06-27

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/007719 WO2001069872A2 (en) 2000-03-10 2001-03-12 Architecture for high-speed decision feedback sequence estimation

Country Status (4)

Country Link
US (3) US7177353B2 (en)
EP (1) EP1264455A2 (en)
AU (1) AU2001243566A1 (en)
WO (1) WO2001069872A2 (en)

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US7656959B2 (en) 2001-04-13 2010-02-02 Agere Systems Inc. Pipelined decision-feedback unit in a reduced-state viterbi detector with local feedback
US7127667B2 (en) * 2002-04-15 2006-10-24 Mediatek Inc. ACS circuit and viterbi decoder with the circuit
US7161980B2 (en) * 2002-08-19 2007-01-09 Lucent Technologies Inc. Receiver for high rate digital communication system
US7301998B2 (en) * 2003-12-19 2007-11-27 Intel Corporation Filter with signal taps temporally spaced at fractional symbol intervals
US20050135468A1 (en) * 2003-12-19 2005-06-23 Bhushan Asuri Feed forward filter
US7561619B2 (en) * 2003-12-19 2009-07-14 Intel Corporation Feedback filter
TWI255622B (en) * 2004-10-21 2006-05-21 Mediatek Inc Method of computing path metrics in a high-speed Viterbi detector and related apparatus thereof
JP4571580B2 (en) * 2005-12-15 2010-10-27 富士通株式会社 Decoder
US8386869B1 (en) * 2008-06-17 2013-02-26 Link—A—Media Devices Corporation Amplitude defect detection and correction in magnetic storage
US8576903B2 (en) 2011-10-18 2013-11-05 Transwitch Corporation Techniques for adaptively adjusting decision levels of a PAM-N decision feedback equalizer
US9447974B2 (en) 2012-09-13 2016-09-20 United Technologies Corporation Light weight swirler for gas turbine engine combustor and a method for lightening a swirler for a gas turbine engine
US9584346B2 (en) 2015-07-15 2017-02-28 International Business Machines Corporation Decision-feedback equalizer
TWI670944B (en) * 2017-08-28 2019-09-01 瑞昱半導體股份有限公司 Communication apparatus and communication method

Citations (4)

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US5870433A (en) * 1995-12-06 1999-02-09 Ke Kommunikations-Eletronik Gmbh & Co. Method of processing signals in a viterbi decoder according to delayed decision feedback sequence estimation (DDFSE) algorithm

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Publication number Priority date Publication date Assignee Title
US5056117A (en) * 1989-08-07 1991-10-08 At&T Bell Laboratories Decision feedback equalization with trellis coding
US5870433A (en) * 1995-12-06 1999-02-09 Ke Kommunikations-Eletronik Gmbh & Co. Method of processing signals in a viterbi decoder according to delayed decision feedback sequence estimation (DDFSE) algorithm
US5822143A (en) * 1996-06-11 1998-10-13 Western Digital Corporation Decision feedback equalization implementation of partial-response signaling in a magnetic recording channel
EP0889612A2 (en) * 1997-07-02 1999-01-07 Lucent Technologies Inc. Viterbi decoder and decision feedback equalizer for coded modulation

Also Published As

Publication number Publication date
WO2001069872A2 (en) 2001-09-20
US20100303144A1 (en) 2010-12-02
US8934527B2 (en) 2015-01-13
US20070189376A1 (en) 2007-08-16
EP1264455A2 (en) 2002-12-11
US7177353B2 (en) 2007-02-13
US7738549B2 (en) 2010-06-15
AU2001243566A1 (en) 2001-09-24
US20020122480A1 (en) 2002-09-05

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