WO2001054056A3 - Chipkartenschaltung mit überwachtem zugang zum testmodus - Google Patents

Chipkartenschaltung mit überwachtem zugang zum testmodus Download PDF

Info

Publication number
WO2001054056A3
WO2001054056A3 PCT/DE2001/000141 DE0100141W WO0154056A3 WO 2001054056 A3 WO2001054056 A3 WO 2001054056A3 DE 0100141 W DE0100141 W DE 0100141W WO 0154056 A3 WO0154056 A3 WO 0154056A3
Authority
WO
WIPO (PCT)
Prior art keywords
test mode
circuit
chipcard
access
monitored access
Prior art date
Application number
PCT/DE2001/000141
Other languages
English (en)
French (fr)
Other versions
WO2001054056A2 (de
Inventor
Stefan Wallstab
Original Assignee
Infineon Technologies Ag
Stefan Wallstab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Stefan Wallstab filed Critical Infineon Technologies Ag
Publication of WO2001054056A2 publication Critical patent/WO2001054056A2/de
Publication of WO2001054056A3 publication Critical patent/WO2001054056A3/de
Priority to US10/197,791 priority Critical patent/US6933742B2/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode

Abstract

Eine Schaltung zur Überwachung des Eintritts in den Testmodus einer Chipschaltung weist eine Schmelzbrücke (1) auf, die über einen Zündtransistor (2) gezündet werden kann. Durch den dadurch erzeugten Spannungsabfall wird mit Hilfe eines Flankendetektors (6) ein Flipflop (9) gesetzt, das den Zugang zum Testmodus ermöglicht. Über die Zahl der gezündeten Schmelzbrücken (1) läßt sich die Zahl der Eintritte in den Testmodus nachweisen.
PCT/DE2001/000141 2000-01-18 2001-01-15 Chipkartenschaltung mit überwachtem zugang zum testmodus WO2001054056A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/197,791 US6933742B2 (en) 2000-01-18 2002-07-18 Chip card circuit with monitored access to a test mode

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP00100952A EP1118868B1 (de) 2000-01-18 2000-01-18 Chipkartenschaltung mit überwachtem Zugang zum Testmodus
EP00100952.1 2000-01-18

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/197,791 Continuation US6933742B2 (en) 2000-01-18 2002-07-18 Chip card circuit with monitored access to a test mode

Publications (2)

Publication Number Publication Date
WO2001054056A2 WO2001054056A2 (de) 2001-07-26
WO2001054056A3 true WO2001054056A3 (de) 2001-12-06

Family

ID=8167652

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2001/000141 WO2001054056A2 (de) 2000-01-18 2001-01-15 Chipkartenschaltung mit überwachtem zugang zum testmodus

Country Status (5)

Country Link
US (1) US6933742B2 (de)
EP (1) EP1118868B1 (de)
AT (1) ATE293796T1 (de)
DE (1) DE50010098D1 (de)
WO (1) WO2001054056A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7098721B2 (en) * 2004-09-01 2006-08-29 International Business Machines Corporation Low voltage programmable eFuse with differential sensing scheme
US8742830B2 (en) * 2012-07-19 2014-06-03 Globalfoundries Singapore Pte. Ltd. Fuse sensing circuits
US9165163B2 (en) * 2012-11-30 2015-10-20 Broadcom Corporation Secure delivery of processing code

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5305267A (en) * 1992-06-25 1994-04-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device adapted for preventing a test mode operation from undesirably occurring
US5617366A (en) * 1994-12-13 1997-04-01 Samsung Electronics Co., Ltd. Method and apparatus for a test control circuit of a semiconductor memory device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5315177A (en) * 1993-03-12 1994-05-24 Micron Semiconductor, Inc. One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture
JP3274364B2 (ja) * 1996-08-14 2002-04-15 株式会社東芝 半導体装置及びヒューズチェック方法
US6023431A (en) * 1996-10-03 2000-02-08 Micron Technology, Inc. Low current redundancy anti-fuse method and apparatus
US6114878A (en) * 1998-02-13 2000-09-05 Micron Technology, Inc. Circuit for contact pad isolation
JP3401522B2 (ja) * 1998-07-06 2003-04-28 日本電気株式会社 ヒューズ回路及び冗長デコーダ回路
US6353336B1 (en) * 2000-03-24 2002-03-05 Cypress Semiconductor Corp. Electrical ID method for output driver

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5305267A (en) * 1992-06-25 1994-04-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device adapted for preventing a test mode operation from undesirably occurring
US5617366A (en) * 1994-12-13 1997-04-01 Samsung Electronics Co., Ltd. Method and apparatus for a test control circuit of a semiconductor memory device

Also Published As

Publication number Publication date
ATE293796T1 (de) 2005-05-15
US6933742B2 (en) 2005-08-23
WO2001054056A2 (de) 2001-07-26
US20030065932A1 (en) 2003-04-03
EP1118868B1 (de) 2005-04-20
EP1118868A1 (de) 2001-07-25
DE50010098D1 (de) 2005-05-25

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