WO2001047014A1 - Organic flip chip packages with an array of through hole pins - Google Patents

Organic flip chip packages with an array of through hole pins Download PDF

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Publication number
WO2001047014A1
WO2001047014A1 PCT/US2000/016788 US0016788W WO0147014A1 WO 2001047014 A1 WO2001047014 A1 WO 2001047014A1 US 0016788 W US0016788 W US 0016788W WO 0147014 A1 WO0147014 A1 WO 0147014A1
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WO
WIPO (PCT)
Prior art keywords
carrier member
organic substrate
solder
solder alloy
pins
Prior art date
Application number
PCT/US2000/016788
Other languages
French (fr)
Inventor
Raj N. Master
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Priority to JP2001547650A priority Critical patent/JP2003518744A/en
Priority to KR1020027008124A priority patent/KR20020065602A/en
Priority to EP00942924A priority patent/EP1249041A1/en
Publication of WO2001047014A1 publication Critical patent/WO2001047014A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3447—Lead-in-hole components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09754—Connector integrally incorporated in the PCB or in housing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10295—Metallic connector elements partly mounted in a hole of the PCB
    • H05K2201/10303—Pin-in-hole mounted pins
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process

Definitions

  • the present invention relates an organic member for mounting a semiconductor device, and more particularly to an organic carrier member having an array of through hole pins embedded in the organic carrier member.
  • Integrated circuit (IC) devices whether individual active devices, individual passive devices, multiple active devices within a single chip, or multiple passive and active devices within a single chip, require suitable input output (I/O) connections between themselves and other circuit elements or structures. These devices are typically very small and fragile. Because of their size and fragility, they are commonly carried on substrates for support, i.e., carrier members.
  • Area array chip interconnects use bumps or solder joints that directly couples the IC chip or die to the carrier member. This technique accommodates an increased number of I/O terminals and provides electrical signals immediately below the chip, improving voltage noise margins and signal speed.
  • area array interconnect packaging technique is the flip chip (FC) solder interconnect on a carrier member.
  • the IC die and other devices are "bumped" with solder bumps or balls, i.e. a plurality of discrete solder bumps are formed over metal contacts on the surface of the die.
  • the chip is then turned upside down or “flipped” so that the device side or face of the IC die couples to the carrier member such as found in a plastic carrier member having balls, pins or land grid arrays.
  • the solder bumps of the device are then attached to the carrier member forming an electrical and mechanical connection.
  • a through-hole organic carrier member conventionally employs a multi-layer substrate constructed of a plurality laminated dielectric and conductive layers where individual IC chips are mounted to the top layer of the substrate.
  • the conductive layers are made of a pre-defined metallization pattern sandwiched between dielectric layers within the substrate.
  • Metallization patterns on certain layers act as voltage reference planes and also provide power to the individual chips.
  • Metallization patterns on other layers route signals between individual chips. Electrical connections to individual terminals of each chip and/or between separate layers are made through well-known vertical interconnects called "vias".
  • Input output (I/O) pins are embedded within the substrate and electrically connected to appropriate metalliation patterns existing within the substrate thereby routing electrical signals between a multi-chip integrated circuit package and external devices. As illustrated in Fig.
  • a conventional flip chip assembly 8 includes a device or die 10 mechanically and electrically attached to substrate 16 by a plurality of solder bumps 12 connected to solder pads 14 on substrate 16. Solder pads 14 are electrically connected to an array of pin leads 18 by internal metallized layers (not shown for illustrative convenience) throughout substrate 16. Pin leads 18 are used to provide electrical connections to external circuitry. The assembly, thus, provides an electrical signal path from die 10 through solder/pad connections 12/14 through substrate 16 by way of internal metallization pattern to an external connection by way of I/O pin leads 18.
  • substrate 16 has a plurality of solder pads 14, which are generally formed by screen printing a coating of solder on the substrate.
  • Solder balls 12 on die 10 are generally formed by known solder bumping techniques and are conventionally formed of a high lead solder, such as solders containing 97-95 weight percent (wt%) lead / 3-5 wt% tin having a melting temperature of approximately 323 °C.
  • a known technique for bonding a pin lead to an organic substrate involves inserting a pin in a preformed through hole in the multilayered substrate.
  • the inserted pin is coated with a 10 wt% lead /10 wt% tin solder and heating the substrate causes the solder on the pin to reflow forming a bond between the pin and the internal metallized layer of the multilayered substrate.
  • One problem associated with attaching pin leads to the internal metallized layer in an organic substrate is that the soldering temperature cannot be higher than the decomposition temperature of the polymeric material used to fabricated to the multilayered substrate, without adversely compromising the mechanical integrity of the substrate.
  • solders employed for joining pin leads to the metallized layer should form strong mechanical bonds capable of withstanding pulling, placement, or testing of the assembly, i.e. socketing, with good electrical signal.
  • An advantage of the present invention is an organic carrier member suitable for mounting a device with highly reliable pin leads.
  • Another advantage of the present invention is a device assembly that maintains reliable electrical connections during its operation.
  • the carrier member of the present invention comprises: an organic substrate having an internal conductive layer; a plurality of conductive contacts on the organic substrate for receiving a device to be mounted thereto in electrical communication with the internal conductive layer; a plurality of pins which extend away from the organic substrate with each pin having its top end portion embedded into the organic substrate and each top end portion joined to the internal conductive layer by a solder alloy having a reflow temperature of no greater than about 300 °C, e.g. the solder alloy has a reflow temperature of about 220 °C to about 270 °C.
  • the conductive contacts comprise solder pads and the solder alloy bonding the top end portion of the pins has a reflow temperature higher than the reflow temperature of the solder pads, i.e., the temperature difference between reflowing the solder pads and the solder alloy joining the pins and the solder pads is no less than approximately 10 °C.
  • Solder alloys of the present invention comprise about 85 wt% to about 82 wt% lead, about 12 wt% to about 8 wt% antimony, about 10 wt% to about 3 wt% tin and up to about 5 wt% silver. Additional solder alloys of the present invention comprise about 95 wt% to about 80 wt% tin, about 15 wt% to about 3 wt% antimony, up to about 50 wt% indium and up to about 5 wt% silver. Other solder alloys of the present invention comprise about 80 wt% to about 50 wt% lead and about 50 wt% to about 20 wt% indium.
  • the organic substrate can comprise polyphenylene sulphide, polysulphone, polyethersulphone, polyarysulphone, phenol, polyamide, bismaleimide-triazine, epoxy or mixtures thereof with optionally fiberous materials, such as glass fibers, to fabricate a laminated structure with internal wiring connecting the solder pads with the leads at the bottom of the organic substrate.
  • the organic substrate can be fabricated by any of the above resins, or mixtures thereof in to a non-laminated structure, such as a molded plastic part with internal wiring.
  • Another aspect of the present invention is a device assembly comprising a device and a supporting organic carrier member having an array of pin leads embedded therein.
  • the assembly comprises: a device having a plurality solderable contacts thereon, wherein the solderable contacts of the device are joined to the conductive contacts on the carrier member of the present invention.
  • the device can be an integrated circuit die having a plurality solder bumps, such as a bumped IC die or bumped capacitor and mounted to the supporting carrier member.
  • Another aspect of the present invention is a method of manufacturing a device assembly.
  • the method comprises: providing carrier member for mounting a device, wherein the carrier member comprising: an organic substrate having an internal conductive layer; a plurality of solder pads on the organic substrate for receiving a device to be mounted thereto in electrical communication with the internal conductive layer; a plurality of pins which extend away from the organic substrate with each pin having its top end portion embedded into the organic substrate and each top end portion electrically bonded to the internal conductive layer by a solder alloy having a reflow temperature of no greater than about 300 °C; mounting a device having a plurality of solderable contacts thereon on to the carrier member such that the solderable contacts of the device are aligned with the solder pads on the organic substrate; and reflowing the solder pads on the organic substrate at a temperature no greater than the reflow temperature of the solder alloy bonding the pins to form an electrical connection between the solderable contacts of the device and the solder pads on the organic substrate.
  • the embedded pins are joined to the internal conductive layer by reflowing a solder alloy therebetween at a temperature no less than about 205 °C to provide a mechanical and electrical joint between the internal conductive layer and the pins prior to providing the carrier member.
  • the solder alloy comprises about 85 wt% to about 82 wt% lead, about 12 wt% to about 8 wt% antimony, about 10 wt% to about 3 wt% tin and up to about 5 wt% silver.
  • Fig. 1 schematically depicts a conventional flip chip assembly.
  • Fig. 2A-2B schematically illustrate a cross-sectional view of a pin lead joined to an internal conductive layer and embedded in an organic substrate of the present invention.
  • the present invention stems from the discovery that employing solder alloys with a high melting or reflow temperature to join an internal conductive layer to an embedded pin lead improves the mechanical integrity of the embedded pin and prevents the joint from separating during subsequent thermal processing steps in manufacturing a device assembly.
  • solder alloys with a high melting or reflow temperature to join an internal conductive layer to an embedded pin lead improves the mechanical integrity of the embedded pin and prevents the joint from separating during subsequent thermal processing steps in manufacturing a device assembly.
  • conventional low temperature solder alloys employed in joining pin leads within organic carrier members melt internally during the die attach process causing volume expansion straining and ultimately breaking the formed joint.
  • the present invention overcomes the undesirable reflow of internal solder alloys by using a high temperature solder alloy to form the joint between an internal conductive layer and embedded pin in an organic carrier member.
  • the solder alloys of the present invention have a reflow temperature that is below the decomposition transition temperature of the organic carrier, yet higher than the reflow temperature of subsequent thermal processes and still forms a strong mechanical and electrical bond capable of undergoing many temperature cycles without discontinuity over the life-time operation of the device.
  • Figs. 2A and 2B illustrate an organic carrier member of the present invention.
  • carrier member 20 comprises an organic substrate 22 having an internal conductive layer 24.
  • An array of conductive contacts 26, e.g. solder pads, are formed on organic substrate 22 for receiving a device (not shown).
  • the array of solder pads 26 are patterned to correspond to the metallization pattern of a give device to be mounted thereon.
  • the organic carrier member further comprises a plurality of pin leads 28. As shown in Fig. 2B, the pin lead extends from the organic substrate 22 with each pin having its top end portion 30 embedded into the organic substrate and each top end portion 30 electrically and mechanically joined to internal conductive layer 24 by a solder alloy 32.
  • the pins can be configured in any desired footprint. Additionally, the organic carrier member can also contain plated through-hole thermal vias and/or a metal slug to dissipate the heat generated by an attached device.
  • the internal conductive layers can be made by vapor deposing metal layers on dielectric layers used to fabricate a laminated structure. Metals useful in forming the conductive layers include aluminum, nickel, iron, copper, gold or alloys thereof at a thickness of about 5 microns to about 40 microns.
  • the pin leads can be made of alloys or layers of cobalt, nickel, iron and plated with one or more layers of nickel or gold. Given the guidance and objectives of the present disclosure, the optimum solder compositions and organic substrate can be necessarily determined for a particular device assembly.
  • formulated solder alloys have a high reflow temperature, i.e. the temperature which the solder is mobile enough to form an electrical connection.
  • the formulated solders have a reflow temperature of about 220 °C to about 270 °C.
  • Solder alloys of the present invention comprise about 85 wt% to about 82 wt% lead, about 12 wt% to about 8 wt% antimony, about 10 wt% to about 3 wt% tin and up to about 5 wt% silver.
  • solder alloys useful in the present invention comprise about 95 wt% to about 80 wt% tin, about 15 wt% to about 3 wt% antimony, up to about 20 wt% indium and up to about 5 wt% silver. Still other solder alloys useful in the present invention comprise about 80 wt% to about 50 wt% lead and up to about 50 wt% indium.
  • Table 1 below provides solder alloys together with their melting characteristics that are suitable for joining pin leads to internal conductive layers within organic substrates in accordance with the present invention. Table 1.
  • the solder alloys of the present invention further advantageously have a reflow temperature which does not compromise the integrity of the organic substrate.
  • the organic substrate comprises a high temperature stable polymeric material, such as sulphone, polyarysulphone, phenol, polyamide, bismaleimide-triazine, epoxy or mixtures thereof.
  • Polyimides are radiation resistant high temperature stable materials that can be prepared as laminates for organic packages. For example, polyimide itself has a thermal decomposition temperature of over 300 °C.
  • Polyimides can further be copolymerized with one or more imide substituted monomers to enhance dielectric and/or thermal properties.
  • Typical monomers that can be copolymerized with polyimides include amides, phenolics, bismaleimide, epoxys and esters to form the corresponding polimide copolymers.
  • the organic substrate of the present invention can be fabricated in the form of a molded part or as a laminated structure.
  • a laminated structure with internal conductive layers with embedded pin leads at can be fabricated having one or more conductive layers and insulating polymer layers with optionally fiberous materials, such as glass fibers.
  • the organic substrate can be fabricated from an organic epoxy-glass resin based material, such as bismaleimide-triazine (BT) resin or FR-4 board laminate having a high thermal decomposition temperature.
  • the organic substrate comprises a bismaleimide-triazine epoxy laminate structure having an internal metal layer, such as a layer of copper.
  • solder pads On the surface of the substrate are a plurality of solder pads arranged in a pattern to receive a semiconductor device.
  • the pin leads are in electrical communication with the internal metal layer.
  • a plurality of Co-Ni-Fe pin leads coated with nickel and/or gold are embedded in the laminate with each top end portion electrically and mechanically joined to the internal metal layer by a solder alloy having a reflow temperature of no greater than about 300 °C.
  • the pin leads are joined to the internal conductive layer by inserting a pre-coated pin leads into a pre-formed through hole in the organic carrier member.
  • the pin lead is joined to the internal conductive layer by reflowing the solder alloys of the present invention at a temperature no less than about 210 °C to form a mechanically and electrically strong bond therebetween.
  • a device assembly is prepared by providing a carrier member of the present invention and mounting a device having a plurality of solderable contacts thereon on to the carrier member such that the solderable contacts of the device are aligned with the solder pads on the member.
  • the device can be any device having a solderable conductive contact thereon.
  • the device can be a high lead solder bumped IC, e.g. 97-95 wt% Pb/3-5 wt% Sn, having under bump metallurgy, i.e. comprising one or more layers or an alloy of chrome, copper, gold, titanium, nickel, etc. between the high lead solder bump and the IC, or a bumped capacitor, or any other device having a solderable conductive contact.
  • an electrical interconnection is formed between the device and the member by the application of heat, such as by infrared radiation, a flow of dry heated gas, such as in a belt furnace, etc. to reflow the solder pads on the member and interconnect the device and carrier member.
  • the solder pads on the carrier member are reflowed by a process of heating the organic carrier member from about 240 °C to about 260 °C, e.g. heating the carrier member to about 250 °C, by a process of a combined infrared/convection heater.
  • the temperature difference between reflowing the solder pads and the solder alloy joining the pins is no less than approximately 10 °C, e.g. no less than about 5 °C.

Abstract

An organic carrier member for mounting a semiconductor device is provided that has a plurality of pin leads joined to conductive pads by an internal conductive layer. The pin leads are embedded in the organic carrier member and joined to the conductive layer by a solder alloy having a reflow temperature higher than the temperature necessary to attach the semiconductor device. Embodiments include a bismaleimide-triazine epoxy laminate carrier member having an array of pins joined to the carrier member by a solder alloys having a reflow temperature of about 220 °C to about 270 °C.

Description

ORGANIC FLIP CHIP PACKAGES WITH AN ARRAY OF THROUGH HOLE PINS
Field of the Invention
The present invention relates an organic member for mounting a semiconductor device, and more particularly to an organic carrier member having an array of through hole pins embedded in the organic carrier member.
Background Art
The escalating requirements for high density and performance associated with ultra-large scale integration technology creates significant challenges for the design and implementation of electrical connections between circuit components and external electrical circuitry. Integrated circuit (IC) devices whether individual active devices, individual passive devices, multiple active devices within a single chip, or multiple passive and active devices within a single chip, require suitable input output (I/O) connections between themselves and other circuit elements or structures. These devices are typically very small and fragile. Because of their size and fragility, they are commonly carried on substrates for support, i.e., carrier members.
Device miniaturization and ever the increasing density of semiconductor devices require an ever increasing number of I O terminals, shorter connections and improvements in the electrical connections, heat dissipation and insulation characteristics of the carrier member. This problem is exacerbated in manufacturing semiconductor devices having a design rule of about 0.18 microns and under.
One technique that supports the increased device densities is the shift from peripheral wire bonding to area array chip interconnects. Area array chip interconnects use bumps or solder joints that directly couples the IC chip or die to the carrier member. This technique accommodates an increased number of I/O terminals and provides electrical signals immediately below the chip, improving voltage noise margins and signal speed. One type of area array interconnect packaging technique is the flip chip (FC) solder interconnect on a carrier member.
In the flip chip assembly or package, the IC die and other devices are "bumped" with solder bumps or balls, i.e. a plurality of discrete solder bumps are formed over metal contacts on the surface of the die. The chip is then turned upside down or "flipped" so that the device side or face of the IC die couples to the carrier member such as found in a plastic carrier member having balls, pins or land grid arrays. The solder bumps of the device are then attached to the carrier member forming an electrical and mechanical connection.
A through-hole organic carrier member conventionally employs a multi-layer substrate constructed of a plurality laminated dielectric and conductive layers where individual IC chips are mounted to the top layer of the substrate. The conductive layers are made of a pre-defined metallization pattern sandwiched between dielectric layers within the substrate. Metallization patterns on certain layers act as voltage reference planes and also provide power to the individual chips. Metallization patterns on other layers route signals between individual chips. Electrical connections to individual terminals of each chip and/or between separate layers are made through well-known vertical interconnects called "vias". Input output (I/O) pins are embedded within the substrate and electrically connected to appropriate metalliation patterns existing within the substrate thereby routing electrical signals between a multi-chip integrated circuit package and external devices. As illustrated in Fig. 1, a conventional flip chip assembly 8 includes a device or die 10 mechanically and electrically attached to substrate 16 by a plurality of solder bumps 12 connected to solder pads 14 on substrate 16. Solder pads 14 are electrically connected to an array of pin leads 18 by internal metallized layers (not shown for illustrative convenience) throughout substrate 16. Pin leads 18 are used to provide electrical connections to external circuitry. The assembly, thus, provides an electrical signal path from die 10 through solder/pad connections 12/14 through substrate 16 by way of internal metallization pattern to an external connection by way of I/O pin leads 18.
As shown, substrate 16 has a plurality of solder pads 14, which are generally formed by screen printing a coating of solder on the substrate. Solder balls 12 on die 10 are generally formed by known solder bumping techniques and are conventionally formed of a high lead solder, such as solders containing 97-95 weight percent (wt%) lead / 3-5 wt% tin having a melting temperature of approximately 323 °C.
A known technique for bonding a pin lead to an organic substrate involves inserting a pin in a preformed through hole in the multilayered substrate. The inserted pin is coated with a 10 wt% lead /10 wt% tin solder and heating the substrate causes the solder on the pin to reflow forming a bond between the pin and the internal metallized layer of the multilayered substrate. One problem associated with attaching pin leads to the internal metallized layer in an organic substrate is that the soldering temperature cannot be higher than the decomposition temperature of the polymeric material used to fabricated to the multilayered substrate, without adversely compromising the mechanical integrity of the substrate. Further, the solders employed for joining pin leads to the metallized layer should form strong mechanical bonds capable of withstanding pulling, placement, or testing of the assembly, i.e. socketing, with good electrical signal. As the need for increasing I/O terminals increases and the need for lighter and smaller packages increase, the problems associated with mounting dies and capacitors creates new challenges for the manufacture of pin-grid-array packages.
Accordingly, a need exists in the art for improved pin grid array packages permitting a strong, reliable, minimally resistive soldered joint to form between the pin leads and the metallized layers.
SUMMARY OF THE INVENTION An advantage of the present invention is an organic carrier member suitable for mounting a device with highly reliable pin leads. Another advantage of the present invention is a device assembly that maintains reliable electrical connections during its operation.
Additional advantages and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a carrier member for mounting a device. The carrier member of the present invention comprises: an organic substrate having an internal conductive layer; a plurality of conductive contacts on the organic substrate for receiving a device to be mounted thereto in electrical communication with the internal conductive layer; a plurality of pins which extend away from the organic substrate with each pin having its top end portion embedded into the organic substrate and each top end portion joined to the internal conductive layer by a solder alloy having a reflow temperature of no greater than about 300 °C, e.g. the solder alloy has a reflow temperature of about 220 °C to about 270 °C. In an embodiment of the present invention, the conductive contacts comprise solder pads and the solder alloy bonding the top end portion of the pins has a reflow temperature higher than the reflow temperature of the solder pads, i.e., the temperature difference between reflowing the solder pads and the solder alloy joining the pins and the solder pads is no less than approximately 10 °C.
Solder alloys of the present invention comprise about 85 wt% to about 82 wt% lead, about 12 wt% to about 8 wt% antimony, about 10 wt% to about 3 wt% tin and up to about 5 wt% silver. Additional solder alloys of the present invention comprise about 95 wt% to about 80 wt% tin, about 15 wt% to about 3 wt% antimony, up to about 50 wt% indium and up to about 5 wt% silver. Other solder alloys of the present invention comprise about 80 wt% to about 50 wt% lead and about 50 wt% to about 20 wt% indium. The organic substrate can comprise polyphenylene sulphide, polysulphone, polyethersulphone, polyarysulphone, phenol, polyamide, bismaleimide-triazine, epoxy or mixtures thereof with optionally fiberous materials, such as glass fibers, to fabricate a laminated structure with internal wiring connecting the solder pads with the leads at the bottom of the organic substrate. Alternatively, the organic substrate can be fabricated by any of the above resins, or mixtures thereof in to a non-laminated structure, such as a molded plastic part with internal wiring.
Another aspect of the present invention is a device assembly comprising a device and a supporting organic carrier member having an array of pin leads embedded therein. The assembly comprises: a device having a plurality solderable contacts thereon, wherein the solderable contacts of the device are joined to the conductive contacts on the carrier member of the present invention. The device can be an integrated circuit die having a plurality solder bumps, such as a bumped IC die or bumped capacitor and mounted to the supporting carrier member.
Another aspect of the present invention is a method of manufacturing a device assembly. The method comprises: providing carrier member for mounting a device, wherein the carrier member comprising: an organic substrate having an internal conductive layer; a plurality of solder pads on the organic substrate for receiving a device to be mounted thereto in electrical communication with the internal conductive layer; a plurality of pins which extend away from the organic substrate with each pin having its top end portion embedded into the organic substrate and each top end portion electrically bonded to the internal conductive layer by a solder alloy having a reflow temperature of no greater than about 300 °C; mounting a device having a plurality of solderable contacts thereon on to the carrier member such that the solderable contacts of the device are aligned with the solder pads on the organic substrate; and reflowing the solder pads on the organic substrate at a temperature no greater than the reflow temperature of the solder alloy bonding the pins to form an electrical connection between the solderable contacts of the device and the solder pads on the organic substrate. In accordance with the present invention, the embedded pins are joined to the internal conductive layer by reflowing a solder alloy therebetween at a temperature no less than about 205 °C to provide a mechanical and electrical joint between the internal conductive layer and the pins prior to providing the carrier member. In an embodiment of the present invention, the solder alloy comprises about 85 wt% to about 82 wt% lead, about 12 wt% to about 8 wt% antimony, about 10 wt% to about 3 wt% tin and up to about 5 wt% silver.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 schematically depicts a conventional flip chip assembly. Fig. 2A-2B schematically illustrate a cross-sectional view of a pin lead joined to an internal conductive layer and embedded in an organic substrate of the present invention.
DESCRIPTION OF THE INVENTION
The present invention stems from the discovery that employing solder alloys with a high melting or reflow temperature to join an internal conductive layer to an embedded pin lead improves the mechanical integrity of the embedded pin and prevents the joint from separating during subsequent thermal processing steps in manufacturing a device assembly. In particular, it was discovered that conventional low temperature solder alloys employed in joining pin leads within organic carrier members melt internally during the die attach process causing volume expansion straining and ultimately breaking the formed joint.
The present invention overcomes the undesirable reflow of internal solder alloys by using a high temperature solder alloy to form the joint between an internal conductive layer and embedded pin in an organic carrier member. The solder alloys of the present invention have a reflow temperature that is below the decomposition transition temperature of the organic carrier, yet higher than the reflow temperature of subsequent thermal processes and still forms a strong mechanical and electrical bond capable of undergoing many temperature cycles without discontinuity over the life-time operation of the device.
Figs. 2A and 2B illustrate an organic carrier member of the present invention. As illustrated, carrier member 20 comprises an organic substrate 22 having an internal conductive layer 24. An array of conductive contacts 26, e.g. solder pads, are formed on organic substrate 22 for receiving a device (not shown). The array of solder pads 26 are patterned to correspond to the metallization pattern of a give device to be mounted thereon. The organic carrier member further comprises a plurality of pin leads 28. As shown in Fig. 2B, the pin lead extends from the organic substrate 22 with each pin having its top end portion 30 embedded into the organic substrate and each top end portion 30 electrically and mechanically joined to internal conductive layer 24 by a solder alloy 32.
The pins can be configured in any desired footprint. Additionally, the organic carrier member can also contain plated through-hole thermal vias and/or a metal slug to dissipate the heat generated by an attached device. The internal conductive layers can be made by vapor deposing metal layers on dielectric layers used to fabricate a laminated structure. Metals useful in forming the conductive layers include aluminum, nickel, iron, copper, gold or alloys thereof at a thickness of about 5 microns to about 40 microns. The pin leads can be made of alloys or layers of cobalt, nickel, iron and plated with one or more layers of nickel or gold. Given the guidance and objectives of the present disclosure, the optimum solder compositions and organic substrate can be necessarily determined for a particular device assembly.
In accordance with the present invention, formulated solder alloys have a high reflow temperature, i.e. the temperature which the solder is mobile enough to form an electrical connection. In an embodiment of the present invention, the formulated solders have a reflow temperature of about 220 °C to about 270 °C. Solder alloys of the present invention comprise about 85 wt% to about 82 wt% lead, about 12 wt% to about 8 wt% antimony, about 10 wt% to about 3 wt% tin and up to about 5 wt% silver. Other solder alloys useful in the present invention comprise about 95 wt% to about 80 wt% tin, about 15 wt% to about 3 wt% antimony, up to about 20 wt% indium and up to about 5 wt% silver. Still other solder alloys useful in the present invention comprise about 80 wt% to about 50 wt% lead and up to about 50 wt% indium.
Table 1 below provides solder alloys together with their melting characteristics that are suitable for joining pin leads to internal conductive layers within organic substrates in accordance with the present invention. Table 1.
Figure imgf000009_0001
The solder alloys of the present invention further advantageously have a reflow temperature which does not compromise the integrity of the organic substrate. In an embodiment of the present invention, the organic substrate comprises a high temperature stable polymeric material, such as sulphone, polyarysulphone, phenol, polyamide, bismaleimide-triazine, epoxy or mixtures thereof. Polyimides are radiation resistant high temperature stable materials that can be prepared as laminates for organic packages. For example, polyimide itself has a thermal decomposition temperature of over 300 °C.
Polyimides can further be copolymerized with one or more imide substituted monomers to enhance dielectric and/or thermal properties. Typical monomers that can be copolymerized with polyimides include amides, phenolics, bismaleimide, epoxys and esters to form the corresponding polimide copolymers.
The organic substrate of the present invention can be fabricated in the form of a molded part or as a laminated structure. A laminated structure with internal conductive layers with embedded pin leads at can be fabricated having one or more conductive layers and insulating polymer layers with optionally fiberous materials, such as glass fibers. For example, the organic substrate can be fabricated from an organic epoxy-glass resin based material, such as bismaleimide-triazine (BT) resin or FR-4 board laminate having a high thermal decomposition temperature. In an embodiment of the present invention, the organic substrate comprises a bismaleimide-triazine epoxy laminate structure having an internal metal layer, such as a layer of copper. On the surface of the substrate are a plurality of solder pads arranged in a pattern to receive a semiconductor device. The pin leads are in electrical communication with the internal metal layer. A plurality of Co-Ni-Fe pin leads coated with nickel and/or gold are embedded in the laminate with each top end portion electrically and mechanically joined to the internal metal layer by a solder alloy having a reflow temperature of no greater than about 300 °C.
In practicing the invention, the pin leads are joined to the internal conductive layer by inserting a pre-coated pin leads into a pre-formed through hole in the organic carrier member. The pin lead is joined to the internal conductive layer by reflowing the solder alloys of the present invention at a temperature no less than about 210 °C to form a mechanically and electrically strong bond therebetween.
In accordance with the present invention, a device assembly is prepared by providing a carrier member of the present invention and mounting a device having a plurality of solderable contacts thereon on to the carrier member such that the solderable contacts of the device are aligned with the solder pads on the member. The device can be any device having a solderable conductive contact thereon. For example, the device can be a high lead solder bumped IC, e.g. 97-95 wt% Pb/3-5 wt% Sn, having under bump metallurgy, i.e. comprising one or more layers or an alloy of chrome, copper, gold, titanium, nickel, etc. between the high lead solder bump and the IC, or a bumped capacitor, or any other device having a solderable conductive contact.
Once the carrier member of the present invention is aligned with the device, an electrical interconnection is formed between the device and the member by the application of heat, such as by infrared radiation, a flow of dry heated gas, such as in a belt furnace, etc. to reflow the solder pads on the member and interconnect the device and carrier member. . In an embodiment of the present invention, the solder pads on the carrier member are reflowed by a process of heating the organic carrier member from about 240 °C to about 260 °C, e.g. heating the carrier member to about 250 °C, by a process of a combined infrared/convection heater. In an embodiment of the present invention, the temperature difference between reflowing the solder pads and the solder alloy joining the pins is no less than approximately 10 °C, e.g. no less than about 5 °C.
The process steps and structures described above do not form a complete process flow for manufacturing device assemblies or the packaging of integrated semiconductor devices. The present invention can be practiced in conjunction with electronic package fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections of portions of electronic package fabrication are not drawn to scale, but instead are drawn to illustrate the features of the present invention.
While this invention has been described in connection with what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

What is Claimed Is:
1. A carrier member for mounting a device, the member comprising: an organic substrate having an internal conductive layer; a plurality of conductive contacts on the organic substrate for receiving a device to be mounted thereto in electrical communication with the internal conductive layer; a plurality of pins which extend away from the organic substrate with each pin having its top end portion embedded into the organic substrate and each top end portion joined to the internal conductive layer by a solder alloy having a reflow temperature of no greater than about 300 °C.
2. The carrier member of claim 1, wherein the solder alloy has a reflow temperature of about 220 to about 270 °C.
3. The carrier member of claim 1, wherein the conductive contacts comprise solder pads and the solder alloy joining the top end portion of the pins has a reflow temperature higher than the reflow temperature of the solder pads.
4. The carrier member of claim 3, wherein the temperature difference between reflowing the solder pads and the solder alloy joining the pins is no less than about 5 °C.
5. The carrier member of claim 1, wherein the solder alloy comprises about 85 wt% to about 82 wt% lead, about 12 wt% to about 8 wt% antimony, about 10 wt% to about 3 wt% tin and up to about 5 wt% silver.
6. The carrier member of claim 1, wherein the solder alloy comprises about 95 wt% to about 80 wt% tin, about 15 wt% to about 3 wt% antimony, up to about 50 wt% indium and up to about 5 wt% silver.
7. The carrier member of claim 1. wherein the solder alloy comprises about 80 wt% to about 50 wt% tin and about 50 wt% to about 20 wt% indium.
8. The carrier member of claim 1, wherein the reflow temperature of the solder alloy is between about 240°C to about 260 °C.
9. The carrier member of claim 1, wherein the organic substrate comprises a laminated structure.
10. The carrier member of claim 1, wherein the organic substrate comprises a bismaleimide-triazine epoxy laminate.
11. The carrier member of claim 1, wherein the organic substrate comprises a molded plastic.
12. A carrier member for mounting a device, the member comprising: a substrate comprising a bismaleimide-triazine epoxy laminate having an internal metallized layer; a plurality of solder pads on the laminate for receiving a device to be mounted thereto in electrical communication with the internal metallized layer; and a plurality of gold coated pins which extend away from the laminate with each pin having its top end portion embedded into the laminate and each top end portion joined to the internal metallized layer by a solder alloy having a reflow temperature of no greater than about 300 °C.
13. A device assembly, the assembly comprising: the carrier member of claim 1 ; and a device having a plurality solderable contacts thereon, wherein the solderable contacts of the device are joined to the conductive contacts on the organic substrate.
14. The device assembly of claim 13, wherein the solderable contacts comprise an alloy or layers of chrome, copper and gold in electrical communication with solder bumps.
15. The device assembly of claim 14, wherein the device is an integrated circuit die.
16. A method of manufacturing a device assembly, the method comprising: providing carrier member for mounting a device, wherein the carrier member comprising: an organic substrate having an internal conductive layer; a plurality of solder pads on the organic substrate for receiving a device to be mounted thereto in electrical communication with the internal conductive layer; a plurality of pins which extend away from the organic substrate with each pin having its top end portion embedded into the organic substrate and each end portion electrically bonded to the internal conductive layer by a solder alloy having a reflow temperature of no greater than about 300 °C; mounting a device having a plurality of solderable contacts thereon on to the carrier member such that the solderable contacts of the device are aligned with the solder pads on the organic substrate; and reflowing the solder pads on the organic substrate at a temperature no greater than the reflow temperature of the solder alloy bonding the pins to form an electrical connection between the solderable contacts of the device and the solder pads on the organic substrate.
17. The method of claim 16, comprising reflowing the solder pads on the organic substrate by heating the carrier member to about 250 °C.
18. The method of claim 16, comprising joining the plurality of pins mechanically and electrically to the internal conductive layer by reflowing a solder alloy at a temperature no less than about 210 °C prior to providing the carrier member.
19. The method of claim 18, wherein the solder alloy comprises about 85 wt% to about 82 wt% lead, about 12 wt% to about 8 wt% antimony, about 10 wt% to about 3 wt% tin and up to about 5 wt% silver.
20. The carrier member of claim 18, wherein the solder alloy comprises about 95 wt% to about 80 wt% tin, about 15 wt% to about 3 wt% antimony, up to about 50 wt% indium and up to about 5 wt% silver.
PCT/US2000/016788 1999-12-21 2000-06-15 Organic flip chip packages with an array of through hole pins WO2001047014A1 (en)

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EP00942924A EP1249041A1 (en) 1999-12-21 2000-06-15 Organic flip chip packages with an array of through hole pins

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Citations (4)

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US4170472A (en) * 1977-04-19 1979-10-09 Motorola, Inc. Solder system
US5303862A (en) * 1992-12-31 1994-04-19 International Business Machines Corporation Single step electrical/mechanical connection process for connecting I/O pins and creating multilayer structures
US5479319A (en) * 1992-12-30 1995-12-26 Interconnect Systems, Inc. Multi-level assemblies for interconnecting integrated circuits
US5938862A (en) * 1998-04-03 1999-08-17 Delco Electronics Corporation Fatigue-resistant lead-free alloy

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4170472A (en) * 1977-04-19 1979-10-09 Motorola, Inc. Solder system
US5479319A (en) * 1992-12-30 1995-12-26 Interconnect Systems, Inc. Multi-level assemblies for interconnecting integrated circuits
US5303862A (en) * 1992-12-31 1994-04-19 International Business Machines Corporation Single step electrical/mechanical connection process for connecting I/O pins and creating multilayer structures
US5938862A (en) * 1998-04-03 1999-08-17 Delco Electronics Corporation Fatigue-resistant lead-free alloy

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