WO2001045112A1

WO2001045112A1 - Mobile communication device having flash memory system with word line buffer

Info

Publication number: WO2001045112A1
Application number: PCT/US2000/034215
Authority: WO
Inventors: Stephen Mark Simmonds; Sanjay Jha
Original assignee: Qualcomm Incorporated
Priority date: 1999-12-17
Filing date: 2000-12-14
Publication date: 2001-06-21
Also published as: AU2108701A

Abstract

The flash memory system includes a flash memory controller and flash memory cells. The flash memory controller includes a buffer register for caching a word line of data. A write unit writes data to the flash memory using the buffer register by receiving data to be written to said flash memory, storing the data in the buffer register; and writing all data within the buffer register, in parallel, into the flash memory. A write verify unit of the flash memory controller reads data written to the flash memory, compares the data to corresponding data of the buffer register, and determines whether the data read from the flash memory is the same as the corresponding data of the buffer register. A read unit reads data from the flash memory using the buffer register by receiving an address location to be read from said flash memory, determining whether the address location is among addresses of data already stored in the buffer register. If so, the read unit reads data from the buffer register corresponding to the address location. If not, the read unit retrieves data from the flash memory cells containing the address location and then reads the data from the buffer register. By providing a word line buffer register in connection with the flash memory, overall system response time is improved. Method and apparatus embodiments are provided.

Description

MOBILE COMMUNICATION DEVICE HAVING FLASH MEMORY SYSTEM WITH WORD LINE BUFFER

I. Field of the Invention The invention generally relates to mobile communication devices such as cellular telephones and in particular to flash memory for use therein.

II. Description of the Related Art

A flash memory is a type of non-volatile memory that retains stored information even after power is disconnected. This is in contrast with volatile memory devices, such as SRAM or dynamic RAM (DRAM), which lose data stored therein once power has been disconnected. In addition to being nonvolatile, flash memory is electrically erasable and reprogrammable within the system in which it is incorporated. This is in contrast with other non-volatile memory devices, such as erasable, programmable read-only memory (EPROM) which typically requires special voltages for reprogramming and, hence, is typically only reprogrammable by a manufacturer or service specialist.

Accordingly, flash memory is advantageously employed within devices requiring non-volatile memory that can be selectively erased and reprogrammed. In particular, flash memory is well-suited for use in desktop personal computers, laptop computers, video game cartridges, digital voice recorders, personal digital assistants (PDA's), and cellular telephones (or other mobile stations of wireless communication systems). Typically, within such systems, the flash memory is configured as a single flash macro, which can either be written to or read from, but not both, at any given time. For most devices this is sufficient. For example, within most devices containing flash memory, any data to be stored within the flash memory is stored within volatile memory until the device is to be shut off, then the flash memory is reprogrammed with the data during a shut-down operation. As such, it is unlikely that the device will ever need to both read from and write to the flash memory at the same time. As one example, a PC or laptop computer may store changes to a basic input/cutput system (BIOS) within a DRAM memory until the computer is to be shut dow n, then the changes to the BIOS are transferred to flash memory.

Problems, however, arise when attempting to implement flash memory within a cellular telephone which may require many more frequent read operations and write operations to the flash memory. Cellular telephones consume a considerable amount of power during use and, to be commercially desirable, the cellular telephone must be able to operate effectively for long periods of time between recharging. As a result, cellular telephones are typically configured to shut down power to internal components as often as possible. Within CDMA cellular telephones, for example, many components are powered down between each successive paging slot of the overall CDMA system. (The paging slots occur 30 milli-seconds apart.) Accordingly, it is not feasible to accumulate pending write operations within a non-volatile memory until a single final power shut-down operation. Rather, a data to be written to the flash memory may need to be written promptly prior to a next power shutdown. Moreover, the need to frequently reprogram the flash memory is typically much greater within a cellular telephone, particularly within a cellular smart phone, i.e., a cellular telephone configured with a PDA to provide both cellular telephony functions and PDA functions, and any other devices such as laptop computers and video game systems. Insofar as computers are concerned, a flash memory may only need to be reprogrammed in the event there are changes to the BIOS or other configuration parameters of the system. With a cellular smart phone, the flash memory may need to be frequently reprogrammed to record new telephone numbers, addresses, calendar dates, meeting dates and the like. For smart phones configured to record voice memos, the flash memory may need to be reprogrammed whenever an operator of the telephone wishes to record a voice memo. Accordingly, reading and writing operations may need to be performed much more frequently in connection with cellular telephones and the conventional flash memory arrangement, whereby reading from and writing to the flash memory cannot be performed simultaneously, may be inadequate.

Moreover, within cellular telephone applications, the flash memory may need to be accessed much more quickly than is required in other applications. This is particularly true if the data to be retrieved from the flash memory is required for use in connection with any real time functions of the cellular telephone, such as voice telephone calls. For such functions, any delay necessitated by having to wait for a previous write operation to be completed before reading from the flash memory may be significant. Moreover, read times within conventional flash memories are typically relatively slow. More specifically, flash memories become degraded with use such that the read time for particular flash cells that have been frequently rewritten becomes relatively slow in comparison with flash cells that have not been frequently rewritten. Hence, the overall read time for the flash memory is set to be relatively slow to compensate for possible degradation. In this regard, a bus system connected to the flash memory for retrieving data from the flash memory is programmed with some number of wait states to compensate for potentially slow access times. In other words, the bus system is preprogrammed to accommodate the worst case scenario insofar as flash memory access time is concerned. As a result, all read accesses are relatively slow even from flash memory locations which have not yet been degraded. Again, with many devices, the slow read time is not problematic. However, in connection in with cellular telephones, it is much more important to minimize the time required for each access from flash memory, particularly while the cellular telephone is engaged in real time functions. Accordingly, it would be highly desirable to provide an improved flash memory system, particularly for use within cellular telephones or similar devices which overcomes the disadvantages set forth above. It is to this end that aspects of the present invention are directed. SUMMARY OF THE INVENTION

In accordance with the invention, a flash memory system for use in a mobile communications device is provided with a buffer register for storing recently accessed data from flash memory. The flash memory system includes a flash memory controller and flash memory cells. The controller includes a buffer register for storing recently accessed data for a plurality of the flash memory cells.

In an exemplary embodiment, the flash controller also includes a write unit for writing data to the flash memory using the buffer register. The flash controller also includes a write verify unit for reading data written to the flash memory, comparing the data to corresponding data of the buffer register, and determining whether the data read from the flash memory is the same as the corresponding data of the buffer register. The flash controller additionally includes a read unit for reading data from the flash memory using the buffer register. The flash controller also includes an erase unit for erasing data from the flash memory using the buffer register. The flash controller further includes an erase verify unit for reading data from cells of the flash memory subject to a previous erase operation and for verifying that the cells have been erased. By providing a buffer register in connection with a flash memory controller for use in a mobile communications device, overall efficiency of the mobile communications device is improved. For example, if data to be read from flash memory is already in the buffer register, read operations can be satisfied by accessing the buffer register rather than accessing the slower flash memory. In the event a write operation is in progress to the flash memory, a pending read operation need not be deferred until the write operation is completed so long as the read can be satisfied from the buffer register. Indeed, since flash memory write operations typically take much longer than flash memory read operations, numerous read operations may be performed from the buffer register during a single flash memory ^ vrite operation. Also, in the exemplary embodiment, the buffer register of the flash controller stores a word line of data (e.g. 2048 bits). The flash controller is connected to the flash memory by a flash memory data bus capable of transmitting a word line of data in parallel. The flash controller is connected to a microcontroller of the mobile communications device by a system data bus capable of transmitting only a fraction of a word line, such as 32 bits, in parallel. As such, write operations to the same word line can be accumulated in the buffer register, then processed as a single write operation, potentially saving considerable processing time over a system wherein each individual write operation must be separately performed to flash memory. By permitting fewer write operations to the flash memory, flash memory cell degradation is reduced and read times therefore can be generally faster. Moreover, power is saved whenever a read or write can be accommodated by the buffer register because flash memory accesses consume more power than register accesses. Other objects, features and advantages of the invention will be apparent from the descriptions which follow in conjunction with the attached drawings. Method and apparatus embodiments of the invention are provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a voice and data modem ASIC having an embedded flash memory system with buffer register for use within a mobile telephone.

FIG. 2 is a block diagram of a flash memory system of the ASIC of FIG. 1.

FIG. 3 is a block diagram of internal components of the read unit of FIG 1.

FIG. 4 is a block diagram of internal components of the write unit of

FIG 1.

FIG. 5 is a block diagram of internal components of the erase unit of

FIG 1. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

With reference to the figures, preferred and exemplary embodiments of the invention will now be described. The invention will primarily be described with reference to an embedded flash memory system with buffer register for use within a voice and data modem ASIC of a CDMA cellular telephone.

However, the principles of the invention are applicable to other systems as well.

FIG. 1 illustrates a voice and data modem ASIC 100 for use within a mobile wireless communications device such as a cellular telephone configured for use within a CDMA wireless communication system. The voice and data modem ASIC includes circuitry for handling telephony functions of the cellular telephone. Although not shown, the cellular telephone may include other ASIC's or other integrated circuits configured to perform other functions. For example, if the cellular telephone is configured as a smart phone to provide PDA functions as well as wireless telephony functions, a separate ASIC may be provided for controlling the PDA functions. Alternatively, all functions may be integrated within a single ASIC.

To handle the wireless telephony functions of the cellular telephone, ASIC includes a microprocessor 102 for controlling the voice and data modem functions. The microprocessor may be, for example, a reduced instruction set computing (RISC) microprocessor, such as the ARM 7TDMI^# microprocessor provided by Arm, Incv ARM 7TDMI and Arm, Inc. are both trademarks of Arm, Inc. In other implementations, other microprocessors are employed including, for example, complex instruction set computing (CISC) microprocessors. Various peripheral components, generally denoted 104, are provided within the ASIC for performing specific CDMA wireless telephony functions.

A system bus 106 interconnects the microprocessor and the various CDMA peripheral components. In use, the microprocessor controls the various CDMA peripheral components, via the system bus, to perform various functions directed to processing CDMA wireless communications such as converting CDMA signals received from a base station (not shown) into voice signals for outputting through a speaker of the cellular telephone or converting voice signals received from a microphone of the cellular telephone into CDMA signals for transmission to the base station. To perform these and other functions, the microprocessor and the peripheral components store data or other information within either an internal memory system 108 formed on the ASIC or within an external memory system 110, which may comprise one or more SRAM, DRAM or flash memory chips mounted within the cellular telephone external to the ASIC. In general, data or other information that needs to be accessed quickly, such as data used in connection with real time processing of telephone calls and the like, is stored within the internal memory system for expedient access. Data that does not need to be retrieved as quickly, such as data for use with non-real time functions, is stored within the external memory system.

The internal memory system includes a flash memory system 112 and an SRAM 113 integrated as a single memory system. As will be described in greater detail below, the flash memory system includes a buffer register for caching data stored in the flash memory system. An internal memory interface unit 115 interconnects the internal memory system with the mciroprocessor and the peripheral CDMA components via system bus 106. An external memory interface unit 117 interconnects the external memory system with the mciroprocessor and the peripheral CDMA components also via system bus 106. Flash memory system 112 of the internal memory system is used primarily for storing CDMA software code for use by the microprocessor or the CDMA peripheral components. Typically, the flash memory also includes a boot loader which is retrieved and run during an initial power-up operation by the microprocessor. The boot loader includes instructions for accessing and running other CDMA programs stored within the flash memory. The flash memory is also employed for providing non-volatile storage of data used in connection with the cellular telephone, such as storage of names, telephone numbers, addresses and the like. If the cellular telephone is configured as a smart phone to additionally perform the operations of a PDA, then the flash memory additionally stores data used by the PDA, such as meeting dates, calenders, schedules, voice memos, and the like. In general, any type of software or data which much be retained even while the cellular telephone is completed powered down is preferably stored within either the flash memory system embedded within ASIC or within the flash memory system, if any, provided within the external memory. Embedded SRAM 113 provides volatile storage of other types of data or software programs employed by the microprocessor or the peripheral components in connection with their functions. For example, as CDMA signals are received from a base station during a cellular telephone conversation, the various peripheral components may store the signals, or processed versions thereof, within the SRAM. As one specific example, after the deinterleaver has processed the input signals, the deinterleaved signals are stored within the SRAM for subsequent processing by the Viterbi decoder. The external memory may also be employed as a volatile memory for storing data, particularly data which need not be accessed at high rates. Now briefly considering the CDMA peripheral components of ASIC 100, for transmission of signals, a vocoder 114 is provided, which may be configured as a DSP, for converting voice signals it receives through a microphone (not shown) into digitized symbols or other packets of information. One example of a vocoder is described in U.S. Patent No. 5,414,796. A CDMA encoder 116 encodes the symbols generated by the vocoder for error correction and detection purposes. An example encoder is a trellis encoder described in U.S. Patent No. 5,848,102. A CDMA interleaver 118 interleaves the encoded signals to provide time diversity to thereby permit a reduction in transmission power. An exemplary interleaver is described within U.S. Patent No. 5,633,881. A CDMA modulator 120 modulates the interleaved signals for subsequent transmission via an antenna (not shown). An implementation of a CDMA modulator is described in U.S. Patent Nos. 5,103,459 and 4,901,307. For processing received signals, a CDMA demodulator 122 demodulates the signals, a deinterleaver 124 deinterleaves the signals so as to remove the effect of any previous interleaving, and a CDMA decoder 126 decodes signals to extract voice or data signals encoded therein. An exemplary demodulator is described within U.S. Patent No. 5,602,833. An exemplary deinterleaver is described within the aforementioned U.S. Patent No. 5,633,881. An exemplary decoder is provided within the aforementioned U.S. Patent No. 5,848,102. Another exemplary decoder is provided within U.S. Patent No. 5,710,784. Each of the aforementioned patents are assigned to the assignee of the present invention and are incorporated by reference herein at least for the purposes of providing information pertinent to the functions performed by the various CDMA peripheral components. For voice communications, the decoded voice signals are output through a speaker (not shown) to the user of the telephone. For data communications, the decoded data signals are further processed by other components of the phone such as, for example, for display (on a display not shown) using a web browser program, email program or the like.

Thus, FIG. 1 illustrates, among other features, an ASIC having a flash memory provided with buffer register for caching data stored within the flash memory. As noted above, by providing a buffer register in connection with the flash memory, overall system response time is improved. Many read operations can be satisfied by directly accessing the buffer register rather than accessing the slower flash memory. Pending read operations need not be deferred until the write operation is completed so long as the read can be satisfied from the flash buffer register. Numerous read operations may be performed from the buffer register during a single flash memory write operation. Write operations can be accumulated in the buffer register, then processed as a single word line write, potentially saving processing time by a factor of sixty-four. Flash memory cell degradation is typically reduced and read times therefore can be generally faster. Power is also saved whenever a read or write is accommodated by the buffer register.

Thus, the provision of a flash memory with buffer register within ASIC 100 provides numerous advantages. In the following, specific features of the flash memory will be described in greater detail. Referring now to FIG. 2, the embedded flash memory system includes a flash memory array 130 and a flash memory controller 132 having a buffer register 134. A flash memory system bus 136 interconnects the flash memory and the flash controller permitting the flash controller to access the flash memory array. The flash controller is also connected to the system bus 106 permitting the microprocessor (FIG. 1) and possibly other units of the mobile communication system to access the flash controller to retrieve data stored within the flash memory, to write data into the flash memory, or to erase data from the flash memory. The connection of the flash memory controller to the system bus may be direct or, as shown in FIG. 1, may be through an internal memory interface unit or the like. Subsequent to a write operation or an erase operation, the flash controller verifies that the write or erase operation was properly performed. To accommodate these and other functions, the flash controller includes a flash read unit 138, a flash write unit 140, a flash erase unit 142, a write verify unit 144 and an erase verify unit 146. The manner by which flash read unit 138 processes read commands will now be described with reference to FIG. 3. Upon receiving a read command from the microprocessor via a read address reception unit 150, the read unit of the flash controller examines the address specified by the read command using a buffer register address range determination unit 152 to compare the address with the range of addresses stored within the data currently maintained within buffer register 134. If the address is within the address range of the buffer register, the read unit merely accesses the buffer register using a buffer register data read unit 154 to retrieve the data requested by the read command, then forwards the data over the system bus to the microprocessor or other requesting device. If the address of the read command is not within the address range of data currently stored within the buffer register, the read unit performs a word line read operation using a flash memory word line data retrieval unit 156 and flash bus 136 to read the entire word line of data containing the requested address. The word line of data retrieved is stored in the buffer register by overwriting whatever word line of data was previously stored therein. Then, the read unit extracts the specific data requested by the read command using the aforementioned buffer register data read unit 154 and forwards the data over the system bus to the microprocessor or other requesting device. In this manner, a read command is fulfilled, if possible, merely by accessing data contained within the buffer register thereby eliminating the need to power up the flash memory and read data stored therein. Hence, power is saved and processing is expedited.

Note that, the buffer register stores an entire word line of data. Hence, if a subsequent read command requests data within the same word line while the word line is still stored within the register, the subsequent read command also can be accommodated by accessing the buffer register. On the average, a read command is more likely to access the same word line of data accessed by an immediately previous memory access command than another word line of data. Accordingly, on the average, processing time and power are both saved by performing read operations using the buffer register.

The manner by which a write command is processed by the flash controller will now be described with reference to FIG. 4. Upon receiving a write command from the system bus via a data and address receive unit 158, write unit 140 uses a buffer register data storage unit 160 to store the received data within the buffer register. To this end, the write unit compares the address specified by the write command with the range of addresses of data stored within the buffer register using a buffer register address range determination unit 162. If the address falls within the range of addresses, the write unit merely replaces that portion of data stored within the buffer register with the data received within the write command using a buffer register data insertion unit 164. If, however, the address does not fall within the range of addresses of data currently stored within the buffer register, the write unit accesses the flash memory to read the word line of data containing the address using a flash memory word line data retrieval unit 166. Once the word line of data has been inserted into the buffer register, the write unit then uses the aforementioned buffer register data insertion unit to insert data into the buffer register. If another write command is received specifying an address also within the range of addresses of the buffer register, the subsequent write command is also accommodated merely by replacing data within the buffer register. Ultimately, a read command, write command or other command will be received which requires access to some other word line of data. At that time, the entire contents of the buffer register are written to flash memory via the flash memory bus using a flash memory word line data write unit 168. With the flash memory bus having a width equal to that of the buffer register, the write operation is performed in only one clock cycle.

Depending upon the specific implementation, the read command, write command or other command triggering the flash memory write operation is either delayed pending completion of the flash memory write operation or is performed concurrently therewith. To permit a read operation to be performed while a write operation is pending, a read while writing unit is provided. A specific implementation of the read while writing unit is set forth in copending United States Patent Application Serial No. unknown entitled "Mobile Communication Device Having Integrated Embedded Flash and SRAM Memory", Attorney Docket No. PD990406, filed December 13, 1999, assigned to the Assignee of rights to the present invention, and incorporated by reference herewith.

As with read operations, write operations are, on the average, more likely to be to the same word line of data accessed by an immediately previous memory access command than to another word line. Accordingly, on the average, processing time and power are both saved by performing write operations using the buffer register.

An erase command received via the system bus is processed in much the same manner as a write command. The erase command will be summarized with reference to the components illustrated in FIG. 5. Briefly, erase unit 142 receives an erase command specifying an address of data to be erased using an erase command address reception unit 170. The erase unit then determines whether the data to be erased is currently within the register buffer using a buffer register address range determination unit 172. If so, the erase unit merely erases that portion of data within the register buffer using a buffer register data erase unit 174. Herein, by erase, it is meant that the erase unit sets all of the bits of that portion of data to all binary zeros. Eventually, when a memory access is required to an address not within the range of addresses of the data currently stored within the buffer register, the data stored within the buffer register is then written to flash memory using a flash memory word line data write unit 176 to thereby commit the erase operation to memory. Any pending write operations or other erase operations accumulated within the buffer register are also thereby committed to memory. If, on the other hand, the buffer register address range determination unit determines that the address to be erased is not currently within the buffer register, then the erase unit uses a flash memory word line data retrieval unit 178 to retrieve the word line of data containing the address to be erased from the flash memory. The aforementioned buffer register data erase unit is then used to erase the data as it appears within the buffer register. Ultimately, the word line containing the erased data is written to the flash memory using word line data write unit 176.

Referring again to FIG. 2, subsequent to a write command or an erase command, the flash controller performs a write verify operation or an erase verify operation to verify that the write or erase was properly recorded within the flash memory. Write verification is performed by write verify unit 144 by reading the data written to the flash memory, then comparing the data with that within the buffer register. More specifically, the write verify unit compares the data stored within the buffer register at the specified address with the data read from flash memory and, if the data matches, verification is complete. If not, then corrective measures are taken perhaps requiring that the write operation be repeated. Similar operations are performed to verify an erase command using erase verify unit 146.

In a specific implementation, a word line of data contains 2048 bits of data. Accordingly, flash memory bus 136 is a 2048-bit wide bus and buffer register 134 stores 2048 bits of data. The system bus is a 32 bit bus. Hence, the buffer register stores 64 times the amount of data accommodated by the system bus. Hence, significant processing time and power savings can be achieved as compared with a system wherein the flash memory bus, the buffer register and the system bus are all of equal width. Nevertheless, even in an implementation wherein all are of equal length, the presence of the buffer register within the flash controller permits at least some gain in processing time and power savings by permitting at least some read commands to be accommodated directly from the buffer register. As can be appreciated, though, the greater the ratio of the size of the buffer register to the size of the system bus, the greater the benefits of the invention. In general, the buffer register and flash memory bus may be of length N and the system bus may be of length M. Preferably, N divided by M is 64. However, other ratios are advantageous as well. For example, it may be desirable to configure the buffer register to store only a half word, quarter word or one-eighth word of data. In still other implementations, the buffer register and the flash memory bus do not have the same length. For example, the flash memory bus may accommodate only one-half word of data, although the buffer register accommodates an entire word line of data. In such an implementation, at least two clock cycles are required to transfer the entire contents of the buffer register to the flash memory. Nevertheless, overall power savings and processing time benefits still may be achieved. In still other implementations, two or more buffer registers are provided within the flash controller for storing two or more word lines of data. As can be appreciated, a wide range of different combinations of the various configuration parameters may be employed consistent with the general principles of the invention. Accordingly, the specific examples described herein are merely illustrative of the invention and should not be construed as limiting the scope of the invention.

What is claimed is:

Claims

1. A flash memory system for use in a mobile communication device comprising: flash memory cells; and a flash memory controller having a buffer register for caching data from a plurality of said flash memory cells.

2. The system of claim 1 wherein said buffer register caches either a word line of data, a half word line of data, a quarter word line of data, or an eight word line of data.

3. The system of claim 2 wherein said word line of data contains 2048 bits.

4. The system of claim 1 wherein said flash controller includes a write unit for writing data to the flash memory using the buffer register.

5. The svstem of claim 4 wherein said write unit includes: a data and address reception unit for receiving data to be written to said flash memory; a buffer register data storage unit for storing said data in said buffer register; and a flash memory data write unit for writing all data within said buffer register, in parallel, into said flash memory.

6. The system of claim 5 wherein said buffer register data storage unit includes an address location determination unit for determining whether an address location for storing the data is among address locations of data contained within the buffer register; a buffer register data insertion unit, responsive to a determination that said address location is among address locations of data contained within the buffer register, for inserting the data into the buffer register; and a flash memory data retrieval unit, responsive to a determination that said address location is not among address locations of data contained within the buffer register, for retrieving data from the flash memory cells containing said address location.

7. The system of claim 1 wherein said flash controller includes a write verify unit for verifying data written to said flash memory.

8. The system of claim 7 wherein said write verify unit reads data written to the flash memory, compares the data to corresponding data within the buffer register, and determines whether the data read from the flash memory is the same as the corresponding data of the buffer register.

9. The system of claim 1 wherein said flash controller includes an erase unit for erasing data from the flash memory using the buffer register.

10. The system of claim 9 wherein erase unit includes: an address reception unit for receiving an address location specifying data to be erased from said flash memory; an buffer register address range determination unit for determining whether the address location is among address locations of data contained within the buffer register; a buffer register dε ta erase unit, responsive to a determination that said address location is among a dress locations of data contained within the buffer register, for erasing data at said address location from within the buffer register; a flash memory data retrieval unit, responsive to a determination that said address location is not among address locations of data contained within the buffer register, for retrieving data from the flash memory cells containing said address location; and a flash memory data write unit for writing all data within said buffer register, in parallel, into said flash memory.

11. The system of claim 1 wherein said flash controller includes an erase verify unit for verifying erasure of data from said flash memory.

12. The system of claim 11 wherein said erase verify unit reads data from cells of the flash memory subject to a previous erase operation, compares the data to corresponding data within the buffer register, and determines whether the data read from the flash memory is the same as the corresponding data of the buffer register to verify that the cells have been erased.

13. The system of claim 1 wherein said flash controller includes a read unit for reading data from the flash memory using the buffer register.

14. The system of claim 13 wherein read unit includes: an address reception unit for receiving an address location to be read from said flash memory; a buffer register address range determination unit for determining whether the address location is among addresses of data already stored in said buffer register; a buffer register read unit for reading data from the buffer register corresponding to the address location; and a flash memory data retrieval unit for retrieving data from the flash memory cells containing said address location.

15. The system of claim 1 wherein said flash controller is connected to said flash memory by a first data transmission bus of width N and connected to a microcontroller by a second data transmission bus of width M, with M less than N; and wherein said buffer register is of length N.

16. The system of claim 15 wherein N is 2048 and M is 32.

17. A flash memory system for use in a mobile communication device comprising: flash memory storage means for storing data in flash memory cells; and a flash memory controller means for accessing said flash memory storage means, said flash memory controller means having a buffer register means for caching data from a plurality of said flash memory cells.

18. The system of claim 17 wherein said buffer register means caches either a word line of data, a half word line of data, a quarter word line of data, or an eight word line of data.

19. The system of claim 18 wherein said word line of data contains 2048 bits.

20. The system of claim 17 wherein said flash memory controller means includes write means for writing data to the flash memory using the buffer register storage means.

21. The system of claim 20 wherein said write means includes: means for receiving data to be written to said flash memory storage means; means for storing said data in said buffer register storage means; and means for writing all data within said buffer register storage means, in parallel, into said flash memory cells.

22. The system of claim 21 wherein said means for storing data in said buffer register storage means includes means for determining whether an address location for storing the data is among address locations of data contained within the buffer register storage means; means, responsive to a determination that said address location is among address locations of data contained within the buffer register storage means, for inserting the data into the buffer register storage means; and means, responsive to a determination that said address location is not among address locations of data contained within the buffer register storage means, for retrieving data from the flash memory cells containing said address location and for then inserting the data into the buffer register storage means.

23. The system of claim 20 wherein said means for writing all data within said buffer register storage means includes means for receiving a command requiring access to an address not among address locations of data contained within the buffer register storage means; and means, responsive to receipt of said command, for writing all data contained in the buffer register storage means to the flash memory cells.

24. The system of claim 17 wherein said flash memory controller means includes write verify means for verifying data written to said flash memory cells.

25. The system of claim 24 wherein said write verify means includes means for reading data written to the flash memory cells; means for comparing the data to corresponding data within the buffer register storage means; and means for determining whether the data read from the flash memory cells is the same as the corresponding data of the buffer register storage means.

26. The system of claim 17 wherein said flash memory controller means includes erase means for erasing data from the flash memory cells using the buffer register storage means.

27. The system of claim 25 wherein said erase means includes: means for receiving an address location specifying data to be erased from said flash memory; means for determining whether the address location is among address locations of data contained within the buffer register storage means; means, responsive to a determination that said address location is among address locations of data contained within the buffer register storage means, for erasing data at said address location from within the buffer register storage means; means, responsive to a determination that said address location is not among address locations of data contained within the buffer register storage means, for retrieving data from the flash memory cells containing said address location and then for erasing the data at said address location from within the buffer register storage means; and means for writing ail data within said buffer register storage means, in parallel, into said flash memory.

28. The system of claim 27 wherein said means for writing all data within said buffer register storage means includes means for receiving a command requiring access to an address not among address locations of data contained within the buffer register storage means; and means, responsive to receipt of said command, for writing all data contained in the buffer register storage means to the flash memory cells.

29. The system of claim 17 wherein said flash controller includes erase verify means for verifying erasure of data from said flash memory cells.

30. The system of claim 29 wherein said erase verify means includes means for reading data from flash memory cells subject to a previous erase operation; means for comparing the data to corresponding data within the buffer register storage means; and means for determining whether the data read from the flash memory cells is the same as the corresponding data of the buffer register storage means to verify that the cells have been erased.

31. The system of claim 17 wherein said flash controller includes read means for reading data from the flash memory using the buffer register storage means.

32. The system of claim 31 wherein said read means includes: means for receiving an address location to be read from said flash memory cells; means for determining whether the address location is among addresses of data already stored in said buffer register storage means; means, responsive to a determination that the address location is among addresses of data already stored in said buffer register storage means, for reading data from the buffer register storage means corresponding to the address location; and means, responsive to a determination that the address location is not among addresses of data already stored in said buffer register storage means, for retrieving data from the flash memory cells containing said address location and for then reading the data from the buffer register storage means.

33. The system of claim 17 wherein said flash controller is connected to said flash memory by a first data transmission bus of width N and connected to a microcontroller by a second data transmission bus of width M, with M less than N; and wherein said buffer register means is of length N.

34. The system of claim 33 wherein N is 2048 and M is 32.

35. A method for use in a mobile communication device for accessing a flash memory system having flash memory cells and a flash memory controller having a buffer register for caching data from a plurality of the flash memory cells, said method comprising the steps of: storing data from a flash memory access command in the buffer register; receiving a new flash memory access command; and processing the new command using the buffer register.

36. The method of claim 35 wherein said buffer register caches either a word line of data, a half word line of data, a quarter word line of data, or an eight word line of data.

37. The method of claim 36 wherein said word line of data contains 2048 bits.

38. The method of claim 35 wherein the new command is a write command and wherein the step of processing the new command using the buffer register includes the steps of: receiving data to be written to said flash memory; storing said data in said buffer register; and writing all data within said buffer register, in parallel, into said flash memory.

39. The method of claim 38 wherein said step of storing data in said buffer register includes the steps of determining whether an address location for storing the data is among address locations of data contained within the buffer register; responsive to a determination that said address location is among address locations of data contained within the buffer register, inserting the data into the buffer register; and responsive to a determination that said address location is not among address locations of data contained within the buffer register, retrieving data from the flash memory cells containing said address location and for then inserting the data into the buffer register.

40. The method of claim 38 wherein said step of writing all data within said buffer register includes the steps of receiving a command requiring access to an address not among address locations of data contained within the buffer register; and responsive to receipt of said command, writing all data contained in the buffer register to the flash memory cells.

41. The method of claim 35 further including the step of performing a write verify operation by: reading the data written to the flash memory; and comparing the data to corresponding data within the buffer register, and determines whether the data read from the flash memory is the same as the corresponding data of the buffer register.

42. The method of claim 35 wherein the new command is an erase command and wherein the step of processing the new command using the buffer register includes the steps of: receiving an address location specifying data to be erased from said flash memory; determining whether the address location is among address locations of data contained within the buffer register; responsive to a determination that said address location is among address locations of data contained within the buffer register, erasing data at said address location from within the buffer register; and responsive to a determination that said address location is not among address locations of data contained within the buffer register, retrieving data from the flash memory cells containing said address location and then for erasing the data at said address location from within the buffer register. writing all data within said buffer register, in parallel, into said flash memory.

43. The system of claim 42 wherein said step of writing all data within said buffer register includes the steps of receiving a command requiring access to an address not among address locations of data contained within the buffer register; and responsive to receipt of said command, writing all data contained in the buffer register to the flash memory cells.

44. The method of claim 35 further including the step of performing an erase verify operation by: reading data from cells of the flash memory subject to a previous erase operation; comparing the data to corresponding data within the buffer register; and determining whether the data read from the flash memory is the same as the corresponding data of the buffer register to verify that the cells have been erased.

45. The method of claim 35 wherein the new command is a read command and wherein the step of processing the new command using the buffer register includes the steps of: receiving an address location to be read from said flash memory; and determining whether the address location is among addresses of data already stored in said buffer register, and if so, reading data from the buffer register corresponding to the address location and, if not, retrieving data from the flash memory cells containing said address location and for then reading the data from the buffer register.