WO2001040816A1 - A method and integrated circuit arranged for feeding a test forcing pattern on a single shared pin of the circuit - Google Patents
A method and integrated circuit arranged for feeding a test forcing pattern on a single shared pin of the circuit Download PDFInfo
- Publication number
- WO2001040816A1 WO2001040816A1 PCT/EP2000/011115 EP0011115W WO0140816A1 WO 2001040816 A1 WO2001040816 A1 WO 2001040816A1 EP 0011115 W EP0011115 W EP 0011115W WO 0140816 A1 WO0140816 A1 WO 0140816A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit
- test
- pattern
- forcing
- data
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE60021705T DE60021705T2 (en) | 1999-11-29 | 2000-11-09 | METHOD AND INTEGRATED CIRCUIT DESIGNED TO FEED A TEST PATTERN ON AN INDIVIDUAL COMMON TERMINAL |
EP00979546A EP1157278B1 (en) | 1999-11-29 | 2000-11-09 | A method and integrated circuit arranged for feeding a test forcing pattern on a single shared pin of the circuit |
JP2001542225A JP2003515747A (en) | 1999-11-29 | 2000-11-09 | Method and integrated circuit for providing a test pattern to a single pin of a circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99204015 | 1999-11-29 | ||
EP99204015.4 | 1999-11-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001040816A1 true WO2001040816A1 (en) | 2001-06-07 |
Family
ID=8240923
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2000/011115 WO2001040816A1 (en) | 1999-11-29 | 2000-11-09 | A method and integrated circuit arranged for feeding a test forcing pattern on a single shared pin of the circuit |
Country Status (6)
Country | Link |
---|---|
US (1) | US6657451B2 (en) |
EP (1) | EP1157278B1 (en) |
JP (1) | JP2003515747A (en) |
KR (1) | KR100742406B1 (en) |
DE (1) | DE60021705T2 (en) |
WO (1) | WO2001040816A1 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7157813B2 (en) * | 2003-10-03 | 2007-01-02 | Power Integrations, Inc. | Method and apparatus for mode selection for high voltage integrated circuits |
DE102004016387A1 (en) * | 2004-04-02 | 2005-10-27 | Texas Instruments Deutschland Gmbh | Interface circuit for a single logic input pin of an electronic system |
ATE534077T1 (en) * | 2005-02-24 | 2011-12-15 | Microchip Tech Inc | ACTIVATION OF SPECIAL MODES ON A DIGITAL DEVICE |
US7526693B1 (en) * | 2006-03-09 | 2009-04-28 | Semiconductor Components Industries, Llc | Initial decision-point circuit operation mode |
US9159420B1 (en) * | 2011-08-16 | 2015-10-13 | Marvell Israel (M.I.S.L) Ltd. | Method and apparatus for content addressable memory parallel lookup |
CN117095729B (en) * | 2023-10-17 | 2023-12-26 | 江苏帝奥微电子股份有限公司 | Single Pin input control code generation circuit for chip test mode |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60131480A (en) * | 1983-12-20 | 1985-07-13 | Sharp Corp | Multimode testing circuit |
JPS60142282A (en) * | 1983-12-28 | 1985-07-27 | Seiko Epson Corp | Semiconductor integrated circuit |
WO1996018910A1 (en) * | 1994-12-15 | 1996-06-20 | Intel Corporation | A method and apparatus for selecting modes of an integrated circuit |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58207648A (en) * | 1982-05-28 | 1983-12-03 | Toshiba Corp | Setting circuit for test mode of integrated circuit |
JPH0353316Y2 (en) * | 1987-03-18 | 1991-11-21 | ||
JP2561164B2 (en) * | 1990-02-26 | 1996-12-04 | 三菱電機株式会社 | Semiconductor integrated circuit |
US5161159A (en) * | 1990-08-17 | 1992-11-03 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory with multiple clocking for test mode entry |
JPH052052A (en) * | 1991-06-26 | 1993-01-08 | Nec Ic Microcomput Syst Ltd | Test signal generation circuit of semiconductor device |
US5198758A (en) * | 1991-09-23 | 1993-03-30 | Digital Equipment Corp. | Method and apparatus for complete functional testing of a complex signal path of a semiconductor chip |
JPH05256913A (en) * | 1992-03-11 | 1993-10-08 | Oki Electric Ind Co Ltd | Semiconductor integrated circuit device |
US5457400A (en) * | 1992-04-10 | 1995-10-10 | Micron Technology, Inc. | Semiconductor array having built-in test circuit for wafer level testing |
US6101457A (en) * | 1992-10-29 | 2000-08-08 | Texas Instruments Incorporated | Test access port |
US5798653A (en) * | 1995-04-20 | 1998-08-25 | Sun Microsystems, Inc. | Burn-in system for reliable integrated circuit manufacturing |
-
2000
- 2000-11-09 KR KR1020017009445A patent/KR100742406B1/en not_active IP Right Cessation
- 2000-11-09 EP EP00979546A patent/EP1157278B1/en not_active Expired - Lifetime
- 2000-11-09 DE DE60021705T patent/DE60021705T2/en not_active Expired - Lifetime
- 2000-11-09 WO PCT/EP2000/011115 patent/WO2001040816A1/en active IP Right Grant
- 2000-11-09 JP JP2001542225A patent/JP2003515747A/en active Pending
- 2000-11-29 US US09/725,418 patent/US6657451B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60131480A (en) * | 1983-12-20 | 1985-07-13 | Sharp Corp | Multimode testing circuit |
JPS60142282A (en) * | 1983-12-28 | 1985-07-27 | Seiko Epson Corp | Semiconductor integrated circuit |
WO1996018910A1 (en) * | 1994-12-15 | 1996-06-20 | Intel Corporation | A method and apparatus for selecting modes of an integrated circuit |
Non-Patent Citations (2)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 009, no. 296 (P - 407) 22 November 1985 (1985-11-22) * |
PATENT ABSTRACTS OF JAPAN vol. 009, no. 312 (P - 411) 7 December 1985 (1985-12-07) * |
Also Published As
Publication number | Publication date |
---|---|
KR100742406B1 (en) | 2007-07-24 |
JP2003515747A (en) | 2003-05-07 |
DE60021705T2 (en) | 2006-06-01 |
EP1157278B1 (en) | 2005-08-03 |
US6657451B2 (en) | 2003-12-02 |
US20010002790A1 (en) | 2001-06-07 |
KR20010101738A (en) | 2001-11-14 |
EP1157278A1 (en) | 2001-11-28 |
DE60021705D1 (en) | 2005-09-08 |
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