WO2001035524A1 - Schaltungsanordnung zur erzeugung von signalformen - Google Patents
Schaltungsanordnung zur erzeugung von signalformen Download PDFInfo
- Publication number
- WO2001035524A1 WO2001035524A1 PCT/EP2000/010990 EP0010990W WO0135524A1 WO 2001035524 A1 WO2001035524 A1 WO 2001035524A1 EP 0010990 W EP0010990 W EP 0010990W WO 0135524 A1 WO0135524 A1 WO 0135524A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- pulse width
- signal
- width modulation
- control
- voltage converter
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B28/00—Generation of oscillations by methods not covered by groups H03B5/00 - H03B27/00, including modification of the waveform to produce sinusoidal oscillations
Definitions
- the present invention relates to a circuit arrangement for generating certain waveforms, in particular waveforms that can be used for sound generation m (mobile) phones.
- circuit arrangement which can generate the signal described above with the desired signal shape.
- Known circuit arrangements use a relatively high constant supply voltage to derive the desired signal with the aid of a suitable voltage converter.
- the present invention has for its object to provide a circuit arrangement for generating waveforms, which can generate a signal with a desired waveform with relatively simple means and high reliability or accuracy.
- a voltage converter circuit is used, to which a first and a second control signal are supplied.
- the voltage converter circuit is one way configured both for increasing the voltage and for reducing the voltage, the output voltage of the voltage converter circuit being increased as a function of the first control signal and being reduced as a function of the second control signal.
- the voltage converter circuit is preferably controlled by adjusting the frequency and / or pulse width of the two control signals, the frequency and / or the pulse width of the control signals being regulated or set as a function of a reference signal in such a way that the desired signal shape is output at the voltage converter circuit occurs.
- the circuit arrangement according to the invention can be designed both in the form of an "open loop control" without feedback of the output voltage of the voltage converter circuit and in the form of a control loop ("closed loop control") with feedback of the output voltage of the voltage converter circuit.
- a reduction in the circuit complexity can be achieved, while in the second case the signal shape of the output signal of the voltage converter circuit can be generated more precisely.
- FIG. 1 shows a schematic block diagram of a circuit arrangement for generating signal forms according to an exemplary embodiment of the present invention
- FIG. 2 shows a possible circuit implementation of a voltage converter shown in FIG. 1, and
- FIG. 3A and 3B show waveforms m of the circuit arrangement shown in FIG. 1 to explain its operation.
- the voltage converter 4 is thus able to both increase and decrease its output voltage V ou ⁇ .
- the control of the voltage converter 4 for setting the signal shape of its output signal V 0D ⁇ takes place via two control signals V H and V L , the output voltage V 0U ⁇ being increased via the control signal V H and being lowered via the control signal V L.
- Each control signal V H or V L is generated by a corresponding pulse width modulation unit (PWM unit) 2 or 3, which sets the frequency and / or the pulse width of the respective pulse-shaped control signal as a function of setting signals that are specified by a control unit 1.
- PWM unit pulse width modulation unit
- the control unit 1 receives a reference signal V REF and compares it with the actual value of the output signal V 0 u ⁇ . Depending on the comparison result, pulse width setting signals pwml or pwm2 for setting the pulse width and / or frequency setting signals fl or f2 for setting the frequency of the control signals V H and V L , which are specified for the PWM unit 2 and the PWM unit 3, so that the PWM units 2 and 3 can generate the control signals V H and V L depending on the respectively specified setting values.
- the pulse width and / or the frequency of the pulse-shaped control signals V H and V L is regulated or set as a function of the reference signal V REF in such a way that the desired signal shape occurs at the output of the voltage converter, the output voltage V 0 u ⁇ being applied by pulses the input of the voltage converter 4 assigned to the control signal V H is increased, while it is decreased by pulses at the input assigned to the control signal V L.
- the in Fig. The circuit arrangement shown in FIG. 1 thus corresponds in principle to a delta-modulated DC / DC converter.
- FIG. 2 shows a possible implementation of the voltage converter 4, the voltage converter 4 being operated by a bipolar transistor Tl, T2, a coil L, a diode D, a capacitor C and resistors R1- operated with a supply voltage V 0 .
- R3 existing circuit is formed.
- the individual components are interconnected as shown in FIG. 2, the control signal V H via the
- Connection resistor Rl is applied to the base connection of the bipolar transistor Tl and the control signal V L via the connection resistor R2 to the base connection of the bipolar transistor T2.
- the output voltage V 0 u ⁇ can be tapped at the capacitor C.
- the output voltage V ou ⁇ is increased by V H pulses at the bipolar transistor T1, while it is reduced by V L pulses at the bipolar transistor T2.
- the control unit 1 can be used to set either the pulse width or the frequency or else both the pulse width and the frequency of the two control signals V H and V L , the functionality of the circuit arrangement shown in FIG. 1 being guaranteed in each of these cases.
- the two PWM units 2 and 3 are operated at a constant frequency, so that the control unit 1 and the PWM units 2 and 3 only provide the pulse width of the two control signals V H and V L is set.
- the pulse width can be set digitally with the help of counters that are operated at a higher clock rate.
- the frequency of the two PWM units 2 and 3 can be, for example, 128 kHz, while the counter clock is 10.368 MHz, so that 81 different pulse widths result for the two control signals V H and V L.
- the control unit 1 determines the value of the pulse width PW as a function of the difference signal e (k) as follows:
- C denotes the value of the capacitor shown in FIG. 2, L the value of the coil shown in FIG. 2, R the value of the resistor R3 shown in FIG. 2, 1 / T the frequency of the PWM units 2 and 3 or of the two control signals V H and V L and V 0 the value of the supply voltage shown in FIG. 2.
- the circuit complexity can be reduced if the two control signals V H and V L are generated without feedback, ie without evaluating the output voltage V 0ÜT of the voltage converter 4.
- R EC denotes the emitter-collector resistance of the bipolar transistor Tl.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00993060A EP1230729B1 (de) | 1999-11-09 | 2000-11-07 | Schaltungsanordnung zur erzeugung von signalformen |
DE50003478T DE50003478D1 (de) | 1999-11-09 | 2000-11-07 | Schaltungsanordnung zur erzeugung von signalformen |
JP2001537160A JP4112227B2 (ja) | 1999-11-09 | 2000-11-07 | 信号波形生成回路構造 |
US10/141,558 US7053676B2 (en) | 1999-11-09 | 2002-05-08 | Circuit arrangement for generating a signal having a specific waveform with an adjustable voltage level |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19953884.0 | 1999-11-09 | ||
DE19953884A DE19953884A1 (de) | 1999-11-09 | 1999-11-09 | Schaltungsanordnung zur Erzeugung von Signalformen |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/141,558 Continuation US7053676B2 (en) | 1999-11-09 | 2002-05-08 | Circuit arrangement for generating a signal having a specific waveform with an adjustable voltage level |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001035524A1 true WO2001035524A1 (de) | 2001-05-17 |
Family
ID=7928432
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2000/010990 WO2001035524A1 (de) | 1999-11-09 | 2000-11-07 | Schaltungsanordnung zur erzeugung von signalformen |
Country Status (5)
Country | Link |
---|---|
US (1) | US7053676B2 (de) |
EP (1) | EP1230729B1 (de) |
JP (1) | JP4112227B2 (de) |
DE (2) | DE19953884A1 (de) |
WO (1) | WO2001035524A1 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4765900B2 (ja) * | 2006-11-07 | 2011-09-07 | 船井電機株式会社 | ディスク装置 |
JP4803041B2 (ja) * | 2007-01-06 | 2011-10-26 | 船井電機株式会社 | ディスク装置 |
US8736363B2 (en) * | 2010-09-13 | 2014-05-27 | Cadence Ams Design India Private Limited | Circuit for optimizing a power management system during varying load conditions |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4353115A (en) * | 1980-03-28 | 1982-10-05 | Litton Systems, Inc. | Apparatus for synthesizing a sinusoidal output |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2066005A (en) * | 1979-12-21 | 1981-07-01 | Philips Electronic Associated | A tone generator for producing a tone signal from a digital signal |
EP0153423B1 (de) * | 1984-02-20 | 1988-02-10 | HONEYWELL BULL ITALIA S.p.A. | Treiberschaltung für einen Leistungs-FET |
JPS61277211A (ja) * | 1985-06-03 | 1986-12-08 | Toshiba Corp | 周波数変換装置 |
US4648019A (en) * | 1985-08-23 | 1987-03-03 | Gte Communication Systems Corporation | High efficiency ringing generator |
IT1227430B (it) * | 1988-07-22 | 1991-04-11 | Sgs Thomson Microelectronics | Circuito a pompa di carica a induttanza e capacita' per il pilotaggio di ponti a transistori mos di potenza. |
US5220204A (en) * | 1991-05-24 | 1993-06-15 | Rockwell International Corporation | Voltage and temperature compensated emitter-follower driver |
DE4213096A1 (de) * | 1992-04-21 | 1993-10-28 | Ind Automation Mikroelektronik | Spannungswandler |
JPH066229A (ja) * | 1992-06-23 | 1994-01-14 | Mitsubishi Electric Corp | D/a変換器 |
US6201417B1 (en) * | 1994-09-02 | 2001-03-13 | Semiconductor Components Industries, Llc. | Shaping a current sense signal by using a controlled slew rate |
JPH09140126A (ja) * | 1995-05-30 | 1997-05-27 | Linear Technol Corp | 適応スイッチ回路、適応出力回路、制御回路およびスイッチング電圧レギュレータを動作させる方法 |
US5892389A (en) * | 1997-06-03 | 1999-04-06 | Motorola, Inc. | Method and circuit for current limiting of DC-DC regulators |
US6614288B1 (en) * | 1998-05-20 | 2003-09-02 | Astec International Limited | Adaptive drive circuit for zero-voltage and low-voltage switches |
US6400126B1 (en) * | 1999-12-30 | 2002-06-04 | Volterra Semiconductor Corporation | Switching regulator with multiple power transistor driving voltages |
JP3521842B2 (ja) * | 2000-04-13 | 2004-04-26 | 株式会社デンソー | モータ駆動装置 |
US6650169B2 (en) * | 2001-10-01 | 2003-11-18 | Koninklijke Philips Electronics N.V. | Gate driver apparatus having an energy recovering circuit |
-
1999
- 1999-11-09 DE DE19953884A patent/DE19953884A1/de not_active Withdrawn
-
2000
- 2000-11-07 DE DE50003478T patent/DE50003478D1/de not_active Expired - Lifetime
- 2000-11-07 WO PCT/EP2000/010990 patent/WO2001035524A1/de active IP Right Grant
- 2000-11-07 JP JP2001537160A patent/JP4112227B2/ja not_active Expired - Fee Related
- 2000-11-07 EP EP00993060A patent/EP1230729B1/de not_active Expired - Lifetime
-
2002
- 2002-05-08 US US10/141,558 patent/US7053676B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4353115A (en) * | 1980-03-28 | 1982-10-05 | Litton Systems, Inc. | Apparatus for synthesizing a sinusoidal output |
Also Published As
Publication number | Publication date |
---|---|
US7053676B2 (en) | 2006-05-30 |
EP1230729B1 (de) | 2003-08-27 |
DE19953884A1 (de) | 2001-05-23 |
JP4112227B2 (ja) | 2008-07-02 |
US20030025534A1 (en) | 2003-02-06 |
DE50003478D1 (de) | 2003-10-02 |
EP1230729A1 (de) | 2002-08-14 |
JP2003514424A (ja) | 2003-04-15 |
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