WO2001028108A1 - Method and device for conserving power in a cdma mobile telephone - Google Patents
Method and device for conserving power in a cdma mobile telephone Download PDFInfo
- Publication number
- WO2001028108A1 WO2001028108A1 PCT/US2000/023374 US0023374W WO0128108A1 WO 2001028108 A1 WO2001028108 A1 WO 2001028108A1 US 0023374 W US0023374 W US 0023374W WO 0128108 A1 WO0128108 A1 WO 0128108A1
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- Prior art keywords
- clock source
- low power
- power consuming
- circuit
- system time
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 238000004891 communication Methods 0.000 claims abstract description 41
- 239000013078 crystal Substances 0.000 abstract description 4
- 230000008569 process Effects 0.000 description 13
- 230000006870 function Effects 0.000 description 10
- 230000008901 benefit Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000004622 sleep time Effects 0.000 description 3
- 230000002618 waking effect Effects 0.000 description 3
- 230000001413 cellular effect Effects 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- VJYFKVYYMZPMAB-UHFFFAOYSA-N ethoprophos Chemical compound CCCSP(=O)(OCC)SCCC VJYFKVYYMZPMAB-UHFFFAOYSA-N 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000000979 retarding effect Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7075—Synchronisation aspects with code phase acquisition
- H04B1/70756—Jumping within the code, i.e. masking or slewing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/02—Power saving arrangements
- H04W52/0209—Power saving arrangements in terminal devices
- H04W52/0261—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
- H04W52/0287—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level changing the clock frequency of a controller in the equipment
- H04W52/029—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level changing the clock frequency of a controller in the equipment reducing the clock frequency of the controller
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7075—Synchronisation aspects with code phase acquisition
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
- H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
- H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
- H04B2201/70707—Efficiency-related aspects
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Definitions
- the present invention relates to the field of wireless telecommunications. More particularly, the present invention relates to the field of Code Division Multiple Access (CDMA) system time.
- CDMA Code Division Multiple Access
- CDMA Code Division Multiple Access
- a user of a mobile station e.g. handset
- a mobile station and a base station of the Code Division Multiple Access system communicate by way of a wireless digital radio interface.
- the CDMA system also provides facsimile (fax) and multimedia communication capabilities.
- the CDMA system has the ability to operate both indoors and outdoors, which offers greater communication opportunities. For instance, the indoor operations include using it within homes, office spaces, shopping malls, hotels, and airports. Furthermore, the outdoor operations of the CDMA system include using it within suburban and city areas.
- a mobile or portable station typically operates under the limited power of an internal battery source.
- an internal battery source In order to extend the life of the internal battery source, it is important to optimize the power consumption within the mobile station during various modes of operation (e.g., sleep mode).
- the present invention provides a method and system for optimizing power consumption during sleep mode within a mobile station of the Code Division Multiple Access (CDMA) system. Furthermore, the present invention provides the above accomplishment while maintaining the CDMA system time during sleep mode.
- CDMA Code Division Multiple Access
- one embodiment of the present invention includes a method for conserving power during a low power mode of a communication device while dynamically maintaining a Code Division Multiple Access (CDMA) system time.
- the method includes the step of causing a mobile station to enter a low power mode and utilizing a low power consuming inaccurate clock source (e.g., 32 kHz) to dynamically maintain a CDMA system time while limiting power input to a high power consuming accurate clock source, e.g., a Voltage Control Temperature Control Crystal Oscillator (VCTCXO).
- a low power consuming inaccurate clock source e.g. 32 kHz
- VCTCXO Voltage Control Temperature Control Crystal Oscillator
- the method includes the step of utilizing an adjustment function to update a polynomial function (e.g., long PN) at a fixed increment which is part of the CDMA system time in order to minimize pilot signal acquisition time when the mobile station wakes up from the low power mode.
- a polynomial function e.g., long PN
- Another embodiment of the present invention also includes a circuit for conserving power during a low power mode of a communication device while dynamically maintaining a CDMA system time.
- the circuit includes a low power consuming clock source. Additionally, the circuit includes a timing circuit coupled to the low power consuming clock source in order to dynamically maintain a CDMA system time during a low power mode of a communication device. It should be appreciated that the timing circuit utilizes an adjustment function to update a polynomial function at a fixed increment which is part of the CDMA system time in order to minimize pilot signal acquisition time when the communication device wakes up from the low power mode.
- FIGURE 1 illustrates a general overview of a Code Division Multiple Access (CDMA) system in accordance with one embodiment of the present invention.
- CDMA Code Division Multiple Access
- FIGURE 2 is a block diagram of slotted paging mode circuitry used in accordance with one embodiment of the present invention.
- FIGURE 3 is a block diagram of master timer circuit of Figure 2 in accordance with one embodiment of the present invention.
- FIGURE 4 is a block diagram of the clock generator circuit of Figure 2 in accordance with one embodiment of the present invention.
- FIGURE 5 shows how the polynomial of the long PN state circuit of Figure 3 is defined in accordance with one embodiment of the present invention.
- FIGURE 6 is a flowchart of a method in accordance with one embodiment of the present invention.
- the present invention operates within a communication system known as the Code Division Multiple Access (CDMA) system which provides its users wireless voice communication.
- CDMA Code Division Multiple Access
- the CDMA system also provides facsimile (fax) and multimedia communication capabilities.
- the CDMA system has the ability to operate both indoors and outdoors, which offers greater communication opportunities. For instance, the indoor operations include using it within office spaces, homes, hotels, shopping malls and airports. Furthermore, the outdoor operations of the CDMA system include using it within _ _
- the CDMA system is well known by those of ordinary skill in the art.
- FIG. 1 illustrates a general overview of a Code Division Multiple Access (CDMA) system 100 in which the present invention operates.
- the two main components which comprise the CDMA system 100 are a base station device 102 and a mobile station device (e.g., 104).
- a base station device 102 When an embodiment in accordance with the present invention is implemented within the CDMA system 100, it typically resides within a mobile station 104 and/or a base station 102. Since optimizing power consumption within a mobile station 104 is very critical, the following detailed discussion about the present invention focuses on its implementation within mobile station 104. However, it is understood that the present invention operates equally well within base station 102 of the CDMA system 100.
- Base station 102 is a transmitter and receiver base station which can be implemented by coupling it into an existing network 114, such as a public telephone network. Implemented in this way, base station 102 enables the users of mobile stations 104-108 to communicate with each other and with the users of telephones 110 and 1 12, which are coupled by wire to the existing network 114.
- the information that is communicated between base station 102 and mobile stations 104-108 is the same type of information (e.g., voice/data etc.) that can normally be transferred and received over a public telephone wire network system.
- the CDMA system uses a wireless digital radio interface to communicate information between base station 102 and mobile stations 104-108.
- One embodiment in accordance with the present invention is used during a sleep mode of a mobile station (e.g., 104) in order to maintain continuous CDMA system time while using a 32 kHz clock source.
- a mobile station e.g., 104
- Material which is related to the present invention is described in co-pending US patent application serial number 09/322,240 which was filed on May 28, 1999, entitled “Device and Method for Maintaining Time Synchronous with a Network Master Time,” by McDonough et al., attorney docket number DOT1180 and is herein incorporated by reference as background material.
- FIG. 2 is a slotted paging mode circuit 200 used in accordance with one embodiment of the present invention.
- a mobile station e.g., 104
- a 32 kHz clock source is used within one embodiment in accordance with the present invention to maintain keypad and CDMA system time operations.
- accurately maintained CDMA system time in slotted mode is important in order to shorten slotted paging time.
- preparing for slotted paging mode is described in four separate processes: calibration, entering sleep mode, sleep mode, and exiting sleep mode. Calibration
- the Sync Channel is acquired (which is well known by those of ordinary skill in the art)
- software initiates a calibration process.
- a 32.768 kHz crystal is used as a low power consuming clock source 202.
- ms millisecond
- any length of time can be used during the calibration process.
- many different low power consuming clock sources with varying frequencies can be used for the low power consuming clock source 202 of the present embodiment.
- the calibration process of the present embodiment can take place at many different times.
- the present invention is also well suited to embodiments in which the calibration process occurs other than after the Sync Channel is acquired. The calibration process of the present embodiment is described in more detail below with reference to Figure 4.
- a processor 216 commands a clock generator circuit 206 to go to sleep.
- processor 216 programs the total sleep time into a counter of sleep timer circuit 214.
- clock generator circuit 206 sends a sleep signal 220 to master timer circuit 208 on a rising edge of a low power consuming clock signal 234 (e.g., 16.384 kHz).
- master timer circuit 208 updates the last short pseudonoise (PN) and long PN at chip rate (e.g., 1 .2288 MHz) and sends back a sleep request signal 222 to clock generator circuit 206.
- PN pseudonoise
- clock generator circuit 206 holds clock signal 226 to a low and sends a sleep grant signal 224 to master timer circuit 208. Additionally, clock generator circuit 206 switches clock signal 226 from a 16 times chip rate (e.g., 19.6608 MHz) to a low power consuming clock rate (e.g., 16.384 kHz). At the same time, clock generator circuit 206 enables sleep timer circuit 214. During the next step, master timer circuit 208 switches to sleep mode and sets the short PN, long PN, and frame index to be updated at 75 chips or PNs every clock cycle. It should be appreciated that the short PN, long PN, and frame index can be updated at any number of chips or PNs within the present embodiment. Furthermore, processor 216 turns off a high power consuming clock source 204, e.g., Voltage Control Temperature Control Crystal Oscillator (VCTCXO). In this manner, mobile station 104 enters sleep mode.
- VCTCXO Voltage Control Temperature Control Crystal Osc
- sleep mode most of the hardware blocks of slotted paging mode circuit 200 are inactive.
- the term sleep mode will be synonymous with low power mode.
- some hardware blocks continue to operate. That is, within the present embodiment sleep timer circuit 214, a keypad circuit 218, a portion of master timer circuit 208, and a portion of clock generator circuit 206 continue to operate during the sleep mode of mobile station 104.
- master timer circuit 208 continues to update the short PN, long PN, and frame index at 75 chips every low power consuming clock rate of clock signal 226.
- clock generator circuit 206 continues to send clock signal 226, which has a frequency of the low power consuming clock rate, to master timer circuit 208.
- Sleep timer circuit 214 of the present embodiment keeps track of the total sleep time using a counter.
- keypad circuit 218 continues to monitor keypad activities of mobile station 104 during sleep mode.
- any interrupt generated by keypad circuit 218 or sleep timer circuit 214 automatically enables high power consuming clock source 204 and wakes up the processor 216.
- processor 216 waits for stabilization of high power consuming clock source 204. During this step, processor 216 continues to operate at the low power consuming clock rate. Next, processor 216 removes the sleep command. As such, clock generator circuit 206 waits until a rising edge of the low power consuming clock signal and switches the demodulator clock node to 16 times chip rate.
- clock generator circuit 206 disables the sleep grant signal 224 and operates processor 216 at the high power consuming clock rate.
- sleep timer circuit 214 is disabled at the same time the sleep grant signal 224 is disabled.
- processor 216 reads the counter of sleep timer circuit 214 in order to figure out the total amount of sleep time. Once read, processor 216 calculates an estimated frequency error and adjusts for the frequency error by advancing/retarding master timer circuit 208.
- a searcher process is initiated in order to locate the pilot signal transmitted by base station 102.
- a finger is assigned to receive the paging message. In this fashion, mobile station 104 exits sleep mode.
- FIG 2 illustrates an exemplary slotted paging mode circuit 200 used during implementation of one embodiment in accordance with the present invention. It is appreciated that slotted paging mode circuit 200 of Figure 2 is exemplary only and that the present invention can operate within a number of different circuits.
- sleep mode timer (SMT) 214 operates in sleep mode, e.g., when sleep grant signal 224 from clock generator circuit 206 is high. It should be appreciated that sleep mode timer 214 of the present embodiment is a low power timer circuit.
- the low power consuming clock source 202 is an inaccurate clock source compared to the high power consuming clock source 204. It should be further appreciated that the high power consuming clock source 204 is a very accurate clock source compared to the low power consuming clock source 202.
- FIG. 3 is a block diagram of master timer circuit 208 in accordance with one embodiment of the present invention.
- a short pseudonoise (PN) index counter 306 and a long PN state 308 operate at a chip rate frequency.
- the chip rate frequency can be many different values in accordance with the present embodiment.
- the present embodiment is implemented using 16.384 kHz (75 chips) in order to update CDMA system time. In other words, every 16.384 kHz clock period, the short PN, the long PN, symbol and frame index shall advance 75 chips. It should be appreciated that the CDMA system time can be updated using many different frequencies in accordance with the present embodiment.
- the first rising edge of the low power consuming clock signal (e.g., 16.384 kHz) shall occur approximately 75 chips after the last high power consuming clock update.
- the last rising edge of low power consuming clock shall update 75 chips at the end of sleep mode.
- a state machine to control the interface between chip rate and the low power consuming clock source 202 is accomplished by monitoring the location of the signal of the high power consuming clock source 204. Before switching to the low power consuming clock source 202, master timer circuit 208 shall signal to clock generator circuit 206 that it is ready to go to sleep. The switching time shall be within 1 chip time.
- Sleep controller circuit 302 interfaces with clock generator circuit 206. When sleep command 220 is received from clock generator circuit 206, sleep controller circuit 302 shall monitor the last chip enable and immediately send a sleep request signal 222 to clock generator circuit 206. As soon as sleep grant signal 224 is granted from clock generator circuit 206, both a short PN index counter 306 and a long PN state 308 shall always be enabled. Also, the logic to control 75 chips loading shall be active.
- long PN states 308 is implemented within the present embodiment using a Linear Feedback Shift Register (LFSR) method.
- LFSR Linear Feedback Shift Register
- the polynomial for this long PN state can be defined by the IS-95 specification as shown in Figure 5, which is well known by those of ordinary skill in the art.
- registers at time n written in vector form S(n), can be expressed as:
- g(k) is defined as follows:
- transfer matrix G is solely determined by the fixed polynomial p(x) and is always full-rank, we can compute S(n - m) or S(n + m) directly from S(n) for any
- sleep controller circuit 302 is coupled to receive sleep signal 220 and sleep grant signal 224 from clock generator circuit 206 ( Figure 2). Furthermore, sleep controller circuit 302 is coupled to output sleep request signal 222 to clock generator circuit 206. Additionally, sleep controller circuit 302 is coupled to enable both short PN index counter circuit 306 and long PN state circuit 308. Moreover, sleep controller circuit 302 is coupled to receive a chip rate signal 324 from a decimator circuit 312. It should be appreciated that a frame indicator circuit 304 is coupled to also receive chip rate signal 324 from decimator circuit 312. Furthermore, decimator circuit 312 is coupled to receive Advance/Retard signals 320 from processor 318. It should be further appreciated that decimator circuit 312, frame indicator circuit 304, short PN index counter circuit 306, and long PN state circuit 308 are each coupled to receive clock signal 226 from clock generator circuit 206.
- the processor 318 is coupled to send signals to a master correct value circuit
- processor 318 is coupled to receive a long PN symbol signal 322 from a long PN mask 310.
- Long PN state circuit 308 is coupled to output signals to G 75 block 316 and long PN mask 310.
- G 75 block 316 is coupled to output signals to feed back into long PN state circuit 308.
- master correct value circuit 314 is coupled to output signals to short PN index counter circuit 306 and frame indicator circuit 304.
- Short PN index counter circuit 306 is coupled to output signal to a searcher, finger front ends (FFEs) and a modulator (all not shown).
- the low power consuming clock source 202 is not as accurate as the high power consuming clock source 204.
- calibration from time to time is implemented by the present embodiment.
- processor 216 specifies the calibration duration in terms of the number of low power consuming clock cycles (e.g., 16.384 kHz) by loading NSLOW register (not shown).
- NSLOW register not shown.
- calibration unit 406 starts to count the number of high power consuming clock source signal 232 periods on the first edge of the signal of the low power consuming clock source 202.
- the number of counted high power consuming clock periods is stored within NFAST register, which is read by processor 216.
- the processor 216 then passes this information to DEMOD master timer circuit 208 for CDMA system time correction upon wake-up.
- Flowchart 600 includes processes of the present invention which, in one embodiment, are carried out by electrical components under the control of computer readable and computer executable instructions. Although specific steps are disclosed in flowchart 600 of Figure 6, such steps are exemplary. That is, the present invention is well suited to performing various other steps or variations of the steps recited in Figure 6.
- a calibration process is performed in order to determine a frequency error between a first clock source (e.g., high power consuming clock source 204) and a second clock source (e.g., low power consuming clock source 202) of a communication device.
- a first clock source e.g., high power consuming clock source 20
- a second clock source e.g., low power consuming clock source 202
- the first clock source of the present embodiment can be implemented as an accurate clock having high power consumption.
- the second clock source of the present embodiment can be implemented as an inaccurate clock source having low power consumption.
- the communication device of the present embodiment can be a mobile station within a CDMA system.
- the communication device of the present embodiment can also be a base station within the CDMA system.
- the present embodiment causes the communication device to enter a low power sleep mode.
- the present embodiment limits the power input to the first clock source (e.g., high power consuming clock source 204).
- the present embodiment utilizes a signal (e.g., 16 kHz) from the second clock source to dynamically maintain CDMA system time.
- the present embodiment performs steps 610-614 simultaneously. Specifically, in step 610, the present embodiment utilizes an adjustment function to update at a fixed increment a long PN (a polynomial function) which is part of the CDMA system time in order to minimize pilot signal acquisition time when the communication device wakes up from the low power sleep mode. It should be appreciated that the fixed - -
- the fixed increment of the present embodiment can be preselected in order to facilitate efficient computation.
- the fixed increment can be measured by a certain number of chips (e.g., 37.5, 75, 1 12.5, etc.) or PNs.
- the fixed increment can be measured by an integer amount of chips (e.g., 75, 150, etc.) or PNs.
- the present embodiment updates at the fixed increment a short PN (a polynomial function) which is also part of the CDMA system time in order to minimize pilot signal acquisition time when the communication device wakes up from the low power sleep mode.
- a short PN a polynomial function
- the fixed increment of the present embodiment can be preselected in order to facilitate efficient computation. Additionally, the fixed increment can be measured by a certain number of chips (e.g., 37.5, 75, 112.5, etc.) or PNs. Furthermore, the fixed increment can be measured by an integer amount of chips (e.g., 75, 150, etc.) or PNs.
- the present embodiment updates at the fixed increment a frame index which is also part of the CDMA system time in order to minimize pilot signal acquisition time when the communication device wakes up from the low power sleep mode.
- the present embodiment determines whether the communication device is waking up from the low power sleep mode. If present embodiment determines that the communication device is not waking up from the sleep mode, the present embodiment proceeds to the beginning of step 608. If the present embodiment determines that the communication device is waking up from the sleep mode, the present embodiment proceeds to step 618. In step 618, the present embodiment increases the supply of power to the first clock source (e.g., high power consuming clock source 204) and subsequently switches from using the second clock source to using the first clock source. At step 620, the present embodiment corrects for any frequency error by performing an Advance/Retard function to the CDMA system time of the communication device. In step 622, the present embodiment performs a search in order to acquire a pilot signal transmitted by a base station of the CDMA system. After completing step 622, the present embodiment of flowchart 600 is exited.
- the first clock source e.g., high power consuming clock source 204
- the present invention provides a method and system for optimizing power consumption during sleep mode within a mobile station of a Code Division Multiple Access (CDMA) system.
- CDMA Code Division Multiple Access
- the present invention provides the above accomplishment while maintaining a CDMA system time during the sleep mode.
- the present embodiment provides the above accomplishments while utilizing, for example, a 32 kHz clock source during sleep mode.
- a 32 kHz clock source during sleep mode.
- One of the advantages is that it consumes very little power compared to a VCTCXO clock source.
- Another advantage is that the 32 kHz clock source is widely available, thereby causing them to be inexpensive.
- Still another advantage is that the 32 kHz clock source is small in size enabling a size reduction of mobile stations.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00959408A EP1138123A1 (en) | 1999-10-08 | 2000-08-25 | Method and device for conserving power in a cdma mobile telephone |
JP2001530214A JP2003511951A (en) | 1999-10-08 | 2000-08-25 | Method and apparatus for storing power in a CDMA mobile phone |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US41548499A | 1999-10-08 | 1999-10-08 | |
US09/415,484 | 1999-10-08 |
Publications (1)
Publication Number | Publication Date |
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WO2001028108A1 true WO2001028108A1 (en) | 2001-04-19 |
Family
ID=23645862
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/023374 WO2001028108A1 (en) | 1999-10-08 | 2000-08-25 | Method and device for conserving power in a cdma mobile telephone |
Country Status (3)
Country | Link |
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EP (1) | EP1138123A1 (en) |
JP (1) | JP2003511951A (en) |
WO (1) | WO2001028108A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002093769A1 (en) * | 2001-05-15 | 2002-11-21 | Qualcomm Incorporated | Fast slewing pseudorandom noise genereator |
GB2410652A (en) * | 2004-01-29 | 2005-08-03 | Nec Technologies | Timing control circuit and related method |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5910944A (en) * | 1997-02-28 | 1999-06-08 | Motorola, Inc. | Radio telephone and method for operating a radiotelephone in slotted paging mode |
WO1999031912A2 (en) * | 1997-12-12 | 1999-06-24 | Koninklijke Philips Electronics N.V. | Circuit for synchronizing cdma mobile phones |
JPH11220425A (en) * | 1997-11-13 | 1999-08-10 | Lsi Logic Corp | Method and system for hopping pn sequence |
-
2000
- 2000-08-25 EP EP00959408A patent/EP1138123A1/en not_active Withdrawn
- 2000-08-25 JP JP2001530214A patent/JP2003511951A/en active Pending
- 2000-08-25 WO PCT/US2000/023374 patent/WO2001028108A1/en not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5910944A (en) * | 1997-02-28 | 1999-06-08 | Motorola, Inc. | Radio telephone and method for operating a radiotelephone in slotted paging mode |
JPH11220425A (en) * | 1997-11-13 | 1999-08-10 | Lsi Logic Corp | Method and system for hopping pn sequence |
US5987056A (en) * | 1997-11-13 | 1999-11-16 | Lsi Logic Corporation | PN sequence hopping method and system |
WO1999031912A2 (en) * | 1997-12-12 | 1999-06-24 | Koninklijke Philips Electronics N.V. | Circuit for synchronizing cdma mobile phones |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002093769A1 (en) * | 2001-05-15 | 2002-11-21 | Qualcomm Incorporated | Fast slewing pseudorandom noise genereator |
US6735606B2 (en) | 2001-05-15 | 2004-05-11 | Qualcomm Incorporated | Multi-sequence fast slewing pseudorandom noise generator |
GB2410652A (en) * | 2004-01-29 | 2005-08-03 | Nec Technologies | Timing control circuit and related method |
Also Published As
Publication number | Publication date |
---|---|
EP1138123A1 (en) | 2001-10-04 |
JP2003511951A (en) | 2003-03-25 |
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