WO2001026431A1

WO2001026431A1 - A power oscillator for driving a discharge lamp

Info

Publication number: WO2001026431A1
Application number: PCT/GB2000/003793
Authority: WO
Inventors: Colin Julian Seymour
Original assignee: Central Research Laboratories Limited
Priority date: 1999-10-05
Filing date: 2000-10-04
Publication date: 2001-04-12
Also published as: GB2370168A; GB0206896D0; GB9923389D0

Abstract

A power oscillator for driving a discharge lamp includes a bridge inverter as an oscillating circuit. The control signals for the oscillating circuit devices are provided by a current controlled oscillator which is controlled by a signal from a phase locked loop. The oscillator typically operates at frequencies between 3 and 30 MHz, and is suitable for driving inductively coupled discharges.

Description

A POWER OSCILLATOR FOR DRIVING A DISCHARGE LAMP

The present invention relates to a power oscillator for driving a discharge lamp. It relates particularly, though not exclusively, to power oscillators for driving inductively coupled and /or electrodeless lamps.

A known electrical power oscillator designed to drive inductively coupled lamps has previously been described in GB 2,322,019, and is essentially as shown in Figure 1. Although this circuit is very efficient, there are areas in which improvements are desired, mainly for cost and size reduction: 1. Wound components: there are 4, plus the lamp winding. These are all custom- made, except possibly LI, therefore introduce significant costs and PCB area requirements.

2. The circuit must be adjusted by C_adj. This component is relatively expensive compared to a fixed capacitor, invokes production costs, and is susceptible to drift, for example if contaminated by sealant. Eventually excessive ageing can occur shortening the lifetime of the circuit. It is desirable to eliminate the tuning capacitor or allow the use of a trimming resistor instead, which is less costly.

US 5,519,285 "Electrodeless Discharge Lamp" cites 25 patent references. These patents mainly refer to the electrodeless lamp itself and methods for coupling RF energy into the plasma via an externally wound coil or coils.

Circuits for electrodeless discharge lamps differ somewhat from those for electroded lamps. US 5,252,891 describes an "uninterruptible fluorescent lamp circuit available for emergency lighting" comprised of a circuit which generates a high-frequency, high-voltage power, and a current-limiting circuit which can provide enough high-voltage power to activate the lamp without the need to use any conventional starter and stabiliser. Electrodeless lamps must be driven by an external coil, and to obtain sufficient coupling of energy into the plasma, magnetic induction must be used since electric field coupling would require impractical voltage levels to couple equivalent energy into the plasma through the lamp shell. Because of a frequency dependency, the use of magnetic coupling is not practical below a few MHz. Practical coupling circuits are probably limited at the low end to approximately 5 MHz. Frequencies of 10, 13.6 and 27.1 MHz are common.

Higher frequencies (e.g. 2450 MHz) may be used but are not cost-effective for lamps of the order of 10 W power levels. US 5,852,339 "Affordable

Electrodeless Lighting" describes a solid-state 2450MHz lamp (and see also US 4,070,630). For electroded lamps or low efficiency lamps, drive circuits may be operated at much lower frequencies corresponding to common practice in switching power supplies, i.e. up to about 1 MHz (for example US 4,712,170 describes an electroded neon tube power supply at 40kHz) or even at DC (for example US 5,675,220: "Power supply for vehicular neon light" describes a DC- DC converter utilising a Royer inverter circuit at 30 kHz to drive a neon bulb so as to avoid electromagnetic interference radiation from the bulb).

The principal general requirements for an inductive electrodeless lamp driver circuit are therefore, as described in GB 2,322,019:

1. Higher frequency operation - order of magnitude or more (compared with lamps having electrodes).

2. High frequency devices: e.g. fast switching, low distributed gate resistance power FETs. 3. Circuit must accommodate the reactive component of the gate impedance at the driving frequency (this is far more important at higher frequencies of operation).

4. A suitable phase shift response must be provided in the oscillator's feedback loop. 5. The circuit must generate sufficiently large electric field to strike the plasma discharge, then maintain a sufficiently high (but controlled) current in the induction coil to maintain an inductive plasma discharge. According to the present invention there is provided a power oscillator as specified in the claims.

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings, in which:- Figure 1 shows a known circuit arrangement,

Figure 2 shows a block diagram of a circuit arrangement according to the present invention,

Figure 3 shows the external drive circuit,

Figure 4 shows the pulse amplifier circuits, Figure 5 shows the phase locked loop (PLL system), and

Figure 6 shows the output voltage from the second op amp stage of the PLL loop filter.

The present invention is suitable for driving inductively coupled gas discharge lamps with air-cored coils, and due to the relatively low inductance and the frequency dependency of coupling between the magnetic field and plasma, the coils must be driven with frequencies of at least a few MHz. A frequency of 9- 10 MHz has been found a good compromise between the coil-plasma response which improves with frequency, and the capability of present-day low cost transistors to supply power, which declines with frequency.

The circuit must handle the particular characteristics of inductively coupled discharge lamps, that is to say a resonant circuit must generate a high order of voltage multiplication (Q) to strike the gas discharge and must therefore be driven from a circuit which has a low source impedance throughout the full RF cycle, and not be damaged by the high voltages and currents present, and must also continue to supply drive power efficiently when the initial Ε' mode shifts to Η' mode (power transferred by magnetic field to effective circulating current in the plasma) which results in an increase in effective loss resistance in the lamp resonant circuit. In any oscillator, assuming that a feedback loop can be identified and broken at some point in order to measure energy flow as flowing from an output node on one side of the break to an input node on the other side of the break, the phase shift through the whole network must be zero, (or n times 360 degrees where n is an integer), and the gain magnitude must be 1. These are the

Barkhausen criteria. In practical circuits, the unity gain results from the amplitude of oscillation growing until non-linear compression causes the gain magnitude to fall to unity.

The IC architecture is presently considered to be limited by the following constraints:

• No inductors

• Controlled elements (e.g. oscillators) must be voltage or current controlled

• No varactor diodes should be used due to impractical junction area at this frequency

• Available IC technology is assumed not capable of including final output stage power FETs

• FET driver transistors are assumed integrable with chip area approx. 1 mm square each.

The circuit arrangement in Figure 2 employs power FETs not as a self- oscillating circuit, but driven by an external gate driver circuit. This has the advantage of allowing the output coupling network to be optimised for maximum efficiency without loading by feedback coupling and without necessarily having to meet the restrictions placed on phase shifts by the Barkhausen criteria.

The diagram in Figure 2 shows the overall block diagram of the IC-model system, as built for demonstration purposes using a mixture of discrete components, MSI logic and analogue ICs, but using techniques that should translate readily to a fully integrated mixed-signal IC. The basic principle is that the lamp resonant circuit may be driven from the

12.8V supply without the need for a transformer by using a full bridge driver circuit (which is a well known principle but normally used at much lower frequencies, e.g. in audio amplifiers and motor drivers). If a higher voltage supply were available (24V or more), a half-bridge should be sufficient. Inductors in the feedback circuit are eliminated by using a phase locked loop (PLL) approach, which is suitable for eventual integration. Therefore, in this system the essential off-chip components using low-cost technology are believed to be:

• Four power FETs

• Lamp coil and one high voltage capacitor

• One high voltage, low capacity capacitor used for phase sampling - small enough in value to be printed on a PCB.

• Two power Schottky diodes

• Two capacitors used in the boosted Vdd generator

• Three capacitors used in the PLL loop filter

• Decoupling capacitors (fewer are required for a fully integrated IC compared to the experimental circuit)

The system functions as follows: Gate drive signals must be generated such that the top left FET and bottom right FET pair conduct, then alternately the top right FET and the bottom left FET pair conduct, in a 1:1 duty cycle at around 10 MHz. Due to the relatively high frequency, substantial gate drive current must be generated and the pulse widths and relative timings of the gate drive pulses are very important.

The whole system is clocked by a master oscillator which is also controlled by the PLL. The output of the master oscillator at around 20 MHz is divided by two to obtain a near 1:1 duty cycle set of complementary outputs at 10 MHz. The 10 MHz signal is then further divided by 2 and this 5 MHz signal is used via a pulse amplifier and capacitive voltage doubler circuit to generate a boosted Vdd power supply. This is necessary as the upper FETs must be driven on by a gate voltage which exceeds the normal Vdd by at least the gate-source on threshold bias voltage. Due to losses, the boosted Vdd is at about 50% above Vdd under operating load conditions, but this is sufficient. The 10 MHz clock is used to generate 4 phases of pulses of adjustable widths using one-shot pulse generators triggered from the edges of the clock. The pulses for the lower FETs, which are driven in common-source mode, are delayed by an adjustable delay so that diagonally opposing FETs turn on and off at the same time. The pulse widths and delays must be set such that both FETs vertically on each side of the bridge do not turn on simultaneously but alternate at a 1:1 duty cycle. The methods for achieving correct pulse width and delay settings in an IC will depend on the IC process used; clearly laser trimming is an option if normal tolerances are found to be insufficient to achieve the required signal timing. The timing is very important since the FET turn-on, turn-off and delay times at a 10MHz clock form a substantial fraction of the clock cycle, and delays in the pulse generator and amplifier circuits are also significant.

Figures 3 and 4 show the external drive circuit used for the IC architecture. Figure 3 shows the logic pulse generator circuits. Gl, G2, G3 and Dl form the current-controlled master oscillator. SI is a switch that allows demonstration of either pre-set frequency (via pre-set current source Q1/Q2/R1/VR1) or phase locking from the PLL section. G4 divides the frequency by 2, obtaining a 1:1 duty cycle at its Q and Q' outputs. A PWM input allows the lamp RF drive to be switched on and off, for example for dimming, where a variable duty cycle pulse at 100Hz might be used. G5, and G6, plus 3 inverters each, generate narrow pulses that are required to drive four one-shot pulse generators. For a description of these one-shot circuits, see J. A. Dean and J. P. Rupley, RCA application note ICAN-6267, 1978, Fig. 9. Their principal advantage is in being capable of generating very short pulse widths. The four phase pulse widths are adjustable by variable current sources controlled by VR2-VR5.

The pulses for the lower FET channels are each delayed through two additional logic inverters and a delay adjustment stage comprising variable R-C integrators (VR6, VR7) and another gate to square up the pulse.

The diagram in Figure 4 shows the pulse amplifiers, FET bridge, phase sampling, and voltage doubler circuits. In Figure 4, the Upper Left (UL) FET pulse amplifier and driver circuit is shown, the others are identical except for specific component value variations as stated. The pulse amplifier takes a TTL or

HCMOS logic signal input and amplifies it to the levels corresponding to the full

Vdd or Vddb voltage rails using a Schottky saturated switch (Ql, Dl) with a speed-up capacitor. Current drive capability is increased to that required by the power FET through two emitter follower stages Q2, Q3 and Q4, Q5. RD functions to suppress instability. An example of a standard commercial integrated FET driver circuit using an NPN bipolar process is the Unitrode UC1710 and there are also similar FET process devices on the market.

The driver transistors Q4, Q5 each require a chip area under 1 square mm and therefore the majority of the chip area demand from power output devices should be under 10 square mm.

The phase of RF current in the lamp resonator circuit is sampled by a low- value capacitor (2.5 pF) connected to the centre of the tuned circuit. It is important that the circuit runs at the resonant frequency of the lamp circuit, and the resonant voltage at this point is the most sensitive in terms of phase change as a function of resonant frequency. At resonance, the E field generated across the coil is maximised and the H field generated by the coil current is also maximised. There is a slight frequency shift when the lamp goes to H mode, reflected by an equivalent series resistance, however it is found in practice that reliable starting and adjustment for peak brightness can be achieved by setting a single relative phase condition. A diode/zener voltage clipping circuit squares the lamp phase signal to logic-compatible levels with fast rise and fall times.

The voltage doubler circuit uses two capacitors and two industry standard Schottky rectifier diodes rated at 1A, 30V. Initially, or when PWM is off but Vdd applied, the Vddb output is at Vdd minus two diode Vf drops, which is sufficient to generate RF output at reduced power even before the voltage doubler circuit has generated the boost voltage level after a number of cycles of 5MHz drive.

Figure 5 shows the PLL part of the system, in which a phase comparator circuit (Gl, G2, G3) is implemented using a conventional edge-triggered circuit capable of operating at around 10 MHz. The loop filter has a pre-filter stage (Rl, Cl, R2, C2) to suppress voltage spikes, a phase adjustment input controlled by VR1, and main filter response determined by OP2 with feedback components R8,

R9, RIO and C3 selected for optimum stability and a phase locking response fast enough to respond to PWM pulses down to 1ms duration. The output voltage from the loop filter at OP2 pin 6 is used to generate a current control input to the master oscillator through Rll and R12. R12 provides a nominal current level and the loop filter via Rll supplies a correction current about this nominal value.

Figure 6 shows an oscilloscope trace that illustrates how the PLL performs under PWM conditions. The waveform is the PLL loop filter output from the 2nd op amp stage; this shows the frequency correction applied to the master oscillator. Note that the phase lock is acquired in 0.25 ms, i.e. 0.25% of the PWM cycle time.

Phase lock is held for the duration of the 4.4ms on period and re-acquired for each

PWM on pulse.

A light output of 10500 lux was obtained close to the bulb for a 44% duty cycle at Vdd=12.8V, I(Vdd)ave=1.4A, and operating frequency of 9.35 MHz, under phase locking. This compares with the prior art oscillator/lamp circuit of

GB 2,322,019, which gave 11960 lux at close range for a 65% duty cycle at

V_dd=12.8V, I(V_dd )ave = 1.1 A, and operating frequency of 9.3 MHz.

The invention can provide the following potential advantages:

• Eliminating need for purpose built wound components or tuning capacitor.

• Interfaces to the same power supply voltage rail and pulse width modulation inputs as previous EDL circuits..

• Self-oscillating frequency is controlled by lamp tuned circuit and hence is more tolerant of drift in component values over time (compared with the sensitivity of the previous circuit to drift in the gate circuit tuning capacitor C_ad] and related wound components L_ad|andT₂).

• Lowered cost of manufacture.

• More easily modified for different types and sizes of lamp envelope.

Claims

1. A power oscillator for driving a discharge lamp, including a bridge inverter as an oscillating circuit, where the control signals for the oscillating circuit devices are provided by a current controlled oscillator which is controlled by a signal from a phase locked loop.

2. A power oscillator as claimed in claim 1 which operates at a frequency of between 3 and 30 MHz.