WO2001022239A1 - Method and device for communication between a rf signal identifying electronic circuit and a host system - Google Patents
Method and device for communication between a rf signal identifying electronic circuit and a host system Download PDFInfo
- Publication number
- WO2001022239A1 WO2001022239A1 PCT/FR2000/002609 FR0002609W WO0122239A1 WO 2001022239 A1 WO2001022239 A1 WO 2001022239A1 FR 0002609 W FR0002609 W FR 0002609W WO 0122239 A1 WO0122239 A1 WO 0122239A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- host system
- microcontroller
- communication
- circuit
- radio frequency
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
Definitions
- the present invention relates to a method and a device for communication between an electronic radio frequency identification circuit 5 and a host system.
- the electronic radio frequency identification circuit is commonly called a transponder.
- the present invention therefore aims to overcome the drawbacks of the prior art by proposing a method of communication between an electronic radio frequency identification circuit and a host system by a parallel port of the host system.
- the method of communication between a host system and an electronic identification circuit by radio frequency controlled by a microcontroller is characterized in that the microcontroller communicates with the host system via a PCMCIA bus. or CompactFlash with a parallel interface component connected to a master bus, the method comprising:
- an initialization step comprising a reading of a control register of the interface component by the host system to verify that the interface component is in the memory mode, - a step of confirming that the component has been taken into account interface by the host system,
- the value chosen to modify the control register short-circuits the serial interface of the parallel / parallel interface component, validates the address mode, validates the interrupts of the host system, and affects the I / O functionality. to the interface component by validating the interrupts.
- the parallel / parallel interface component comprises a first communication buffer, called reception, in which the host system can only write and in which the microcontroller can only read, and a second communication buffer, said d transmission, in which the host system can only read and in which the microcontroller can only write.
- the communication step comprises a step of writing the data comprising:
- the communication step comprises a step of reading the data comprising:
- the parallel / parallel interface component is of the CompactFlash type.
- the method comprises a step of processing and analyzing the data supplied by the radio frequency identification circuit comprising:
- a second object of the invention consists in proposing a communication device between an electronic radio frequency identification circuit and a host system by a parallel port of the host system.
- the communication device between the electronic radio frequency identification circuit and a host system is characterized in that it comprises a parallel interface component programmable by control registers to communicate with the system.
- host according to a PCMCIA type parallel input / output system protocol and means for reading and writing status registers to avoid access conflicts between the two buffers allowing communication between the host system and intelligent logic controlling the operation of the electronic identification circuit by radio frequency.
- the intelligent logic is a microcontroller receiving on one of its interrupt inputs the output signal of the identification circuit by radio frequency and sending by one of its serial outputs on the serial input of the radio frequency identification circuit, the information exchanged by radio frequency.
- the microcontroller comprises means of writing, in a control register, information allowing a host system to consider the electronic assembly connected to its PCMCIA port as a memory; then at the end of a determined time of occurrence of a determined event, means of modifying the information written in the register CR to make the circuit take into account by the host system as a parallel input / output device.
- the interface circuit is arranged on one side of a multilayer printed circuit ensuring the electrical connections between on the one hand the various electronic components and on the other hand the bomier of the CompactFlash type and the coil constituting the radiofrequency transmitting antenna; the electronic radio frequency identification circuit and the microcontroller being arranged on the opposite face of the multilayer printed circuit.
- the printed circuit has a dimension corresponding to CompactFlash memories of type I or II.
- connection terminal block of the interface circuit with the external world and compatible CompactFlash and the printed circuit is encapsulated in a housing with a width of the order of 3mm, a length of the order of 4mm and thickness less than 3.5 millimeters.
- the multilayer printed circuit essentially comprises three conductive layers of determined thickness, including a double-sided layer and two layers of insulator of determined thickness, the thickness of the upper and lower conductive layers being between 7 and 11 ⁇ m. , the thickness of the insulating layer being between 45 and
- FIGS. 1A and 1B represent a diagram of an electronic device implementing the communication method according to the invention
- FIG. 2 shows a diagram of the parallel / parallel interface component used in the electronic device.
- FIG. 3 shows an embodiment of the multilayer circuit.
- the communication method is used to provide communication between a radio frequency identification circuit and a host system (1), when the identification circuit is connected to the host system, via a parallel interface.
- FIGS. 1A and 1B represent a diagram of an electronic device implementing the communication method according to the invention.
- the host system (1) is a computer, for example portable, comprising a processor of PC type and the parallel port (100) used to connect the electronic device is of PCMCIA type or , preferably, of the CompactFlash type (trademark registered by the company CompactFlash Association).
- the CompactFlash standard comes from the PCMCIA standard but includes its own characteristics while being compatible with the PCMCIA standard.
- the electronic device according to the invention is, in an alternative embodiment, electrically and mechanically compliant with the CompactFlash standard but can be connected to a PCMCIA port by means of a commercially available CompactFlash / PCMCIA adapter.
- the host system (1) also includes a specific PCMCIA port controller.
- the electronic circuit shown in FIGS. 1A, 1B is mounted on a multilayer printed circuit with components on each of the two opposite faces of the printed circuit.
- the printed circuit a few tenths of a millimeter thick has the surface of a matchbox of the order of 3 cm by 4 cm).
- On this printed circuit board are interconnected by the conductive tracks of the multilayer circuit, the components performing the functions described below.
- FIG. 3 represents an exemplary embodiment of the multilayer circuit.
- the circuit essentially comprises three conductive layers (1010 to 1012) of determined thickness including a double face layer (1011) and two layers of insulator (1020, 1021) of determined thickness.
- the upper (1010) and lower (1012) conductive layers have a thickness of between 7 and 11 ⁇ m, and chosen to be equal to 9 ⁇ m.
- Each insulating layer (1020, 1021) has a thickness between 45 and 55 ⁇ m and chosen equal to 50 ⁇ m.
- the double-sided conductive layer (1011) is located between the two layers (1020, 1021) of insulation and has a thickness between 45 and 55 ⁇ m and chosen equal to 50 ⁇ m.
- the conductive layer (1011) double face is, for example, made from a material having two copper-colored faces, for example, marketed under the reference FR4 by the French company NELCO.
- the total thickness of the multilayer circuit, including the metallization is between 200 and 240 ⁇ m and is chosen to be equal to 227 ⁇ m.
- the insulator chosen is, for example, an epoxy resin, for example sold under the reference Preg 104 by the American company ARLON.
- a first radio frequency identification component (10) consists, for example, of the component marketed by Philips under the reference HTRC110, any other similar component that can also be used. This component is mounted on the same face of the printed circuit with a microcontroller (20) constituted, for example, by a component sold by Intel under the reference 89C51, any other similar component that can also be used.
- a third component (30) constituting an interface circuit is constituted, for example, by the circuit marketed by Texas Industry under the reference TL16PC564B, any other similar component that can also be used.
- This circuit (30) is mounted on the opposite face of the printed circuit and is connected, on the one hand to the PCMCIA terminal block (50), and on the other hand, through the layers of the printed circuit, to the bus (21) of the microcontroller (20). Finally, the midpoint M between a resistor (13) and a plurality of capacitors (15) connected in series between a transmission output and a reception input RX, is connected by a flexible wire to a coil (11) whose other end is also connected by a flexible wire to a second TX transmission output.
- the radiofrequency identification component or circuit (10) is connected to a receiving transmitter probe comprising the coil (11).
- the circuit (10) is controlled by the microcontroller (20) to which it is connected.
- the microcontroller (20) is connected to the female connector (50) compatible with the complementary male connector (100, Fig. 2) of the PCMCIA port, via a parallel / parallel interface component (30).
- the interface component (30) includes the data bus (21) and an address bus (31).
- the electronic device also includes a frequency divider (40), and a 32 MHz clock (60) connected to the interface component (30) and through a divider (40) to the microcontroller (20). Communication between the host system (1) and the electronic device is carried out by an interface (30).
- this interface (30) The particularity of this interface (30) is that the host system (1) and the microcontroller (20) are masters of this interface. Indeed, in principle, a microcontroller (20) must be master of its bus (21) which is connected to this interface (30). Likewise, the processor of the host system is master of its peripherals and therefore of the PCMCIA port to which the interface (30) connects the electronic device. Consequently, the connection between the microcontroller (20) and the processor of the host system (1) is carried out via a master / master bus.
- a PCMCIA type port can operate in three modes.
- the first operating mode is memory mode and allows connection and access to an external memory.
- the second mode is the input / output mode in which information can be exchanged between the host system and an electronic device connected to the PCMCIA port.
- the third mode is IDE mode in which it is possible to connect a disk to the host system via the PCMCIA port.
- the port (100) when connecting any equipment to the PCMCIA port (100) of the host system, the port (100) must operate in the first mode during the phase of initialization and recognition of the port (100) by the controller specific to the host system.
- the PCMCIA port (100) of this device must be configured as if the device were a memory, for a determined duration of the order of twenty milliseconds.
- the microcontroller (20) changes the state of the configuration of the interface component (30) to switch the signals of the connector pins (50) in a state causing the host system to interpret that the device connected to the PCMCIA port (100) is operating in the input / output mode.
- the interface component (30) chosen is initially provided for controlling a serial line and for this purpose comprises two communication buffers (3002, 3003, Fig.
- the identification circuit (10) is in fact a base for reading and writing in a transponder.
- the circuit (10) comprises, between its TX transmission terminals, a resonant circuit comprising in series a coil (11) and capacitors (15) serving as a probe by reacting to variations in the charge of its environment.
- a resonant circuit comprising in series a coil (11) and capacitors (15) serving as a probe by reacting to variations in the charge of its environment.
- At the terminals of the coil (11) there is a large voltage which oscillates at a frequency of the order of 125 kHz.
- the maximum values of the voltage will fluctuate slightly. It is this fluctuation which is detected and processed by the identification circuit (10).
- the voltage across the coil (11) is applied to an RX input of the identification circuit (10).
- the output of the coil (11) comprises a resistor (13) in series.
- the voltage is then processed, in particular by rectification, to form a rectangular signal consisting of a succession of more or less long pulses and representative of the variation of the maximum value of voltage of the coil (11) over time.
- This signal is generated on an output (12) of the identification circuit (10) and applied to an interrupt input (22) of the microcontroller (20) to analyze this signal.
- Signal analysis consists of measure the time intervals between a rising edge and a successive falling edge of the signal, I then compare the values of the intervals obtained, with the expected values stored in a table in the memory of the microcontroller (20) and corresponding to a determined protocol of Manchester type.
- the microcontroller (20) comprises a specific register (TIMER) activated, either on a rising edge or on a falling edge.
- TIMER specific register
- the register (TIMER) is consulted and the activation sensitivity of the register is reversed.
- the register is consulted as soon as a falling edge is detected and consultation of the register makes it possible to know the time interval between the rising edge and the next falling edge.
- the sensitivity of the register is again inverted for a new detection of the next rising edge. The comparison between the value of the measured time intervals and the expected time values makes it possible to determine the value of a data bit.
- the value of this bit is then transmitted on the bus (21) to the transmit buffer (TE, Fig. 2) of the interface component (30), then to the host system (1) via the connectors (50, 100) PCMCIA.
- the identification circuit (10) also receives on an input (14) control signals from the microcontroller (20). These signals are transmitted over a serial link synchronized with a validation clock (SCLK). These control signals are interpreted by the identification circuit (10), for example, as the signal for the initiation of an identification action causing the transmission by the circuit (10) of a train of signals transmitted by the coil (11) to the integrated circuit (3) connected to an antenna (4) coupled by electromagnetic waves to the coil (11).
- This circuit (2) extracts from the signal emitted by the coil (1 1) its power supply and returns by its antenna (4) the information requested and contained in the memory of the integrated circuit (3).
- the interface component (30) used is used in the prior art to control serial lines, for example, for an external modem. According to the invention, this component interface is programmed differently to allow the acquisition of data from the identification circuit (10).
- the electronic device comprising the interface component (30) will be seen as a universal asynchronous transceiver (UART: Universal, asynchronous, receiver transmitter).
- UART Universal, asynchronous, receiver transmitter
- this interface component (30) comprises two sections (300, 301).
- a first section (300, UART) offers a universal asynchronous transmitter-transmitter interface
- a second section (301, PCMCIA) offers a PCMCIA interface.
- the UART interface includes two communication buffers (3002, 3003) and a plurality of registers (3001, 3004) including a control register (3004, CR).
- the buffers (3002, 3003) form, for example a memory structure of the FOFI (First In, First Out) type of the PCMCIA section comprising a plurality (3011) of eight configuration registers (CCRO to CCR7 ), and registers (3010, CIS) defining the personality and functionality of the electronic device connected to the interface component.
- the two communication buffers (3002, 3003) initially used to control a serial line, are used to solve the problem of conflicting access to the bus (21, fig. 1A and 1B) by using the first buffer TR in reception between the circuit (30) and the host system (1).
- the transmission buffer TE to the host system can only be accessed in write mode by the microcontroller (20) and in read mode by the host system (1).
- the microcontroller (20) programs the interface component (30) by modifying the value of the control register (CR) to program it at a determined value, for example at the value 2E in hexadecimal, for the duration of initialization of the PCMCIA controller of the host system.
- the microcontroller (20) also monitors the possible modification of a determined configuration register (CCR0).
- the host system (100) has taken into account the presence of an interface element (30) on its PCMCIA port, it modifies the content of the determined configuration register (CCR0).
- the microcontroller (20) during this phase, is in a waiting loop.
- the microcontroller (20) of the electronic device detects a modification of this configuration register (CCR0), it again programs the interface component (30) to modify the value of the control register (CR).
- the new determined hexadecimal value will be fixed, for example at 8E.
- This value indicates to the host system (100) that, firstly, the serial interface of the interface component (30) is short-circuited, secondly that the address mode is validated, thirdly that the interrupts of the host system are validated, and that the personality of the circuit connected to the port is of the input / output type with validation of interruptions.
- This value is then consulted by the host system (100) which then consults the registers (CIS, Card information structure). These registers contain up to 256 8-bit standardized information for declaring the electronic device according to the invention, as an asynchronous transmitter-transmitter. From this moment, the host system (100) and the microcontroller (20) have free access to the communication buffers (3002, 3003) of the interface component (30).
- a first communication buffer (3002, TR), called reception, is only accessible in writing (3110) by the host system and only in reading (3100) for the microcontroller (20 ).
- the second communication buffer (3003, TE), called transmission, is accessible only in reading (31 1 1) by the host system (100), and only in writing (3101) by the microcontroller (20).
- the management of the occupation of the communication buffers (TR, TE) is carried out by functions of the circuit (30) initially used to control a serial line. This management is carried out by specific registers (LSR, MCR) of the UART section of the interface component. Initially, these registers were used to give the state of the buffers.
- the microcontroller (20) to verify that the reception buffer (TR) is not empty, consults a first specific bit, for example the THRE bit (Transmit and Hold Register Empty: transmission and maintenance of the empty register ), a first determined register, for example the LSR register (Life Status Register). If this first bit (THRE) is, for example, equal to 1, then the microprocessor program (20) concludes that it can read the content of the reception buffer (TR). This first bit (THRE) is also consulted by the host system (100) before performing a write operation in the reception buffer (TR). To avoid losing data, the content of the reception buffer must be read before writing new data.
- a first specific bit for example the THRE bit (Transmit and Hold Register Empty: transmission and maintenance of the empty register ), a first determined register, for example the LSR register (Life Status Register). If this first bit (THRE) is, for example, equal to 1, then the microprocessor program (20) concludes that it can read the content of the reception buffer (TR). This first bit (THRE
- the microcontroller (20) when the microcontroller (20) has read the data contained in the reception buffer (TR), it sets the value of the first bit (THRE), for example, to zero, which indicates to the host system that the data previously written have been read. Otherwise, if this first THRE bit is, for example, at 1, the program of the host system waits and comes periodically to read this bit to ensure that it has passed, for example to zero, before sending new data. to the reception buffer TR. Similarly, before writing to the send buffer (TE), the microprocessor (20) consults a second determined bit, for example the RTS bit (Request to Send), from a second determined register. , for example the Modem Control register (MCR).
- MCR Modem Control register
- this second bit (RTS) is, for example, equal to 1, the microprocessor (20) initiates a write procedure in the transmission buffer (TE) and modifies the value of the second bit (RTS) so that for example, it is zero.
- This second bit (RTS) is also consulted by the host system (1) before performing a read operation in the transmit buffer (TE). Indeed, to avoid reading erroneous data, it is necessary to ensure that the transmission buffer is not empty.
- the second bit (RTS) is zero, the host system (1) reads the TE transmission buffer and sets this bit (RTS) to 1, thus indicating to the microcontroller (20) that it can write to the TE transmission buffer.
- the interface circuit presents a risk of simultaneous access to all of the shared registers, in particular the first or the second determined bit of the LSR or RTS registers.
- This conflict is managed by the arbitration logic of the interface component (30) and decides that ultimately it is the host system which wins the arbitration when a simultaneous write access occurs on the same register of the part of the microcontroller (20) and the host system (100).
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00964331A EP1141844A1 (en) | 1999-09-21 | 2000-09-20 | Method and device for communication between a rf signal identifying electronic circuit and a host system |
AU75291/00A AU7529100A (en) | 1999-09-21 | 2000-09-20 | Method and device for communication between a rf signal identifying electronic circuit and a host system |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9911782A FR2798797B1 (en) | 1999-09-21 | 1999-09-21 | METHOD AND DEVICE FOR COMMUNICATING BETWEEN AN ELECTRONIC RADIO FREQUENCY IDENTIFICATION CIRCUIT AND A HOST SYSTEM |
FR99/11782 | 1999-09-21 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001022239A1 true WO2001022239A1 (en) | 2001-03-29 |
Family
ID=9550075
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2000/002609 WO2001022239A1 (en) | 1999-09-21 | 2000-09-20 | Method and device for communication between a rf signal identifying electronic circuit and a host system |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1141844A1 (en) |
AU (1) | AU7529100A (en) |
FR (1) | FR2798797B1 (en) |
WO (1) | WO2001022239A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2394323B (en) * | 2002-10-14 | 2004-09-22 | Elan Digital Systems Ltd | High-throughput uart interfaces |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5765027A (en) * | 1994-09-26 | 1998-06-09 | Toshiba American Information Systems, Inc. | Network controller which enables the local processor to have greater access to at least one memory device than the host computer in response to a control signal |
US5804811A (en) * | 1994-06-21 | 1998-09-08 | Sony Chemicals Corporation | Non-contacting RF-ID card for wide voltage range input |
-
1999
- 1999-09-21 FR FR9911782A patent/FR2798797B1/en not_active Expired - Fee Related
-
2000
- 2000-09-20 WO PCT/FR2000/002609 patent/WO2001022239A1/en not_active Application Discontinuation
- 2000-09-20 EP EP00964331A patent/EP1141844A1/en not_active Withdrawn
- 2000-09-20 AU AU75291/00A patent/AU7529100A/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5804811A (en) * | 1994-06-21 | 1998-09-08 | Sony Chemicals Corporation | Non-contacting RF-ID card for wide voltage range input |
US5765027A (en) * | 1994-09-26 | 1998-06-09 | Toshiba American Information Systems, Inc. | Network controller which enables the local processor to have greater access to at least one memory device than the host computer in response to a control signal |
Non-Patent Citations (3)
Title |
---|
"DATASHEET HTRC110 Hitag Reader Chip", January 1999, PHILIPS, EINDHOVEN, NL, XP002139555 * |
"TL26PC564B, TL16PC564BLV PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER", February 1998, TEXAS INSTRUMENTS, XP002139556 * |
DON ANDERSON: "PCMCIA SYSTEM ARCHITECHTURE", June 1995, MINDSHARE, INC., READING, MASSACHUSETTS, ISBN: 0-201-40991-7, XP002139554 * |
Also Published As
Publication number | Publication date |
---|---|
FR2798797B1 (en) | 2002-02-22 |
AU7529100A (en) | 2001-04-24 |
FR2798797A1 (en) | 2001-03-23 |
EP1141844A1 (en) | 2001-10-10 |
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