WO2001017128A3 - Synchronous delay generator - Google Patents

Synchronous delay generator Download PDF

Info

Publication number
WO2001017128A3
WO2001017128A3 PCT/US2000/023951 US0023951W WO0117128A3 WO 2001017128 A3 WO2001017128 A3 WO 2001017128A3 US 0023951 W US0023951 W US 0023951W WO 0117128 A3 WO0117128 A3 WO 0117128A3
Authority
WO
WIPO (PCT)
Prior art keywords
signal
clock
sample times
sample
delay
Prior art date
Application number
PCT/US2000/023951
Other languages
French (fr)
Other versions
WO2001017128A2 (en
Inventor
Maurizio Di Veroli
Ayal Bar-David
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Priority to AU70966/00A priority Critical patent/AU7096600A/en
Publication of WO2001017128A2 publication Critical patent/WO2001017128A2/en
Publication of WO2001017128A3 publication Critical patent/WO2001017128A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0029—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/14—Relay systems
    • H04B7/15—Active relay systems
    • H04B7/204—Multiple access
    • H04B7/212—Time-division multiple access [TDMA]
    • H04B7/2125—Synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0041—Delay of data signal

Abstract

A method for generating a variable delay of a signal (28), including: providing a clock (50) indicating a sequence of sample times at regular intervals and receiving a sequence of input samples (41) representing input values of the signal at respective sample times indicated by the clock. The method further includes determining the delay (40, 46) with a temporal resolution substantially finer than the clock interval to be applied to the signal at each of the respective sample times. For each of the sample times, responsive to the respectively-determined delay, one or more of the input samples are processed so as to generate a corresponding output sample (43) representing a delayed output value of the signal at the sample time.
PCT/US2000/023951 1999-08-31 2000-08-30 Synchronous delay generator WO2001017128A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU70966/00A AU7096600A (en) 1999-08-31 2000-08-30 Synchronous delay generator

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US38714099A 1999-08-31 1999-08-31
US09/387,140 1999-08-31

Publications (2)

Publication Number Publication Date
WO2001017128A2 WO2001017128A2 (en) 2001-03-08
WO2001017128A3 true WO2001017128A3 (en) 2001-09-07

Family

ID=23528643

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/023951 WO2001017128A2 (en) 1999-08-31 2000-08-30 Synchronous delay generator

Country Status (2)

Country Link
AU (1) AU7096600A (en)
WO (1) WO2001017128A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3997772A (en) * 1975-09-05 1976-12-14 Bell Telephone Laboratories, Incorporated Digital phase shifter
US4907247A (en) * 1988-02-23 1990-03-06 Nec Corporation Satellite delay simulation system
JPH04288747A (en) * 1990-12-28 1992-10-13 Sony Corp Delay simulator for digital line
EP0639347A1 (en) * 1992-01-14 1995-02-22 Yokogawa Medical Systems, Ltd Digital phase shifter

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3997772A (en) * 1975-09-05 1976-12-14 Bell Telephone Laboratories, Incorporated Digital phase shifter
US4907247A (en) * 1988-02-23 1990-03-06 Nec Corporation Satellite delay simulation system
JPH04288747A (en) * 1990-12-28 1992-10-13 Sony Corp Delay simulator for digital line
EP0639347A1 (en) * 1992-01-14 1995-02-22 Yokogawa Medical Systems, Ltd Digital phase shifter

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
LIU G -S ET AL: "PROGRAMMABLE FRACTIONAL SAMPLE DELAY FILTER WITH LAGRANGE INTERPOLATION", ELECTRONICS LETTERS,GB,IEE STEVENAGE, vol. 26, no. 19, 13 September 1990 (1990-09-13), pages 1608 - 1610, XP000106903, ISSN: 0013-5194 *
MURPHY N P ET AL: "IMPLEMENTATION OF WIDEBAND INTEGER AND FRACTIONAL DELAY ELEMENT", ELECTRONICS LETTERS,GB,IEE STEVENAGE, vol. 30, no. 20, 29 September 1994 (1994-09-29), pages 1658 - 1659, XP000474909, ISSN: 0013-5194 *
PATENT ABSTRACTS OF JAPAN vol. 017, no. 097 (E - 1326) 25 February 1993 (1993-02-25) *

Also Published As

Publication number Publication date
WO2001017128A2 (en) 2001-03-08
AU7096600A (en) 2001-03-26

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