WO2001016773A1 - System and method for initiating a serial data transfer between two clock domains - Google Patents
System and method for initiating a serial data transfer between two clock domains Download PDFInfo
- Publication number
- WO2001016773A1 WO2001016773A1 PCT/US2000/007695 US0007695W WO0116773A1 WO 2001016773 A1 WO2001016773 A1 WO 2001016773A1 US 0007695 W US0007695 W US 0007695W WO 0116773 A1 WO0116773 A1 WO 0116773A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- clock
- ratio
- bit
- clock rate
- bits
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
- G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
Definitions
- This invention relates to data communications, and more particularly to a system and method for initiating a senal data transfer between a first device clocked accordmg to a first clock and a second device clocked accordmg to a second clock.
- processors are each coupled to a b ⁇ dge through separate high speed connections, which m one embodiment each mclude a pair of unidirectional address buses with respective source-synchronous clock lmes and a bi-directional data bus with attendant source-synchronous clock lmes
- System memory and graphics may also be coupled to the b ⁇ dge, as well as an input/output bus.
- the method also provides one or more ratio bits over the senal lme after the start bit
- the ratio bits mdicate the ratio between the second clock rate and the first clock rate.
- the method receives the one or more start bits Usmg a transition between the first state and the second state evident m receivmg each of the start bits, the method receives the one or more ratio bits.
- the method also includes receiving a remainder of the serial data stream at appropriate intervals of the second clock rate.
- FIG. 1 a block diagram of an embodiment of a generalized computer system 100 is illustrated.
- a first processor 110A and a second processor HOB each couple to a bridge 130 through separate processor buses. Both the first processor 110A and the second processor HOB are preferably configured to perform memory and I/O operations using their respective processor buses.
- processors 110A and HOB implement the x86 instruction set architecture. Other embodiments may implement any suitable instruction set architecture.
- the bridge 130 is further coupled to a memory 140.
- the memory 140 is preferably configured to store data and instructions accessible to both the first processor 110A and the second processor HOB, as well as other system devices.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001520658A JP4630512B2 (en) | 1999-08-31 | 2000-03-23 | System and method for initiating serial data transfer between two clock domains |
EP00919559A EP1214662B1 (en) | 1999-08-31 | 2000-03-23 | System and method for initiating a serial data transfer between two clock domains |
DE60002589T DE60002589T2 (en) | 1999-08-31 | 2000-03-23 | SYSTEM AND METHOD FOR INITIALIZING SERIAL DATA TRANSFER BETWEEN TWO CLOCK AREAS |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/386,650 | 1999-08-31 | ||
US09/386,650 US6393502B1 (en) | 1999-08-31 | 1999-08-31 | System and method for initiating a serial data transfer between two clock domains |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001016773A1 true WO2001016773A1 (en) | 2001-03-08 |
Family
ID=23526484
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/007695 WO2001016773A1 (en) | 1999-08-31 | 2000-03-23 | System and method for initiating a serial data transfer between two clock domains |
Country Status (6)
Country | Link |
---|---|
US (3) | US6393502B1 (en) |
EP (1) | EP1214662B1 (en) |
JP (1) | JP4630512B2 (en) |
KR (1) | KR100734528B1 (en) |
DE (1) | DE60002589T2 (en) |
WO (1) | WO2001016773A1 (en) |
Families Citing this family (47)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4091195B2 (en) * | 1999-02-08 | 2008-05-28 | 富士通株式会社 | Interface control apparatus and interface control method |
US6535565B1 (en) * | 1999-03-16 | 2003-03-18 | Level One Communications, Inc. | Receiver rate converter phase calculation apparatus and method |
US6584575B1 (en) * | 1999-08-31 | 2003-06-24 | Advanced Micro Devices, Inc. | System and method for initializing source-synchronous data transfers using ratio bits |
US7047196B2 (en) | 2000-06-08 | 2006-05-16 | Agiletv Corporation | System and method of voice recognition near a wireline node of a network supporting cable television and/or video delivery |
US7039074B1 (en) * | 2000-09-14 | 2006-05-02 | Agiletv Corporation | N-way demultiplexer |
KR100369768B1 (en) | 2000-12-09 | 2003-03-03 | 엘지전자 주식회사 | Apparatus for controling a frequency of bus clock in portable computer |
US6715094B2 (en) * | 2000-12-20 | 2004-03-30 | Intel Corporation | Mult-mode I/O interface for synchronizing selected control patterns into control clock domain to obtain interface control signals to be transmitted to I/O buffers |
US8095370B2 (en) | 2001-02-16 | 2012-01-10 | Agiletv Corporation | Dual compression voice recordation non-repudiation system |
AU2002324959A1 (en) * | 2001-09-07 | 2003-03-24 | Microsemi Corporation | Serial data interface with reduced power consumption |
US6959398B2 (en) * | 2001-12-31 | 2005-10-25 | Hewlett-Packard Development Company, L.P. | Universal asynchronous boundary module |
US8219736B2 (en) * | 2002-02-12 | 2012-07-10 | Ati Technologies Ulc | Method and apparatus for a data bridge in a computer system |
US6898725B2 (en) * | 2002-03-27 | 2005-05-24 | International Business Machines Corporation | Method for adjusting system clocks using dynamic clock ratio detector to detect clock ratio between clock domain of driver and counting receiver clock domain |
JP4159415B2 (en) * | 2002-08-23 | 2008-10-01 | エルピーダメモリ株式会社 | Memory module and memory system |
JP2004112182A (en) * | 2002-09-17 | 2004-04-08 | Fuji Xerox Co Ltd | Communication terminal and control method thereof |
US7324589B2 (en) * | 2003-02-05 | 2008-01-29 | Fujitsu Limited | Method and system for providing error compensation to a signal using feedback control |
US7313210B2 (en) * | 2003-02-28 | 2007-12-25 | Hewlett-Packard Development Company, L.P. | System and method for establishing a known timing relationship between two clock signals |
US20040193931A1 (en) * | 2003-03-26 | 2004-09-30 | Akkerman Ryan L. | System and method for transferring data from a first clock domain to a second clock domain |
US7275171B2 (en) * | 2003-05-22 | 2007-09-25 | Rambus Inc. | Method and apparatus for programmable sampling clock edge selection |
EP1515271A1 (en) * | 2003-09-09 | 2005-03-16 | STMicroelectronics S.r.l. | Method and device for extracting a subset of data from a set of data |
US7657689B1 (en) * | 2003-10-07 | 2010-02-02 | Altera Corporation | Methods and apparatus for handling reset events in a bus bridge |
FR2870368B1 (en) * | 2004-01-27 | 2006-12-15 | Atmel Corp | METHOD AND DEVICE FOR DRIVING MULTIPLE PERIPHERALS WITH DIFFERENT CLOCK FREQUENCIES IN AN INTEGRATED CIRCUIT |
US20060023819A1 (en) * | 2004-07-29 | 2006-02-02 | Adkisson Richard W | Clock synchronizer |
US7436917B2 (en) * | 2004-07-29 | 2008-10-14 | Hewlett-Packard Development Company, L.P. | Controller for clock synchronizer |
US8660647B2 (en) * | 2005-07-28 | 2014-02-25 | Cyberonics, Inc. | Stimulating cranial nerve to treat pulmonary disorder |
US7614737B2 (en) * | 2005-12-16 | 2009-11-10 | Lexmark International Inc. | Method for identifying an installed cartridge |
KR20070114557A (en) * | 2006-05-29 | 2007-12-04 | 삼성전자주식회사 | Semiconductor memory devices having fuses and methods of forming the same |
US7801208B2 (en) * | 2006-05-30 | 2010-09-21 | Fujitsu Limited | System and method for adjusting compensation applied to a signal using filter patterns |
US7764757B2 (en) * | 2006-05-30 | 2010-07-27 | Fujitsu Limited | System and method for the adjustment of offset compensation applied to a signal |
US7848470B2 (en) * | 2006-05-30 | 2010-12-07 | Fujitsu Limited | System and method for asymmetrically adjusting compensation applied to a signal |
US7804921B2 (en) | 2006-05-30 | 2010-09-28 | Fujitsu Limited | System and method for decoupling multiple control loops |
US7787534B2 (en) * | 2006-05-30 | 2010-08-31 | Fujitsu Limited | System and method for adjusting offset compensation applied to a signal |
US7839955B2 (en) * | 2006-05-30 | 2010-11-23 | Fujitsu Limited | System and method for the non-linear adjustment of compensation applied to a signal |
US7817757B2 (en) * | 2006-05-30 | 2010-10-19 | Fujitsu Limited | System and method for independently adjusting multiple offset compensations applied to a signal |
US7817712B2 (en) * | 2006-05-30 | 2010-10-19 | Fujitsu Limited | System and method for independently adjusting multiple compensations applied to a signal |
US7804894B2 (en) | 2006-05-30 | 2010-09-28 | Fujitsu Limited | System and method for the adjustment of compensation applied to a signal using filter patterns |
US7760798B2 (en) * | 2006-05-30 | 2010-07-20 | Fujitsu Limited | System and method for adjusting compensation applied to a signal |
US7839958B2 (en) | 2006-05-30 | 2010-11-23 | Fujitsu Limited | System and method for the adjustment of compensation applied to a signal |
CN101617371B (en) | 2007-02-16 | 2014-03-26 | 莫塞德技术公司 | Non-volatile semiconductor memory having multiple external power supplies |
US7466247B1 (en) | 2007-10-04 | 2008-12-16 | Lecroy Corporation | Fractional-decimation signal processing |
US8781053B2 (en) * | 2007-12-14 | 2014-07-15 | Conversant Intellectual Property Management Incorporated | Clock reproducing and timing method in a system having a plurality of devices |
US8467486B2 (en) * | 2007-12-14 | 2013-06-18 | Mosaid Technologies Incorporated | Memory controller with flexible data alignment to clock |
US9197981B2 (en) * | 2011-04-08 | 2015-11-24 | The Regents Of The University Of Michigan | Coordination amongst heterogeneous wireless devices |
US9858322B2 (en) | 2013-11-11 | 2018-01-02 | Amazon Technologies, Inc. | Data stream ingestion and persistence techniques |
FR3029661B1 (en) * | 2014-12-04 | 2016-12-09 | Stmicroelectronics Rousset | METHODS OF TRANSMITTING AND RECEIVING A BINARY SIGNAL OVER A SERIAL LINK, ESPECIALLY FOR DETECTING THE TRANSMISSION SPEED, AND DEVICES THEREOF |
US9825730B1 (en) * | 2016-09-26 | 2017-11-21 | Dell Products, Lp | System and method for optimizing link performance with lanes operating at different speeds |
DE102019112447A1 (en) * | 2019-05-13 | 2020-11-19 | Jenoptik Optical Systems Gmbh | Method and evaluation unit for determining the point in time of an edge in a signal |
US11860685B2 (en) | 2021-10-29 | 2024-01-02 | Advanced Micro Devices, Inc. | Clock frequency divider circuit |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0273234A2 (en) * | 1986-12-20 | 1988-07-06 | Nokia Unterhaltungselektronik (Deutschland) GmbH | Data bus system for a serial data bus |
US5623522A (en) * | 1994-11-21 | 1997-04-22 | Yamaha Corporation | Asynchronous serial data receiving device |
US5909563A (en) * | 1996-09-25 | 1999-06-01 | Philips Electronics North America Corporation | Computer system including an interface for transferring data between two clock domains |
Family Cites Families (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3725793A (en) | 1971-12-15 | 1973-04-03 | Bell Telephone Labor Inc | Clock synchronization arrangement employing delay devices |
KR900001817B1 (en) | 1987-08-01 | 1990-03-24 | 삼성전자 주식회사 | Cmos input buffer with resistor |
JPH07114348B2 (en) | 1987-12-11 | 1995-12-06 | 日本電気株式会社 | Logic circuit |
JPH07120225B2 (en) | 1988-04-15 | 1995-12-20 | 富士通株式会社 | Semiconductor circuit device |
US4989175A (en) | 1988-11-25 | 1991-01-29 | Unisys Corp. | High speed on-chip clock phase generating system |
JP2559237Y2 (en) * | 1989-01-23 | 1998-01-14 | 旭光学工業株式会社 | Serial data sampling signal generator |
US5058132A (en) | 1989-10-26 | 1991-10-15 | National Semiconductor Corporation | Clock distribution system and technique |
JPH0377543U (en) * | 1989-11-28 | 1991-08-05 | ||
US5295257A (en) * | 1991-05-24 | 1994-03-15 | Alliedsignal Inc. | Distributed multiple clock system and a method for the synchronization of a distributed multiple system |
US5307381A (en) | 1991-12-27 | 1994-04-26 | Intel Corporation | Skew-free clock signal distribution network in a microprocessor |
GB2265283B (en) * | 1992-03-18 | 1995-10-25 | Crystal Semiconductor Corp | Resynchronization of a synchronous serial interface |
US5459855A (en) * | 1992-08-10 | 1995-10-17 | Hewlett-Packard Company | Frequency ratio detector for determining fixed frequency ratios in a computer system |
US5256994A (en) | 1992-09-21 | 1993-10-26 | Intel Corporation | Programmable secondary clock generator |
CA2124709C (en) * | 1993-08-24 | 1998-06-09 | Lee-Fang Wei | Reduced speed equalizer |
JP3402498B2 (en) * | 1993-12-24 | 2003-05-06 | パイオニア株式会社 | Automotive electronics |
US6112307A (en) * | 1993-12-30 | 2000-08-29 | Intel Corporation | Method and apparatus for translating signals between clock domains of different frequencies |
US5550780A (en) * | 1994-12-19 | 1996-08-27 | Cirrus Logic, Inc. | Two cycle asynchronous FIFO queue |
SE515563C2 (en) * | 1995-01-11 | 2001-08-27 | Ericsson Telefon Ab L M | data transmission system |
US6169772B1 (en) * | 1995-04-07 | 2001-01-02 | Via-Cyrix, Inc. | Stretching setup and hold times in synchronous designs |
US5825834A (en) * | 1995-10-13 | 1998-10-20 | Vlsi Technlogy, Inc. | Fast response system implementing a sampling clock for extracting stable clock information from a serial data stream with defined jitter characeristics and method therefor |
US5859881A (en) * | 1996-06-07 | 1999-01-12 | International Business Machines Corporation | Adaptive filtering method and apparatus to compensate for a frequency difference between two clock sources |
GB2315197B (en) * | 1996-07-11 | 2000-07-12 | Nokia Mobile Phones Ltd | Method and apparatus for system clock adjustment |
US6055645A (en) * | 1996-12-30 | 2000-04-25 | Intel Corporation | Method and apparatus for providing a clock signal to a processor |
GB2321351B (en) * | 1997-01-17 | 1999-03-10 | Paul Flood | System and method for data transfer across multiple clock domains |
US6061410A (en) * | 1997-02-27 | 2000-05-09 | Advanced Micro Devices | Frequency ratio estimation arrangement and method thereof |
US6202108B1 (en) * | 1997-03-13 | 2001-03-13 | Bull S.A. | Process and system for initializing a serial link between two integrated circuits comprising a parallel-serial port using two clocks with different frequencies |
KR100230451B1 (en) * | 1997-04-08 | 1999-11-15 | 윤종용 | Method of transceiving asynchronous serial data of digital signal processor |
JPH10322404A (en) * | 1997-05-19 | 1998-12-04 | Sharp Corp | Serial data communication method and system |
FR2764758B1 (en) * | 1997-06-12 | 1999-08-06 | Scm Schneider Microsysteme Mic | METHOD FOR AUTOMATIC MEASUREMENT OF THE TIME UNIT FOR COMMUNICATION DEVICES DEDICATED TO CHIP CARDS |
US6249555B1 (en) * | 1997-07-14 | 2001-06-19 | Grass Valley (Us) Inc. | Low jitter digital extraction of data from serial bitstreams |
US6000022A (en) * | 1997-10-10 | 1999-12-07 | Micron Technology, Inc. | Method and apparatus for coupling signals between two circuits operating in different clock domains |
US6269136B1 (en) * | 1998-02-02 | 2001-07-31 | Microunity Systems Engineering, Inc. | Digital differential analyzer data synchronizer |
US6260152B1 (en) * | 1998-07-30 | 2001-07-10 | Siemens Information And Communication Networks, Inc. | Method and apparatus for synchronizing data transfers in a logic circuit having plural clock domains |
US6128678A (en) * | 1998-08-28 | 2000-10-03 | Theseus Logic, Inc. | FIFO using asynchronous logic to interface between clocked logic circuits |
US6000107A (en) * | 1998-09-15 | 1999-12-14 | West; Stephen W. | Fastening device |
US6321342B1 (en) * | 1999-03-23 | 2001-11-20 | Lsi Logic Corporation | Method and apparatus for interfacing circuits that operate based upon different clock signals |
US6172540B1 (en) * | 1999-08-16 | 2001-01-09 | Intel Corporation | Apparatus for fast logic transfer of data across asynchronous clock domains |
US6327207B1 (en) * | 2001-04-09 | 2001-12-04 | Lsi Logic Corporation | Synchronizing data operations across a synchronization boundary between different clock domains using two-hot encoding |
-
1999
- 1999-08-31 US US09/386,650 patent/US6393502B1/en not_active Expired - Lifetime
- 1999-10-27 US US09/428,633 patent/US6505261B1/en not_active Expired - Lifetime
-
2000
- 2000-03-23 KR KR1020027002343A patent/KR100734528B1/en not_active IP Right Cessation
- 2000-03-23 EP EP00919559A patent/EP1214662B1/en not_active Expired - Lifetime
- 2000-03-23 DE DE60002589T patent/DE60002589T2/en not_active Expired - Lifetime
- 2000-03-23 JP JP2001520658A patent/JP4630512B2/en not_active Expired - Fee Related
- 2000-03-23 WO PCT/US2000/007695 patent/WO2001016773A1/en active IP Right Grant
-
2002
- 2002-03-11 US US10/095,019 patent/US6668292B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0273234A2 (en) * | 1986-12-20 | 1988-07-06 | Nokia Unterhaltungselektronik (Deutschland) GmbH | Data bus system for a serial data bus |
US5623522A (en) * | 1994-11-21 | 1997-04-22 | Yamaha Corporation | Asynchronous serial data receiving device |
US5909563A (en) * | 1996-09-25 | 1999-06-01 | Philips Electronics North America Corporation | Computer system including an interface for transferring data between two clock domains |
Also Published As
Publication number | Publication date |
---|---|
US20020090046A1 (en) | 2002-07-11 |
EP1214662A1 (en) | 2002-06-19 |
US6668292B2 (en) | 2003-12-23 |
KR20020064277A (en) | 2002-08-07 |
EP1214662B1 (en) | 2003-05-07 |
DE60002589T2 (en) | 2004-03-25 |
US6393502B1 (en) | 2002-05-21 |
JP4630512B2 (en) | 2011-02-09 |
DE60002589D1 (en) | 2003-06-12 |
KR100734528B1 (en) | 2007-07-03 |
US6505261B1 (en) | 2003-01-07 |
JP2003508956A (en) | 2003-03-04 |
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