WO2001013564A1 - Protocole de demande de repetition automatique - Google Patents

Protocole de demande de repetition automatique Download PDF

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Publication number
WO2001013564A1
WO2001013564A1 PCT/US2000/022814 US0022814W WO0113564A1 WO 2001013564 A1 WO2001013564 A1 WO 2001013564A1 US 0022814 W US0022814 W US 0022814W WO 0113564 A1 WO0113564 A1 WO 0113564A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
data block
segmented
corrupted
segmented data
Prior art date
Application number
PCT/US2000/022814
Other languages
English (en)
Inventor
Andreas Junghans
Original Assignee
Koninklijke Philips Electronics N.V.
Philips Semiconductors Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V., Philips Semiconductors Inc. filed Critical Koninklijke Philips Electronics N.V.
Priority to JP2001517741A priority Critical patent/JP2003507931A/ja
Priority to KR1020017004849A priority patent/KR20010090794A/ko
Priority to EP00959279A priority patent/EP1123599A1/fr
Publication of WO2001013564A1 publication Critical patent/WO2001013564A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1809—Selective-repeat protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1829—Arrangements specially adapted for the receiver end
    • H04L1/1835—Buffer management
    • H04L1/1845—Combining techniques, e.g. code combining

Abstract

La présente invention concerne une demande de répétition automatique de mémoire pour un taux d'erreur de trame amélioré dans un système de télécommunications radio amélioré numérique (DECT). Spécifiquement, un des modes de réalisation de cette invention comprend un procédé permettant d'améliorer l'efficacité de retransmission d'une trame de données dans un système de communications. Ce procédé consiste à recevoir une trame de données qui comprend un premier bloc de données segmenté et un second bloc de données segmenté. Par ailleurs, ce procédé consiste à déterminer si le premier bloc de données segmenté et le second bloc de données segmenté contiennent des données altérées. En réponse au premier bloc de données segmenté contenant les données altérées et au second bloc de données segmenté ne contenant pas les données altérées, ce procédé consiste également à mémoriser le second bloc de données dans une mémoire. De plus, en réponse au premier bloc de données segmenté contenant les données altérées, ce procédé consiste à demander la retransmission de la trame de données. Lorsque la retransmission du premier bloc de données segmenté ne contenant pas de données altérées est reçue, ce procédé procède consiste alors à combiner le premier bloc de données segmenté ne contenant pas les données altérées avec le second bloc de données segmenté ne contenant pas de données altérées.
PCT/US2000/022814 1999-08-19 2000-08-17 Protocole de demande de repetition automatique WO2001013564A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2001517741A JP2003507931A (ja) 1999-08-19 2000-08-17 自動繰り返し要求プロトコル
KR1020017004849A KR20010090794A (ko) 1999-08-19 2000-08-17 통신 시스템내에서 데이터 프레임의 재전송 효율을개선하는 방법 및 통신 장치
EP00959279A EP1123599A1 (fr) 1999-08-19 2000-08-17 Protocole de demande de repetition automatique

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US37788699A 1999-08-19 1999-08-19
US09/377,886 1999-08-19

Publications (1)

Publication Number Publication Date
WO2001013564A1 true WO2001013564A1 (fr) 2001-02-22

Family

ID=23490914

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/022814 WO2001013564A1 (fr) 1999-08-19 2000-08-17 Protocole de demande de repetition automatique

Country Status (5)

Country Link
EP (1) EP1123599A1 (fr)
JP (1) JP2003507931A (fr)
KR (1) KR20010090794A (fr)
CN (1) CN1327661A (fr)
WO (1) WO2001013564A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003019391A2 (fr) * 2001-08-24 2003-03-06 Intel Corporation Architecture entree/sortie generale, protocole et procedes associes destines a gerer l'integrite des donnees
KR100464493B1 (ko) * 2002-04-06 2005-01-03 엘지전자 주식회사 무선인터넷 데이터 전송 이동통신 시스템 및 그 운용방법
US7177971B2 (en) 2001-08-24 2007-02-13 Intel Corporation General input/output architecture, protocol and related methods to provide isochronous channels
US8218580B2 (en) 2008-07-15 2012-07-10 Intel Corporation Managing timing of a protocol stack
NO337216B1 (no) * 2001-09-17 2016-02-15 Interdigital Tech Corp Radioressurs kontrollservice dataenhetsmottak.
US9836424B2 (en) 2001-08-24 2017-12-05 Intel Corporation General input/output architecture, protocol and related methods to implement flow control

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4446338B2 (ja) * 2004-03-22 2010-04-07 ソニー・エリクソン・モバイルコミュニケーションズ株式会社 再送要求方法、無線通信システム、および受信機

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5440545A (en) * 1993-08-02 1995-08-08 Motorola, Inc. Packet delivery system
WO1998047256A2 (fr) * 1997-04-14 1998-10-22 Telecom Italia S.P.A. Dispositif et procede de transmission de signaux numeriques, en particulier, dans des systemes de type dect

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5440545A (en) * 1993-08-02 1995-08-08 Motorola, Inc. Packet delivery system
WO1998047256A2 (fr) * 1997-04-14 1998-10-22 Telecom Italia S.P.A. Dispositif et procede de transmission de signaux numeriques, en particulier, dans des systemes de type dect

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8566473B2 (en) 2001-08-24 2013-10-22 Intel Corporation General input/output architecture, protocol and related methods to implement flow control
US7177971B2 (en) 2001-08-24 2007-02-13 Intel Corporation General input/output architecture, protocol and related methods to provide isochronous channels
WO2003019391A2 (fr) * 2001-08-24 2003-03-06 Intel Corporation Architecture entree/sortie generale, protocole et procedes associes destines a gerer l'integrite des donnees
US9049125B2 (en) 2001-08-24 2015-06-02 Intel Corporation General input/output architecture, protocol and related methods to implement flow control
US8819306B2 (en) 2001-08-24 2014-08-26 Intel Corporation General input/output architecture with PCI express protocol with credit-based flow control
US7231486B2 (en) 2001-08-24 2007-06-12 Intel Corporation General input/output architecture, protocol and related methods to support legacy interrupts
US7353313B2 (en) 2001-08-24 2008-04-01 Intel Corporation General input/output architecture, protocol and related methods to manage data integrity
CN100409606C (zh) * 2001-08-24 2008-08-06 英特尔公司 管理数据完整性的通用输入/输出体系结构、协议和方法
US7536473B2 (en) 2001-08-24 2009-05-19 Intel Corporation General input/output architecture, protocol and related methods to implement flow control
US9860173B2 (en) 2001-08-24 2018-01-02 Intel Corporation General input/output architecture, protocol and related methods to implement flow control
US9836424B2 (en) 2001-08-24 2017-12-05 Intel Corporation General input/output architecture, protocol and related methods to implement flow control
WO2003019391A3 (fr) * 2001-08-24 2003-05-30 Intel Corp Architecture entree/sortie generale, protocole et procedes associes destines a gerer l'integrite des donnees
US7152128B2 (en) 2001-08-24 2006-12-19 Intel Corporation General input/output architecture, protocol and related methods to manage data integrity
US9071528B2 (en) 2001-08-24 2015-06-30 Intel Corporation General input/output architecture, protocol and related methods to implement flow control
US9088495B2 (en) 2001-08-24 2015-07-21 Intel Corporation General input/output architecture, protocol and related methods to implement flow control
US9736071B2 (en) 2001-08-24 2017-08-15 Intel Corporation General input/output architecture, protocol and related methods to implement flow control
US9565106B2 (en) 2001-08-24 2017-02-07 Intel Corporation General input/output architecture, protocol and related methods to implement flow control
US9602408B2 (en) 2001-08-24 2017-03-21 Intel Corporation General input/output architecture, protocol and related methods to implement flow control
NO337216B1 (no) * 2001-09-17 2016-02-15 Interdigital Tech Corp Radioressurs kontrollservice dataenhetsmottak.
KR100464493B1 (ko) * 2002-04-06 2005-01-03 엘지전자 주식회사 무선인터넷 데이터 전송 이동통신 시스템 및 그 운용방법
US8218580B2 (en) 2008-07-15 2012-07-10 Intel Corporation Managing timing of a protocol stack

Also Published As

Publication number Publication date
EP1123599A1 (fr) 2001-08-16
CN1327661A (zh) 2001-12-19
KR20010090794A (ko) 2001-10-19
JP2003507931A (ja) 2003-02-25

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